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pulley: Get f{32,64}_bitwise.wast tests working (#9814)
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Fill out some more misc float ops.

cc #9783
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alexcrichton authored Dec 13, 2024
1 parent d68cb17 commit c18ca21
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Showing 4 changed files with 42 additions and 4 deletions.
10 changes: 10 additions & 0 deletions cranelift/codegen/src/isa/pulley_shared/lower.isle
Original file line number Diff line number Diff line change
Expand Up @@ -644,3 +644,13 @@

(rule (lower (has_type $F32 (sqrt a))) (pulley_fsqrt32 a))
(rule (lower (has_type $F64 (sqrt a))) (pulley_fsqrt64 a))

;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(rule (lower (has_type $F32 (fneg a))) (pulley_fneg32 a))
(rule (lower (has_type $F64 (fneg a))) (pulley_fneg64 a))

;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(rule (lower (has_type $F32 (fabs a))) (pulley_fabs32 a))
(rule (lower (has_type $F64 (fabs a))) (pulley_fabs64 a))
4 changes: 0 additions & 4 deletions crates/wast-util/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -428,10 +428,6 @@ impl WastTest {
"misc_testsuite/winch/_simd_load.wast",
"misc_testsuite/winch/_simd_multivalue.wast",
"misc_testsuite/winch/_simd_store.wast",
"spec_testsuite/f32_bitwise.wast",
"spec_testsuite/f64_bitwise.wast",
"spec_testsuite/float_exprs.wast",
"spec_testsuite/float_misc.wast",
"spec_testsuite/proposals/annotations/simd_lane.wast",
"spec_testsuite/proposals/multi-memory/simd_memory-multi.wast",
"spec_testsuite/proposals/relaxed-simd/i16x8_relaxed_q15mulr_s.wast",
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24 changes: 24 additions & 0 deletions pulley/src/interp.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2242,6 +2242,18 @@ impl OpVisitor for Interpreter<'_> {
ControlFlow::Continue(())
}

fn fneg32(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
let a = self.state[src].get_f32();
self.state[dst].set_f32(-a);
ControlFlow::Continue(())
}

fn fabs32(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
let a = self.state[src].get_f32();
self.state[dst].set_f32(a.wasm_abs());
ControlFlow::Continue(())
}

fn fadd64(&mut self, operands: BinaryOperands<FReg>) -> ControlFlow<Done> {
let a = self.state[operands.src1].get_f64();
let b = self.state[operands.src2].get_f64();
Expand Down Expand Up @@ -2313,6 +2325,18 @@ impl OpVisitor for Interpreter<'_> {
self.state[dst].set_f64(a.wasm_sqrt());
ControlFlow::Continue(())
}

fn fneg64(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
let a = self.state[src].get_f64();
self.state[dst].set_f64(-a);
ControlFlow::Continue(())
}

fn fabs64(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
let a = self.state[src].get_f64();
self.state[dst].set_f64(a.wasm_abs());
ControlFlow::Continue(())
}
}

impl ExtendedOpVisitor for Interpreter<'_> {
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8 changes: 8 additions & 0 deletions pulley/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -505,6 +505,10 @@ macro_rules! for_each_op {
fnearest32 = Fnearest32 { dst: FReg, src: FReg };
/// `low32(dst) = ieee_sqrt(low32(src))`
fsqrt32 = Fsqrt32 { dst: FReg, src: FReg };
/// `low32(dst) = -low32(src)`
fneg32 = Fneg32 { dst: FReg, src: FReg };
/// `low32(dst) = |low32(src)|`
fabs32 = Fabs32 { dst: FReg, src: FReg };

/// `dst = src1 + src2`
fadd64 = Fadd64 { operands: BinaryOperands<FReg> };
Expand All @@ -528,6 +532,10 @@ macro_rules! for_each_op {
fnearest64 = Fnearest64 { dst: FReg, src: FReg };
/// `dst = ieee_sqrt(src)`
fsqrt64 = Fsqrt64 { dst: FReg, src: FReg };
/// `dst = -src`
fneg64 = Fneg64 { dst: FReg, src: FReg };
/// `dst = |src|`
fabs64 = Fabs64 { dst: FReg, src: FReg };
}
};
}
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