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submission_form.txt
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Team name: Benjamin Devlin
Expected result (avg ns/square): 46ns/sq (3 clocks @ 65MHz)
Design documentation (below):
- Implemented Montgomery multiplication algorithm (chose not to do Barret reduction algorithm as then we need to use subtraction and that makes redundant bit form a bit more complicated)
- One modular multiplication in Montgomery space takes 3 clock cycles
- No reason to pipeline further as no resource sharing, saves on clock power, allows us to do carry propagation if needed in one clock cycle
- One squaring, one multiplication where we mask away the upper half, one multiplication with addition where we shift away the lower half
- We do not require the final check to see if we are larger than the modulus due to increasing the number of words used by 1 in the multiplier
- Final addition step is combined into the multiplier adder tree to save a clock cycle
- Uses log3 adders for shorter critical path / less LUT usage
- If we detect possible overflow on the boundary on any of the 3 multiplications, we will equalize the result so there are no carries in the lower words, adding 2 clock cycles each time this is detected
- Redundant binary representation of 17 bits for a 16 bit word
- Created a multi-mode multiplier that uses 2272 DSPs to fit on one SLR (2280)
- Uses control to select what mode (square / lower half / upper half), control signals one-hot
- Calculates 2 additional words past the shift/mask boundary so that we can detect possible overflow and correct result
- MMCM PLL to get desired clock frequency
- Clock crossing done in wrapper using per-word FIFOs
- Conversion in and out of Montgomery form is done in the SW wrapper in Squarer.hpp pack/unpack functions (inside timer)
- Added seed so that we can try different builds, 16 bits gets shifted out in unpack function
- Software model in System Verilog is in the package file src/rtl/redun_mont_pkg.sv and Python version in scripts/mont.py
- All files are in /redun_mont/ directory
- Self checking testbenches in /tb/
- /synth/ folder was used when doing local builds to check timing