Ambarella support #63
Description
Hi @rgantois ,
I'm finishing support for Ambarella SoC (aarch64, used mostly by DJI, GoPro and other in the past). Just want to make sure where it should land:
- Set BOOT pin, release RST, let BootROM create USB device
- Send commands to initialize the DRAM controller over the board (see the attached file) <- Snagrecovery
- Download the bootloader binary to the DRAM and pass execution to the binary (see the attached file) <- Snagrecovery
- Use Amboot protocol to flash the payload to NAND/eMMC/NOR flash memory.
This is how the DRAM init file looks like (hard to understand what it does without datasheet):
# Init DRAM controller...
# Programming PLL DDR REGs
write 0xed0800dc,0x21100000
write 0xed080110,0x3f770000
write 0xed080114,0x00068304
write 0xed0800dc,0x21100001
write 0xed0800dc,0x21100000
usleep 1000
# Programming DDRIO0 DLL REGs
write 0xdffe0900,0x00202020
write 0xdffe0904,0x00202020
write 0xdffe0908,0x00202020
write 0xdffe090c,0x00202020
write 0xdffe0920,0x0041b9b1
write 0xdffe0924,0x0041b9b1
write 0xdffe0928,0x0041b9b1
write 0xdffe092c,0x0041b9b1
write 0xdffe0910,0x12e50000
write 0xdffe0940,0x0000b041
write 0xdffe0944,0x0000b041
write 0xdffe0948,0x0000b041
write 0xdffe094c,0x0000b041
write 0xdffe08b4,0x00000000
write 0xdffe0800,0x6ec01a00
usleep 2000
write 0xdffe0818,0x00000008
poll 0xdffe0818,0x00000008,0x00000000
write 0xdffe0824,0x00001ce0
write 0xdffe0804,0x702822b8
write 0xdffe0808,0x243038c4
write 0xdffe080c,0x1050e46a
write 0xdffe0810,0x00000061
write 0xdffe0814,0x10143a0f
write 0xdffe0844,0x00000000
write 0xdffe0828,0x00020031
write 0xdffe0848,0x090c990c
write 0xdffe084c,0x0094c000
write 0xdffe0834,0x000000e4
write 0xdffe08a4,0xc2e5cb97
write 0xdffe082c,0x00000060
write 0xdffe08cc,0x00000034
usleep 1000
write 0xdffe0800,0x6ec01a08
usleep 1000
write 0xdffe0800,0x6ec01a0c
usleep 1000
write 0xdffe081c,0x010d0000
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x01030031
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x01020011
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x01010094
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x010b0000
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x010e0010
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x010c0014
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x010d0040
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x01030031
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x01020011
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x01010094
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x010b0000
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x010e0010
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe081c,0x010c0014
poll 0xdffe081c,0x80000000,0x00000000
write 0xdffe0800,0x2ec01a0c
write 0xdffe0818,0x00000010
poll 0xdffe0818,0x00000010,0x00000000
write 0xdffe0800,0x4ec01a0c
write 0xdffe0818,0x00000010
poll 0xdffe0818,0x00000010,0x00000000
write 0xdffe0800,0x6ec01a0c
usleep 1000
write 0xdffe0818,0x00000020
poll 0xdffe0818,0x00000020,0x00000000
write 0xdffe0818,0x00000004
poll 0xdffe0818,0x00000004,0x00000000
write 0xdffe0824,0x00001c40
write 0xdffe082c,0x00000060
write 0xdffe083c,0x001e3204
write 0xdffe0820,0x00000001
write 0xdffe0838,0x00000030
write 0xdffe0800,0x6ec01a0f
# DRAM controller is initialized...