diff --git a/bittide-cpus/data/Riscv32imc0.scala b/bittide-cpus/data/Riscv32imc0.scala
index 846ed48b4..87337c303 100644
--- a/bittide-cpus/data/Riscv32imc0.scala
+++ b/bittide-cpus/data/Riscv32imc0.scala
@@ -44,7 +44,7 @@ object Riscv32imc0 extends App {
         ),
 
         new CsrPlugin(
-            CsrPluginConfig.smallest.copy(
+            CsrPluginConfig.all.copy(
               ebreakGen = true,
               mtvecAccess = CsrAccess.READ_WRITE,
               withPrivilegedDebug = true
diff --git a/bittide-cpus/data/Riscv32imc1.scala b/bittide-cpus/data/Riscv32imc1.scala
index 20548229e..bd949067e 100644
--- a/bittide-cpus/data/Riscv32imc1.scala
+++ b/bittide-cpus/data/Riscv32imc1.scala
@@ -44,7 +44,7 @@ object Riscv32imc1 extends App {
         ),
 
         new CsrPlugin(
-            CsrPluginConfig.smallest.copy(
+            CsrPluginConfig.all.copy(
               ebreakGen = true,
               mtvecAccess = CsrAccess.READ_WRITE,
               withPrivilegedDebug = true
diff --git a/bittide-cpus/data/Riscv32imc2.scala b/bittide-cpus/data/Riscv32imc2.scala
index 3e57f1238..38f1d8597 100644
--- a/bittide-cpus/data/Riscv32imc2.scala
+++ b/bittide-cpus/data/Riscv32imc2.scala
@@ -44,7 +44,7 @@ object Riscv32imc2 extends App {
         ),
 
         new CsrPlugin(
-            CsrPluginConfig.smallest.copy(
+            CsrPluginConfig.all.copy(
               ebreakGen = true,
               mtvecAccess = CsrAccess.READ_WRITE,
               withPrivilegedDebug = true
diff --git a/bittide-cpus/data/Riscv32imc3.scala b/bittide-cpus/data/Riscv32imc3.scala
index 90628fdce..420d626f5 100644
--- a/bittide-cpus/data/Riscv32imc3.scala
+++ b/bittide-cpus/data/Riscv32imc3.scala
@@ -44,7 +44,7 @@ object Riscv32imc3 extends App {
         ),
 
         new CsrPlugin(
-            CsrPluginConfig.smallest.copy(
+            CsrPluginConfig.all.copy(
               ebreakGen = true,
               mtvecAccess = CsrAccess.READ_WRITE,
               withPrivilegedDebug = true