diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SoftUgnDemo/Core.hs b/bittide-instances/src/Bittide/Instances/Hitl/SoftUgnDemo/Core.hs
index 7f5002d4b..51694bb3a 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/SoftUgnDemo/Core.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/SoftUgnDemo/Core.hs
@@ -11,6 +11,7 @@ import Bittide.Calendar (CalendarConfig (..), ValidEntry (..))
 import Bittide.CaptureUgn (captureUgn)
 import Bittide.ClockControl (SpeedChange)
 import Bittide.ClockControl.CallistoSw (SwcccInternalBusses, callistoSwClockControlC)
+import Bittide.Counter (counterSource)
 import Bittide.DoubleBufferedRam (wbStorage)
 import Bittide.ElasticBuffer (xilinxElasticBufferWb)
 import Bittide.Instances.Domains (Basic125, Bittide, GthRx)
@@ -238,7 +239,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
 
     let
       maybeDna = readDnaPortE2 bitClk bitRst bitEna simDna2
-      localCounter = register bitClk bitRst bitEna 0 (localCounter + 1)
+      localCounter = counterSource d3 bitClk bitRst
 
     -- Start management unit
     (muUartBytesBittide, muWbAll) <-
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwitchDemo/Core.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwitchDemo/Core.hs
index f90031dba..5ab0e1868 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/SwitchDemo/Core.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/SwitchDemo/Core.hs
@@ -11,6 +11,7 @@ import Bittide.Calendar (CalendarConfig (..), ValidEntry (..))
 import Bittide.CaptureUgn (captureUgn)
 import Bittide.ClockControl (SpeedChange)
 import Bittide.ClockControl.CallistoSw (SwcccInternalBusses, callistoSwClockControlC)
+import Bittide.Counter (counterSource)
 import Bittide.DoubleBufferedRam (wbStorage)
 import Bittide.ElasticBuffer (xilinxElasticBufferWb)
 import Bittide.Instances.Domains (Basic125, Bittide, GthRx)
@@ -197,7 +198,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
 
     let
       maybeDna = readDnaPortE2 bitClk bitRst bitEna simDna2
-      localCounter = register bitClk bitRst bitEna 0 (localCounter + 1)
+      localCounter = counterSource d3 bitClk bitRst
 
     -- Start management unit
     (muUartBytesBittide, muWbAll) <-
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwitchDemoGppe/Core.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwitchDemoGppe/Core.hs
index f1ee25a27..9fa2748f6 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/SwitchDemoGppe/Core.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/SwitchDemoGppe/Core.hs
@@ -11,6 +11,7 @@ import Bittide.Calendar (CalendarConfig (..), ValidEntry (..))
 import Bittide.CaptureUgn (captureUgn)
 import Bittide.ClockControl (SpeedChange)
 import Bittide.ClockControl.CallistoSw (SwcccInternalBusses, callistoSwClockControlC)
+import Bittide.Counter (counterSource)
 import Bittide.DoubleBufferedRam (wbStorage)
 import Bittide.ElasticBuffer (xilinxElasticBufferWb)
 import Bittide.Instances.Domains (Basic125, Bittide, GthRx)
@@ -265,7 +266,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
 
     let
       maybeDna = readDnaPortE2 bitClk bitRst bitEna simDna2
-      localCounter = register bitClk bitRst bitEna 0 (localCounter + 1)
+      localCounter = counterSource d3 bitClk bitRst
 
     -- Start management unit
     (muUartBytesBittide, muWbAll) <-
diff --git a/bittide/src/Bittide/Counter.hs b/bittide/src/Bittide/Counter.hs
index fc8b0efa3..e9940847b 100644
--- a/bittide/src/Bittide/Counter.hs
+++ b/bittide/src/Bittide/Counter.hs
@@ -4,6 +4,7 @@
 
 module Bittide.Counter (
   Active,
+  counterSource,
   domainDiffCounter,
   domainDiffCountersWbC,
 ) where
@@ -227,3 +228,21 @@ extendSuccCounter clk rst counterLower =
    where
     m1 = if overflow then m0 + 1 else m0
     n1 = concatUnsigneds m1 n0
+
+{- | Counter source for bittide systems that contains a counter whose result has been delayed
+by @d@ cycles to improve timing for distribution across the design.
+TODO: Should we set the inital contents such that its indistinguishable from a normal freerunning counter?
+-}
+counterSource ::
+  forall dom d n.
+  (KnownDomain dom, KnownNat d, KnownNat n) =>
+  SNat d ->
+  Clock dom ->
+  Reset dom ->
+  Signal dom (Unsigned n)
+counterSource d clk rst = cntDelayed
+ where
+  cnt = register clk rst enableGen 0 (cnt + 1)
+  cntDelayed = applyN (snatToNum d :: Int) cnt
+  applyN 0 x = x
+  applyN n x = applyN (n - 1) (dflipflop clk x)