WIP

Author: hiddemoll

bittide/tests/Tests/ProgrammableMux.hs

@@ -11,6 +11,7 @@ import Protocols
 import Bittide.ProgrammableMux (programmableMux)
 import Bittide.SharedTypes (withByteOrderings)
 import Clash.Class.BitPackC (ByteOrder (..))
+import Clash.Class.BitPackC.Padding (packWordC)
 import Data.Maybe (fromJust)
 import Protocols.Hedgehog (defExpectOptions)
 import Protocols.MemoryMap
@@ -54,10 +55,11 @@ because we use a bus datawidth of 64 bits instead of the usual 32 bits.
 prop_ProgrammableMux :: Property
 prop_ProgrammableMux = H.property $ do
   switchCycle <- H.forAll $ genUnsigned @64 (Range.linear 100 200)
+  busByteOrder <- H.forAll $ Gen.element [BigEndian, LittleEndian]
   regByteOrder <- H.forAll $ Gen.element [BigEndian, LittleEndian]
   let
     dut =
-      withByteOrderings BigEndian regByteOrder
+      withByteOrderings busByteOrder regByteOrder
         $ withClockResetEnable @System clockGen resetGen enableGen
         $ circuit
         $ \wb -> do
@@ -76,8 +78,8 @@ prop_ProgrammableMux = H.property $ do
     counterAddr = fromIntegral (fromJust counterLoc).value.address `div` 8
     armAddr = fromIntegral (fromJust armLoc).value.address `div` 8
 
-    switchCycleBv = pack switchCycle
-    armBv = resize $ pack True
+    switchCycleBv = pack $ packWordC @8 busByteOrder switchCycle
+    armBv = pack $ packWordC @8 busByteOrder True
     requests = fmap (,0) [Write counterAddr maxBound switchCycleBv, Write armAddr maxBound armBv]
 
     (resets, outLink) =