Bump clash-compiler hash

Author: lmbollen

bittide/src/Bittide/ClockControl/Topology/LinkMasks.hs

@@ -28,7 +28,7 @@ type MaskConstraints nNodes nLinks =
 
 linkMasks ::
   forall nNodes nLinks.
-  (MaskConstraints nNodes nLinks) =>
+  (MaskConstraints nNodes nLinks, NumConvert (Index nNodes) Int) =>
   Vec nNodes (Vec nLinks (Index nNodes)) ->
   Topology ->
   Vec nNodes (BitVector nLinks)
@@ -44,7 +44,7 @@ linkMasks setup topology
 
 -- | Determines whether a link is active for a given FPGA and topology.
 isActiveLink ::
-  (MaskConstraints nNodes nLinks) =>
+  (MaskConstraints nNodes nLinks, NumConvert (Index nNodes) Int) =>
   Vec nNodes (Vec nLinks (Index nNodes)) ->
   Topology ->
   Index nNodes ->
@@ -86,7 +86,7 @@ setup =
 -}
 linkMask ::
   forall nNodes nLinks.
-  (MaskConstraints nNodes nLinks) =>
+  (MaskConstraints nNodes nLinks, NumConvert (Index nNodes) Int) =>
   Vec nNodes (Vec nLinks (Index nNodes)) ->
   Topology ->
   Index nNodes ->

bittide/src/Bittide/DoubleBufferedRam.hs

@@ -515,23 +515,3 @@ splitWriteInBytes (Just (addr, writeData)) byteSelect =
   case getRegsBe writeData of
     RegisterBank vec -> orNothing <$> unpack byteSelect <*> fmap (addr,) vec
 splitWriteInBytes Nothing _ = repeat Nothing
-
-{- | Takes an address and write operation and 'bitCoerce's the addresses as follows:
-'bitCoerce' (address, bool)
--}
-updateAddrs ::
-  (KnownNat n, 1 <= n, KnownNat m, 1 <= m) =>
-  -- | An address.
-  Index n ->
-  -- | A write operation.
-  Maybe (Index m, b) ->
-  -- | A boolean that will be used for the addresses LSBs.
-  AorB ->
-  -- |
-  --   1. Updated address
-  --   2. Write operation with updated address.
-  (Index (n * 2), Maybe (Index (m * 2), b))
-updateAddrs rdAddr (Just (i, a)) bufSelect =
-  (mul2Index rdAddr bufSelect, Just (mul2Index i (swapAorB bufSelect), a))
-updateAddrs rdAddr Nothing bufSelect =
-  (mul2Index rdAddr bufSelect, Nothing)

bittide/src/Bittide/SharedTypes.hs

@@ -15,7 +15,6 @@ import Clash.Prelude
 import Clash.Class.BitPackC (ByteOrder (..), Bytes)
 import Data.Constraint
 import Data.Constraint.Nat.Lemmas
-import Data.Type.Equality ((:~:) (Refl))
 import Protocols (ToConstBwd)
 import Protocols.MemoryMap (Mm)
 import Protocols.Wishbone
@@ -154,24 +153,13 @@ getDataLe (RegisterBank (reverse -> vec)) =
   case timesDivRU @bw @(BitSize a) of
     Dict -> unpack . snd $ split @_ @(Pad a bw) @(BitSize a) (pack vec)
 
-{- | Coerces a tuple of index n and a boolean to index (n*2) where the LSB of the result
-is determined by the boolean.
--}
-mul2Index ::
-  forall n b.
-  (KnownNat n, 1 <= n, BitPack b, BitSize b ~ 1) =>
-  Index n ->
-  b ->
-  Index (n * 2)
-mul2Index n b = case clogProductRule @n of Refl -> bitCoerce (n, b)
-
 -- | Coerces an index of size (n*2) to index n with the LSB as separate boolean.
 div2Index ::
-  forall n b.
-  (KnownNat n, 1 <= n, BitPack b, BitSize b ~ 1) =>
+  forall n.
+  (KnownNat n, 1 <= n) =>
   Index (n * 2) ->
-  (Index n, b)
-div2Index = case clogProductRule @n of Refl -> bitCoerce
+  (Index n, Bool)
+div2Index idx = (resize (idx `shiftR` 1), lsb idx == 1)
 
 -- | Delays the output controls to align them with the actual read / write timing.
 delayControls ::

cabal.project

@@ -43,7 +43,7 @@ jobs: $ncpus
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-compiler.git
-  tag: 5ec337c04139f74dd706db77ccb25f92ad5dc3dc
+  tag: 83e906547b38a3d8bdeaf5ec839507f3478812fb
   subdir:
     clash-prelude
     clash-ghc