From bfef1bf4ffc51b0d977398aaf26974681d6ee151 Mon Sep 17 00:00:00 2001 From: Ikko Eltociear Ashimine Date: Thu, 7 Dec 2023 00:05:49 +0900 Subject: [PATCH] Update page.tsx wholy -> wholly --- src/app/cpu/guide/01-riscv-basic/page.tsx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/app/cpu/guide/01-riscv-basic/page.tsx b/src/app/cpu/guide/01-riscv-basic/page.tsx index beff4fe..20d992f 100644 --- a/src/app/cpu/guide/01-riscv-basic/page.tsx +++ b/src/app/cpu/guide/01-riscv-basic/page.tsx @@ -152,7 +152,7 @@ export default function Page() { The instruction decode component outputs a whole suite of control signals, which are routed to the various other components, telling them what to do. This component is also considered "combinatorial", meaning - its outputs are wholy determined by its inputs, and don't depend on any internal state. In contrast, + its outputs are wholly determined by its inputs, and don't depend on any internal state. In contrast, the register file is considered "sequential", because it has internal state (the values of the registers), and also integrates with the clock signal.