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Added multinode testbench
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‎README.md

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@@ -10,7 +10,7 @@ My main resource was the links in <https://tis100.complexity.nl/links.html>. Ias
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# Progress
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Currently this codebase can generate a Vivado project that can run behavioral simulations of a a T21 node. The node is functional and should be exactly faithful in behavior to the game implementation. The one missing feature is the that the virtual ports ANY and LAST aren't supported. While I think it's possible to implement their behavior, it would require a much more complicated design.
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Currently this codebase can generate a Vivado project that can run behavioral simulations of a grid of T21 nodes. The nodes are functional and should be exactly faithful in behavior to the game implementation. The one missing feature is the that the virtual ports ANY and LAST aren't supported. While I think it's possible to implement their behavior, it would require a much more complicated design.
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Here's the schematic for the code:
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@@ -22,7 +22,7 @@ In addition I've written a series of python scripts to aid in development and te
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* A basic emulator for running TIS code in Python
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* Tools for generating stimuli and verification data for the FPGA simulation unit tests
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The furthest test is running the following code in the full node:
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An example simulation is running the following code in a single node:
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```
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MOV UP ACC
@@ -39,6 +39,16 @@ Feeding in [5, 100] gives the output [50, 999] in the behavioral simulation. Her
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<a href="docs/mult_sim.png"><img src="docs/mult_sim.png"/></a>
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Another simulation is able to correctly solve the 6th puzzle in the game "Sequence Generator" using two nodes.
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The code and input:
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<a href="docs/sig_gen_ex.png"><img src="docs/sig_gen_ex.png"/></a>
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The first 7 outputs from the simulator:
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<a href="docs/sig_gen_sim.png"><img src="docs/sig_gen_sim.png"/></a>
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# Instruction Format
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I created my own binary representation of the TIS100 instructions. The format is (len in bits):
@@ -112,7 +122,7 @@ It can load the compiler output and prints the register state for each time tick
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# Next Steps
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- [ ] Connect multiple nodes together using top level design file
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- [x] Connect multiple nodes together using top level design file
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- [ ] Connect to ARM in Zynq SoC over AXI (use as co-processor)
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- [ ] Have ability to view contents, load code, input, output
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- [ ] Be able to wire up in Xilinx Block designer

‎data/seq_gen/seq_gen_ina.mem

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‎data/seq_gen/seq_gen_inb.mem

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‎data/seq_gen/seq_gen_node1.mem

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000101000000000000001
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000100100000000000101
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000100100000000000101

‎data/seq_gen/seq_gen_node1.p

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‎data/seq_gen/seq_gen_node1.tis

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MOV UP ACC
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MOV ACC RIGHT
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MOV ACC RIGHT

‎data/seq_gen/seq_gen_node2.mem

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000101000000000000001
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001100000000000000000
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010110000000000000000
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101000000000000101000
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001000000000000000000
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000100100000000000011
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000110000000000000011
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011100000000000100000
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000110000000000000011
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001000000000000000000
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000100100000000000011
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000100000000000000011

‎data/seq_gen/seq_gen_node2.p

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‎data/seq_gen/seq_gen_node2.tis

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MOV UP ACC
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SAV
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SUB LEFT
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JGZ B
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SWP
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MOV ACC DOWN
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MOV LEFT DOWN
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JMP END
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B: MOV LEFT DOWN
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SWP
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MOV ACC DOWN
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END: MOV 0 DOWN

‎data/seq_gen/seq_gen_result.mem

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‎docs/sig_gen_ex.png

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‎docs/sig_gen_sim.png

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‎scripts/gen_node_nets.py

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from enum import Enum, auto
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from typing import Tuple, List, Optional
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class NodeType(Enum):
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IN = auto()
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OUT = auto()
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NODE = auto()
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class WireType(Enum):
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IN = auto()
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OUT = auto()
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INOUT = auto()
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class Direction(Enum):
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RIGHT = auto()
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DOWN = auto()
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class Node:
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def __init__(self, name, type: NodeType):
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self.type = type
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self.name = name
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class Wire:
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def __init__(self, node, dir: Direction, other, type: WireType):
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self.type = type
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self.node = node
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self.dir = dir
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self.other = other
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def get_dir(dir):
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return {
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Direction.RIGHT: 'right',
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Direction.DOWN: 'down'
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}[dir]
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def get_op_dir(dir):
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return {
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Direction.RIGHT: 'left',
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Direction.DOWN: 'up'
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}[dir]
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def wire_write(a, b, dir):
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if (a.type == NodeType.IN or a.type == NodeType.OUT) and \
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(b.type == NodeType.IN or b.type == NodeType.OUT):
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return None
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if a.type == NodeType.IN or b.type == NodeType.OUT:
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return Wire(a.name, dir, b.name, WireType.OUT)
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elif a.type == NodeType.OUT or b.type == NodeType.IN:
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return Wire(a.name, dir, b.name, WireType.IN)
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else:
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return Wire(a.name, dir, b.name, WireType.INOUT)
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def print_assignments(wire: Wire):
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if wire is None:
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return
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if wire.type != WireType.IN:
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print(f'assign {wire.other}_{get_op_dir(wire.dir)}_in_data = {wire.node}_{get_dir(wire.dir)}_out_data;')
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print(f'assign {wire.other}_{get_op_dir(wire.dir)}_in_valid = {wire.node}_{get_dir(wire.dir)}_out_valid;')
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print(f'assign {wire.node}_{get_dir(wire.dir)}_out_ready = {wire.other}_{get_op_dir(wire.dir)}_in_ready;')
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if wire.type != WireType.OUT:
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print(f'assign {wire.node}_{get_dir(wire.dir)}_in_data = {wire.other}_{get_op_dir(wire.dir)}_out_data;')
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print(f'assign {wire.node}_{get_dir(wire.dir)}_in_valid = {wire.other}_{get_op_dir(wire.dir)}_out_valid;')
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print(f'assign {wire.other}_{get_op_dir(wire.dir)}_out_ready = {wire.node}_{get_dir(wire.dir)}_in_ready;')
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def main():
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in_a_stream = Node('in_a_stream', NodeType.IN)
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in_b_stream = Node('in_b_stream', NodeType.IN)
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out_stream = Node('out_stream', NodeType.OUT)
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node1 = Node('node1', NodeType.NODE)
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node2 = Node('node2', NodeType.NODE)
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nodes:List[List[Optional[Node]]] = [[in_a_stream, in_b_stream],
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[node1, node2],
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[None, out_stream]]
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wires: List[Wire] = []
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for r, row in enumerate(nodes):
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for c, node in enumerate(row):
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if node is None:
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continue
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if r + 1 < len(nodes) and nodes[r+1][c] is not None:
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wires.append(wire_write(node, nodes[r+1][c], Direction.DOWN))
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if c + 1 < len(row) and nodes[r][c+1] is not None:
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wires.append(wire_write(node, nodes[r][c+1], Direction.RIGHT))
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wire_segments = []
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for row in nodes:
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for node in row:
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if node is None:
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continue
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if node.type == NodeType.IN:
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for wire in wires:
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if wire is None:
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continue
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if wire.node == node.name:
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print(f'reg signed [10:0] {wire.node}_{get_dir(wire.dir)}_out_data;')
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print(f'reg {wire.node}_{get_dir(wire.dir)}_out_valid;')
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print(f'wire {wire.node}_{get_dir(wire.dir)}_out_ready;')
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print()
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elif wire.other == node.name:
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print(f'reg signed [10:0] {wire.other}_{get_dir(wire.dir)}_out_data;')
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print(f'reg {wire.other}_{get_op_dir(wire.dir)}_out_valid;')
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print(f'wire {wire.other}_{get_op_dir(wire.dir)}_out_ready;')
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print()
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elif node.type == NodeType.OUT:
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for wire in wires:
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if wire is None:
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continue
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if wire.node == node.name:
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print(f'wire signed [10:0] {wire.node}_{get_dir(wire.dir)}_in_data;')
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print(f'wire {wire.node}_{get_dir(wire.dir)}_in_valid;')
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print(f'reg {wire.node}_{get_dir(wire.dir)}_in_ready;')
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print()
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elif wire.other == node.name:
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print(f'wire signed [10:0] {wire.other}_{get_op_dir(wire.dir)}_in_data;')
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print(f'wire {wire.other}_{get_op_dir(wire.dir)}_in_valid;')
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print(f'reg {wire.other}_{get_op_dir(wire.dir)}_in_ready;')
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print()
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else:
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for wire in wires:
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if wire is None:
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continue
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if wire.node == node.name:
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if wire.type != WireType.OUT:
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wire_segments.append(f'{wire.node}_{get_dir(wire.dir)}_in')
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if wire.type != WireType.IN:
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wire_segments.append(f'{wire.node}_{get_dir(wire.dir)}_out')
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if node.name == wire.other:
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if wire.type != WireType.OUT:
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wire_segments.append(f'{wire.other}_{get_op_dir(wire.dir)}_out')
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if wire.type != WireType.IN:
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wire_segments.append(f'{wire.other}_{get_op_dir(wire.dir)}_in')
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for wire in wire_segments:
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print(f'wire [10:0] {wire}_data;')
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print(f'wire {wire}_valid;')
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print(f'wire {wire}_ready;')
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print()
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for wire in wires:
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print_assignments(wire)
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print()
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for row in nodes:
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for node in row:
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if node is None:
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continue
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if node.type == NodeType.NODE:
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for wire in wire_segments:
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if wire.startswith(node.name + '_'):
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sub = wire[len(node.name) + 1:]
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print(f'.{sub}_data({wire}_data),')
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print(f'.{sub}_valid({wire}_valid),')
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print(f'.{sub}_ready({wire}_ready),')
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print()
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if __name__ == "__main__":
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main()

‎scripts/run_tests.sh

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# xsim op_decode_tb_behav -key {Behavioral:sim_1:Functional:op_decode_tb} -tclbatch $SCRIPT_PATH/run_tests.tcl -log simulate1.log
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vivado -mode batch -source scripts/run_tests.tcl | tee simulation.log
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python scripts/check_sim_logs.py simulation.log 6
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python scripts/check_sim_logs.py simulation.log 7

‎scripts/run_tests.tcl

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set_property -name {xsim.simulate.runtime} -value {100us} -objects [get_filesets sim_1]
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set test_benches {"alu_tb" "op_decode_tb" "registers_tb" "instr_rom_tb" "dir_manager_tb" "t21_node_tb" }
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set test_benches {"alu_tb" "op_decode_tb" "registers_tb" "instr_rom_tb" "dir_manager_tb" "t21_node_tb" "t21_2_node_tb" }
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foreach test_bench $test_benches {
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set_property top $test_bench [get_filesets sim_1]

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