Changes to support release 1.2.2

Author: kristopk

FAQs.md

@@ -204,7 +204,7 @@ We encourage you to use the [AWS FPGA Developer Forum](https://forums.aws.amazon
 
 The required AWS software is the [FPGA Management Tool set](./sdk/userspace/fpga_mgmt_tools). This software manages loading and clearing AFIs for the instance FPGAs. It also allows developers to retrieve FPGAs status from within the instance. Users will need to load the F1 AMI with the drivers and runtime libraries needed for their FPGA application.
 
-Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope.
+Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope (Virtual JTAG).
 
 
 ## Marketplace
@@ -235,7 +235,7 @@ There are two types of interfaces from the instance host CPU to the FPGAs:
 
 The first is the FPGA Image Management Tools. These APIs are detailed in the [SDK portion](./sdk/userspace/fpga_mgmt_tools) of the GitHub repository. FPGA Image Management Tools include APIs to load, clear, and get status of the FPGA. 
 
-The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance.
+The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software (Virtual JTAG) uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance.
 
 
 
@@ -379,7 +379,7 @@ Yes. The HDK includes a simulation model for the AWS shell. See the [HDK common
 
 **Q: What resources within the FPGA does the AWS Shell consume?**
 
-The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
+The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope (Virtual JTAG) and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
 
 
 

RELEASE_NOTES.md

@@ -26,12 +26,17 @@
          *     1 DDR controller implemented in the SH (always available)
          *     3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
 
+# Release 1.2.1
+   *    Expanded [clock recipes](./hdk/docs/clock_recipes.csv) 
+   *    Virtual JTAG documentation updates
+   *    Included encryption of .sv files for CL examples
+
 # Release 1.2.1
    *    Updated CL example build scripts with Prohibit URAM sites 
    *    EDMA Performance improvments 
    *    Expanded EC2 Instance type support
    *    CL Examples @250Mhz (Clock recipe A1)
-   *    Option to exclude chipscope from building CL examples (DISABLE_CHIPSCOPE_DEBUG)
+   *    Option to exclude Chipscope (Virtual JTAG) from building CL examples (DISABLE_VJTAG_DEBUG)
 
 # Release 1.2.0
 

hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings

@@ -1 +1 @@
-152
+152

hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv

@@ -720,7 +720,7 @@ cl_sda_slv CL_SDA_SLV (
 //-----------------------------------------
 
 
-`ifndef DISABLE_CHIPSCOPE_DEBUG
+`ifndef DISABLE_VJTAG_DEBUG
 
 cl_ila CL_ILA (
 
@@ -751,7 +751,7 @@ cl_vio CL_VIO (
 );
 
 
-`endif //  `ifndef DISABLE_CHIPSCOPE_DEBUG
+`endif //  `ifndef DISABLE_VJTAG_DEBUG
 
 //----------------------------------------- 
 // Virtual JATG ILA Debug core example 

hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh

@@ -27,8 +27,8 @@
 //uncomment below to make SH and CL async
 `define SH_CL_ASYNC
 
-// Uncomment to disable Chipscope
-//`define DISABLE_CHIPSCOPE_DEBUG
+// Uncomment to disable Virtual JTAG
+//`define DISABLE_VJTAG_DEBUG
 
 `endif
 

hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f

@@ -49,7 +49,7 @@
 ${SH_LIB_DIR}/bram_2rw.sv
 ${SH_LIB_DIR}/flop_fifo.sv
 
-+define+DISABLE_CHIPSCOPE_DEBUG
++define+DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f

@@ -45,7 +45,7 @@
 ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
 ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
 
-+define+DISABLE_CHIPSCOPE_DEBUG
++define+DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f

@@ -47,7 +47,7 @@
 ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
 ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
 
---define DISABLE_CHIPSCOPE_DEBUG
+--define DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv

@@ -328,9 +328,9 @@ assign pre_cl_sh_status_vled[15:0] = vled_q[15:0] & sh_cl_status_vdip_q2[15:0];
   assign cl_sh_status1[31:0] = `CL_VERSION;
 
 //-----------------------------------------------
-// Debug bridge, used if need chipscope
+// Debug bridge, used if need Virtual JTAG
 //-----------------------------------------------
-`ifndef DISABLE_CHIPSCOPE_DEBUG
+`ifndef DISABLE_VJTAG_DEBUG
 
 // Flop for timing global clock counter
 logic[63:0] sh_cl_glcount0_q;
@@ -381,7 +381,7 @@ always_ff @(posedge clk_main_a0)
    );
 
 //-----------------------------------------------
-// VIO Example - Needs Chipscope
+// VIO Example - Needs Virtual JTAG
 //-----------------------------------------------
    // Counter running at 125MHz
 
@@ -465,7 +465,7 @@ always_ff @(posedge clk_main_a0)
                    .probe10 (vo_cnt_watermark_q)
                    );
 
-`endif //  `ifndef DISABLE_CHIPSCOPE_DEBUG
+`endif //  `ifndef DISABLE_VJTAG_DEBUG
 
 endmodule
 

hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh

@@ -23,7 +23,7 @@
 // FPGA flop init capability).  This will help with routing resources.
 `define FPGA_LESS_RST
 
-// Uncomment to disable Chipscope
-//`define DISABLE_CHIPSCOPE_DEBUG
+// Uncomment to disable Virtual JTAG
+//`define DISABLE_VJTAG_DEBUG
 
 `endif