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Release 1.2.1
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‎.gitignore

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@@ -52,3 +52,9 @@ hdk/common/verif/models/.vivado_version
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vivado_pid*.str
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vivado*.jou
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vivado*.log
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# Pycharm projects
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.idea/
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# Python compiled code
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*.pyc

‎RELEASE_NOTES.md

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* 1 DDR controller implemented in the SH (always available)
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* 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
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# Release 1.2.1
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* Updated CL example build scripts with Prohibit URAM sites
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* EDMA Performance improvments
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* Expanded EC2 Instance type support
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* CL Examples @250Mhz (Clock recipe A1)
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* Option to exclude chipscope from building CL examples (DISABLE_CHIPSCOPE_DEBUG)
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# Release 1.2.0
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‎hdk/cl/examples/README.md

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@@ -46,11 +46,18 @@ If you like to start your own CL, check out the [How to create your own CL](../d
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Executing the `aws_build_dcp_from_cl.sh` script will perform the entire implementation process converting the CL design into a completed Design Checkpoint that meets timing and placement constrains of the target FPGA.
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The output is a tarball file comprising the DCP file, and other log/manifest files, formatted as `YY_MM_DD-hhmm.Developer_CL.tar`.
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This file would be submitted to AWS to create an AFI.
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This file would be submitted to AWS to create an AFI. By default the build script will use Clock Group A Recipe A0 wich uses a main clock of 125 MHz.
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$ cd $CL_DIR/build/scripts
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$ ./aws_build_dcp_from_cl.sh
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In order to use a 250 MHz main clock the developer can specify the A1 Clock Group A Recipe as in the following example:
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$ cd $CL_DIR/build/scripts
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$ ./aws_build_dcp_from_cl.sh -clock_recipe_a A1
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Other clock recipes can be specified as well. More details on the [Clock Group Recipes Table](../../docs/clock_recipes.csv) and how to specify different recipes can be found in the following [README](../../common/shell_v04151701/new_cl_template/build/README.md).
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**NOTE**: *The DCP generation can take up to several hours to complete, hence the `aws_build_dcp_from_cl.sh` will run the main build process (`vivado`) in within a `nohup` context: This will allow the build to continue running even if the SSH session is terminated half way through the run*
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To be notified via e-mail when the build completes:

‎hdk/cl/examples/cl_dram_dma/build/constraints/cl_pnr_user.xdc

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@@ -38,14 +38,17 @@ add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical
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add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/SH_DDR/ddr_cores.DDR4_2*}]
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add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/SH_DDR/ddr_inst[2].*}]
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add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/SH_DDR/ddr_stat[2].*}]
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add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/CL_PCIM_MSTR/CL_TST_PCI}]
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#add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/CL_PCIM_MSTR/CL_TST_PCI}]
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add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells [list CL/CL_DMA_PCIS_SLV/PCI_AXL_REG_SLC CL/CL_PCIM_MSTR/PCI_AXI4_REG_SLC CL/CL_OCL_SLV/AXIL_OCL_REG_SLC CL/CL_SDA_SLV/AXIL_SDA_REG_SLC]]
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add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -hierarchical -filter { NAME =~ "*CL/CL_OCL_SLV/slv_tst_wdata_reg[*][*]*" && PRIMITIVE_TYPE =~ REGISTER.*.* }]
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resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y4}
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set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]
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set_clock_groups -name cl_main_a0_tck -asynchronous -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] -group [get_clocks tck]
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#set_clock_groups -name cl_main_a0_tck -asynchronous -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] -group [get_clocks tck]
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set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
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set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
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set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
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‎hdk/cl/examples/cl_dram_dma/build/constraints/cl_synth_user.xdc

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# This contains the CL specific constraints for synthesis at the CL level
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set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins CL/SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
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set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins CL/CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]
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‎hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings

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‎hdk/cl/examples/cl_dram_dma/build/scripts/.warnings

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‎hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl

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@@ -32,8 +32,7 @@ set subsystem_vendor_id [lindex $argv 7]
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set clock_recipe_a [lindex $argv 8]
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set clock_recipe_b [lindex $argv 9]
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set clock_recipe_c [lindex $argv 10]
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set run_aws_emulation [lindex $argv 11]
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set notify_via_sns [lindex $argv 12]
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set notify_via_sns [lindex $argv 11]
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##################################################
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### Implementation step options
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puts "Clock Recipe A: $clock_recipe_a";
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puts "Clock Recipe B: $clock_recipe_b";
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puts "Clock Recipe C: $clock_recipe_c";
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puts "Run AWS Emulation: $run_aws_emulation";
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puts "Notify when done: $notify_via_sns";
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#checking if CL_DIR env variable exists
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########################
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puts "AWS FPGA: Place design stage";
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# Constraints for TCK<->Main Clock
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set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
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set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
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set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
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switch $strategy {
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"BASIC" {
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puts "BASIC strategy."
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write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
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close_project
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# ################################################
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# Emulate AWS Bitstream Generation
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# ################################################
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# Only run AWS emulation step if explicitly specified.
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if {[string compare $run_aws_emulation "1"] == 0} {
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_dcp_verify.tcl to emulate AWS bitstream generation for checking the DCP.";
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source $HDK_SHELL_DIR/build/scripts/aws_dcp_verify.tcl
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}
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# ################################################
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# Create Manifest and Tarball for delivery
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# ################################################

‎hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh

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//uncomment below to make SH and CL async
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`define SH_CL_ASYNC
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// Uncomment to disable Chipscope
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//`define DISABLE_CHIPSCOPE_DEBUG
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`endif
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‎hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma.c

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fail_on(rc, out, "Interrupt example failed");
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out:
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return 1;
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return rc;
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}
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static int

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