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flattened.v
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/* Generated by Yosys 0.25+83 (git sha1 755b753e1, aarch64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os) */
/* top = 1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:4.1-18.10" */
module d22_yushuanl_convolution(io_in, io_out);
wire [2:0] _00_;
wire _01_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
wire _02_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
wire _03_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
wire _04_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
wire _05_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
wire _06_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
wire _07_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
wire _08_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
wire _09_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
wire _10_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:5.18-5.23" */
input [13:0] io_in;
wire [13:0] io_in;
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:6.19-6.25" */
output [13:0] io_out;
wire [13:0] io_out;
/* hdlname = "mchip Shifted_A" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:53.15-53.24" */
wire [5:0] \mchip.Shifted_A ;
/* hdlname = "mchip Shifted_B" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:53.26-53.35" */
wire [5:0] \mchip.Shifted_B ;
/* hdlname = "mchip add Out" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:24.23-24.26|d22_yushuanl_convolution/src/chip.sv:65.9-65.59" */
wire [3:0] \mchip.add.Out ;
/* hdlname = "mchip clock" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:49.10-49.15" */
wire \mchip.clock ;
/* enum_type = "$enum0" */
/* hdlname = "mchip curState" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:73.20-73.28" */
reg [2:0] \mchip.curState ;
/* hdlname = "mchip enRO" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:52.25-52.29" */
wire \mchip.enRO ;
/* hdlname = "mchip enRT" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:52.19-52.23" */
wire \mchip.enRT ;
/* hdlname = "mchip inReg" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:56.15-56.20" */
wire [3:0] \mchip.inReg ;
/* hdlname = "mchip io_in" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:48.23-48.28" */
wire [11:0] \mchip.io_in ;
/* hdlname = "mchip io_out" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:50.23-50.29" */
wire [3:0] \mchip.io_out ;
/* hdlname = "mchip mul First" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:15.16-15.21|d22_yushuanl_convolution/src/chip.sv:61.14-63.32" */
wire \mchip.mul.First ;
/* hdlname = "mchip mul Second" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:15.23-15.29|d22_yushuanl_convolution/src/chip.sv:61.14-63.32" */
wire \mchip.mul.Second ;
/* hdlname = "mchip mux A" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:30.22-30.23|d22_yushuanl_convolution/src/chip.sv:64.7-64.52" */
wire [3:0] \mchip.mux.A ;
/* hdlname = "mchip mux B" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:30.25-30.26|d22_yushuanl_convolution/src/chip.sv:64.7-64.52" */
wire [3:0] \mchip.mux.B ;
/* hdlname = "mchip oldSum" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:56.22-56.28" */
wire [3:0] \mchip.oldSum ;
/* hdlname = "mchip registerOut In" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:38.22-38.24|d22_yushuanl_convolution/src/chip.sv:67.7-67.69" */
wire [3:0] \mchip.registerOut.In ;
/* hdlname = "mchip registerOut Out" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:40.23-40.26|d22_yushuanl_convolution/src/chip.sv:67.7-67.69" */
reg [3:0] \mchip.registerOut.Out ;
/* hdlname = "mchip registerOut clk" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:39.16-39.19|d22_yushuanl_convolution/src/chip.sv:67.7-67.69" */
wire \mchip.registerOut.clk ;
/* hdlname = "mchip registerOut en" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:39.21-39.23|d22_yushuanl_convolution/src/chip.sv:67.7-67.69" */
wire \mchip.registerOut.en ;
/* hdlname = "mchip registerTemp In" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:38.22-38.24|d22_yushuanl_convolution/src/chip.sv:66.7-66.69" */
wire [3:0] \mchip.registerTemp.In ;
/* hdlname = "mchip registerTemp Out" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:40.23-40.26|d22_yushuanl_convolution/src/chip.sv:66.7-66.69" */
reg [3:0] \mchip.registerTemp.Out ;
/* hdlname = "mchip registerTemp clk" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:39.16-39.19|d22_yushuanl_convolution/src/chip.sv:66.7-66.69" */
wire \mchip.registerTemp.clk ;
/* hdlname = "mchip registerTemp en" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:39.21-39.23|d22_yushuanl_convolution/src/chip.sv:66.7-66.69" */
wire \mchip.registerTemp.en ;
/* hdlname = "mchip reset" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:49.17-49.22" */
wire \mchip.reset ;
/* hdlname = "mchip shiftA In" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:3.22-3.24|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
wire [5:0] \mchip.shiftA.In ;
/* hdlname = "mchip shiftA Shifted" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:5.23-5.30|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
reg [5:0] \mchip.shiftA.Shifted ;
/* hdlname = "mchip shiftA clk" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:4.26-4.29|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
wire \mchip.shiftA.clk ;
/* hdlname = "mchip shiftB In" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:3.22-3.24|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
wire [5:0] \mchip.shiftB.In ;
/* hdlname = "mchip shiftB Shifted" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:5.23-5.30|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
reg [5:0] \mchip.shiftB.Shifted ;
/* hdlname = "mchip shiftB clk" */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:4.26-4.29|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
wire \mchip.shiftB.clk ;
assign _12_ = ~(\mchip.curState [1] | \mchip.curState [0]);
assign _13_ = _12_ & ~(\mchip.curState [2]);
assign _14_ = ~\mchip.curState [2];
assign _15_ = \mchip.curState [1] & \mchip.curState [0];
assign _16_ = \mchip.curState [2] ? _15_ : _12_;
assign _01_ = _13_ | ~(_16_);
assign _17_ = ~_15_;
assign _18_ = \mchip.curState [1] | ~(\mchip.curState [0]);
assign \mchip.enRT = \mchip.curState [2] ? _17_ : _18_;
assign \mchip.enRO = _15_ & ~(_14_);
assign _07_ = _13_ ? io_in[6] : \mchip.shiftB.Shifted [1];
assign _08_ = _13_ ? io_in[7] : \mchip.shiftB.Shifted [2];
assign _09_ = _13_ ? io_in[8] : \mchip.shiftB.Shifted [3];
assign _10_ = _13_ ? io_in[9] : \mchip.shiftB.Shifted [4];
assign _11_ = _13_ ? io_in[10] : \mchip.shiftB.Shifted [5];
assign _02_ = _13_ ? io_in[0] : \mchip.shiftA.Shifted [1];
assign _03_ = _13_ ? io_in[1] : \mchip.shiftA.Shifted [2];
assign _04_ = _13_ ? io_in[2] : \mchip.shiftA.Shifted [3];
assign _05_ = _13_ ? io_in[3] : \mchip.shiftA.Shifted [4];
assign _06_ = _13_ ? io_in[4] : \mchip.shiftA.Shifted [5];
assign _19_ = ~\mchip.curState [0];
assign _00_[0] = \mchip.curState [2] ? _18_ : _19_;
assign _20_ = ~_12_;
assign _21_ = \mchip.curState [1] ^ \mchip.curState [0];
assign _00_[1] = \mchip.curState [2] ? _20_ : _21_;
assign _00_[2] = _15_ | \mchip.curState [2];
assign _22_ = \mchip.registerTemp.Out [0] & ~(_16_);
assign _23_ = ~(\mchip.shiftA.Shifted [0] & \mchip.shiftB.Shifted [0]);
assign _24_ = _22_ & ~(_23_);
assign _25_ = _16_ | ~(\mchip.registerTemp.Out [1]);
assign \mchip.registerTemp.In [1] = ~(_25_ ^ _24_);
assign _26_ = _24_ & ~(_25_);
assign _27_ = _16_ | ~(\mchip.registerTemp.Out [2]);
assign \mchip.registerTemp.In [2] = ~(_27_ ^ _26_);
assign _28_ = _26_ & ~(_27_);
assign _29_ = \mchip.registerTemp.Out [3] & ~(_16_);
assign \mchip.registerTemp.In [3] = _29_ ^ _28_;
assign \mchip.registerTemp.In [0] = ~(_23_ ^ _22_);
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
always @(posedge io_in[12])
if (_01_)
if (!_13_) \mchip.shiftA.Shifted [5] <= 1'h0;
else \mchip.shiftA.Shifted [5] <= io_in[5];
always @(posedge io_in[12])
if (io_in[13]) \mchip.curState [0] <= 1'h0;
else \mchip.curState [0] <= _00_[0];
always @(posedge io_in[12])
if (io_in[13]) \mchip.curState [1] <= 1'h0;
else \mchip.curState [1] <= _00_[1];
always @(posedge io_in[12])
if (io_in[13]) \mchip.curState [2] <= 1'h0;
else \mchip.curState [2] <= _00_[2];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftA.Shifted [0] <= _02_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftA.Shifted [1] <= _03_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftA.Shifted [2] <= _04_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftA.Shifted [3] <= _05_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:57.12-58.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftA.Shifted [4] <= _06_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftB.Shifted [0] <= _07_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftB.Shifted [1] <= _08_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftB.Shifted [2] <= _09_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftB.Shifted [3] <= _10_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
always @(posedge io_in[12])
if (_01_) \mchip.shiftB.Shifted [4] <= _11_;
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:41.3-43.17|d22_yushuanl_convolution/src/chip.sv:67.7-67.69" */
always @(posedge io_in[12])
if (\mchip.enRO ) \mchip.registerOut.Out [0] <= \mchip.registerTemp.Out [0];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:41.3-43.17|d22_yushuanl_convolution/src/chip.sv:67.7-67.69" */
always @(posedge io_in[12])
if (\mchip.enRO ) \mchip.registerOut.Out [1] <= \mchip.registerTemp.Out [1];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:41.3-43.17|d22_yushuanl_convolution/src/chip.sv:67.7-67.69" */
always @(posedge io_in[12])
if (\mchip.enRO ) \mchip.registerOut.Out [2] <= \mchip.registerTemp.Out [2];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:41.3-43.17|d22_yushuanl_convolution/src/chip.sv:67.7-67.69" */
always @(posedge io_in[12])
if (\mchip.enRO ) \mchip.registerOut.Out [3] <= \mchip.registerTemp.Out [3];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:6.3-10.39|d22_yushuanl_convolution/src/chip.sv:59.12-60.52" */
always @(posedge io_in[12])
if (_01_)
if (!_13_) \mchip.shiftB.Shifted [5] <= 1'h0;
else \mchip.shiftB.Shifted [5] <= io_in[11];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:41.3-43.17|d22_yushuanl_convolution/src/chip.sv:66.7-66.69" */
always @(posedge io_in[12])
if (\mchip.enRT ) \mchip.registerTemp.Out [0] <= \mchip.registerTemp.In [0];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:41.3-43.17|d22_yushuanl_convolution/src/chip.sv:66.7-66.69" */
always @(posedge io_in[12])
if (\mchip.enRT ) \mchip.registerTemp.Out [1] <= \mchip.registerTemp.In [1];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:41.3-43.17|d22_yushuanl_convolution/src/chip.sv:66.7-66.69" */
always @(posedge io_in[12])
if (\mchip.enRT ) \mchip.registerTemp.Out [2] <= \mchip.registerTemp.In [2];
/* \always_ff = 32'd1 */
/* src = "d22_yushuanl_convolution/src/toplevel_chip.v:9.13-14.6|d22_yushuanl_convolution/src/chip.sv:41.3-43.17|d22_yushuanl_convolution/src/chip.sv:66.7-66.69" */
always @(posedge io_in[12])
if (\mchip.enRT ) \mchip.registerTemp.Out [3] <= \mchip.registerTemp.In [3];
assign io_out = { 10'h000, \mchip.registerOut.Out };
assign \mchip.Shifted_A = \mchip.shiftA.Shifted ;
assign \mchip.Shifted_B = \mchip.shiftB.Shifted ;
assign \mchip.add.Out = \mchip.registerTemp.In ;
assign \mchip.clock = io_in[12];
assign \mchip.inReg = \mchip.registerTemp.In ;
assign \mchip.io_in = io_in[11:0];
assign \mchip.io_out = \mchip.registerOut.Out ;
assign \mchip.mul.First = \mchip.shiftA.Shifted [0];
assign \mchip.mul.Second = \mchip.shiftB.Shifted [0];
assign \mchip.mux.A = \mchip.registerTemp.Out ;
assign \mchip.mux.B = 4'h0;
assign \mchip.oldSum = \mchip.registerTemp.Out ;
assign \mchip.registerOut.In = \mchip.registerTemp.Out ;
assign \mchip.registerOut.clk = io_in[12];
assign \mchip.registerOut.en = \mchip.enRO ;
assign \mchip.registerTemp.clk = io_in[12];
assign \mchip.registerTemp.en = \mchip.enRT ;
assign \mchip.reset = io_in[13];
assign \mchip.shiftA.In = io_in[5:0];
assign \mchip.shiftA.clk = io_in[12];
assign \mchip.shiftB.In = io_in[11:6];
assign \mchip.shiftB.clk = io_in[12];
endmodule