You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Create a single .vhd source file with an entity and architecture declaration. The entity should be named "modulator". The architecture should be named "Structural" for structural modelling.
The architecture should contain the following components:
mux
Index_reg
COS_LUT
adder
All signals should be std_logic_vector except for Fs_clk which is std_logic. Signals required:
Sample_out - entity output
Fs_clk - entity input
Data_in - entity input
offset - architecture signal
addr_in - architecture signal
mark - architecture signal
space - architecture signal
The text was updated successfully, but these errors were encountered:
Summary
Lucidchart link
Acceptance Criteria
Create a single .vhd source file with an entity and architecture declaration. The entity should be named "modulator". The architecture should be named "Structural" for structural modelling.
The architecture should contain the following components:
All signals should be std_logic_vector except for Fs_clk which is std_logic. Signals required:
The text was updated successfully, but these errors were encountered: