feat: 添加 x86_64 架构支持，包含 CPU 和 HAL 模块的实现

Author: ZR233

Cargo.toml

@@ -14,10 +14,10 @@ anyhow = {version = "1.0", default-features = false}
 cfg-if = "1.0"
 lazyinit = "0.2"
 log = "0.4"
+ranges-ext.workspace = true
 spin = "0.10"
 thiserror = {version = "2", default-features = false}
 timer_list = "0.1"
-ranges-ext.workspace = true
 
 # System independent crates provided by ArceOS.
 axerrno = "0.1.0"
@@ -31,7 +31,6 @@ percpu = {version = "0.2", features = ["arm-el2"]}
 vm-allocator.workspace = true
 vm-fdt.workspace = true
 
-
 # System dependent modules provided by ArceOS-Hypervisor.
 axaddrspace = "0.2"
 # axdevice = {git = "https://github.com/arceos-hypervisor/axdevice.git"}
@@ -45,7 +44,8 @@ axvmconfig = {version = "0.1", default-features = false}
 fdt-edit = "0.1"
 
 [target.'cfg(target_arch = "x86_64")'.dependencies]
-# x86_vcpu = "0.1"
+x86_vcpu = "0.1"
+axplat-x86-qemu-q35.workspace = true
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 # riscv_vcpu = "0.1"

src/arch/aarch64/cpu.rs

@@ -102,10 +102,15 @@ impl VCpu {
         let vcpu = arm_vcpu::Aarch64VCpu::new(Aarch64VCpuCreateConfig {
             mpidr_el1: hard_id.raw() as u64,
             dtb_addr: dtb_addr.as_usize(),
+            pt_level: 4,
         })
         .unwrap();
         Ok(VCpu { vcpu, common })
     }
+
+    pub fn set_pt_level(&mut self, level: usize) {
+        self.vcpu.pt_level = level;
+    }
 }
 
 impl VCpuOp for VCpu {
@@ -119,6 +124,7 @@ impl VCpuOp for VCpu {
 
     fn run(&mut self) -> Result<(), RunError> {
         info!("Starting vCPU {}", self.bind_id());
+
         self.vcpu
             .setup_current_cpu(self.vm_id().into())
             .map_err(|e| anyhow!("{e}"))?;

src/arch/aarch64/vm/unint.rs

@@ -120,6 +120,7 @@ impl VmMachineUninit {
         for vcpu in &mut cpus {
             vcpu.vcpu.set_entry(kernel_entry).unwrap();
             vcpu.vcpu.set_dtb_addr(dtb_addr).unwrap();
+            vcpu.set_pt_level(self.pt_levels);
 
             let setup_config = Aarch64VCpuSetupConfig {
                 passthrough_interrupt: self.config.interrupt_mode()

src/arch/x86_64/cpu.rs

@@ -0,0 +1,196 @@
+use core::{
+    fmt::{self, Debug, Display},
+    ops::Deref,
+};
+
+use axvm_types::addr::*;
+use x86_vcpu::*;
+
+use crate::{
+    RunError,
+    data::VmDataWeak,
+    vcpu::{VCpuCommon, VCpuOp},
+    vhal::{
+        ArchCpuData,
+        cpu::{CpuHardId, CpuId},
+    },
+};
+
+pub struct HCpu {
+    pub id: CpuId,
+    pub hard_id: CpuHardId,
+    vpercpu: VmxArchVCpu,
+    max_guest_page_table_levels: usize,
+    pub pa_range: core::ops::Range<usize>,
+}
+
+impl HCpu {
+    pub fn new(id: CpuId) -> Self {
+        let mpidr = MPIDR_EL1.get() as usize;
+        let hard_id = mpidr & 0xff_ff_ff;
+
+        let vpercpu = Aarch64PerCpu::new();
+
+        HCpu {
+            id,
+            hard_id: CpuHardId::new(hard_id),
+            vpercpu,
+            max_guest_page_table_levels: 0,
+            pa_range: 0..0,
+        }
+    }
+
+    pub fn init(&mut self) -> anyhow::Result<()> {
+        self.vpercpu.hardware_enable();
+        self.max_guest_page_table_levels = self.vpercpu.max_guest_page_table_levels();
+        self.pa_range = self.vpercpu.pa_range();
+        Ok(())
+    }
+
+    pub fn max_guest_page_table_levels(&self) -> usize {
+        self.max_guest_page_table_levels
+    }
+}
+
+impl ArchCpuData for HCpu {
+    fn hard_id(&self) -> CpuHardId {
+        self.hard_id
+    }
+}
+
+impl Display for HCpu {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(
+            f,
+            "
+CPU {}:
+  Hard ID: {}
+  PT Levels: {}",
+            self.id, self.hard_id, self.max_guest_page_table_levels
+        )
+    }
+}
+
+pub(super) struct VCpuHal;
+
+impl arm_vcpu::CpuHal for VCpuHal {
+    fn irq_hanlder(&self) {
+        axhal::irq::irq_handler(0);
+    }
+
+    fn inject_interrupt(&self, irq: usize) {
+        todo!()
+    }
+}
+
+pub struct VCpu {
+    pub vcpu: arm_vcpu::Aarch64VCpu,
+    common: VCpuCommon,
+}
+
+impl VCpu {
+    pub fn new(
+        host_cpuid: Option<CpuId>,
+        dtb_addr: GuestPhysAddr,
+        vm: VmDataWeak,
+    ) -> anyhow::Result<Self> {
+        let common = VCpuCommon::new_exclusive(host_cpuid, vm)?;
+
+        let hard_id = common.hard_id();
+
+        let vcpu = arm_vcpu::Aarch64VCpu::new(Aarch64VCpuCreateConfig {
+            mpidr_el1: hard_id.raw() as u64,
+            dtb_addr: dtb_addr.as_usize(),
+        })
+        .unwrap();
+        Ok(VCpu { vcpu, common })
+    }
+}
+
+impl VCpuOp for VCpu {
+    fn bind_id(&self) -> CpuId {
+        self.common.bind_id()
+    }
+
+    fn hard_id(&self) -> CpuHardId {
+        self.common.hard_id()
+    }
+
+    fn run(&mut self) -> Result<(), RunError> {
+        info!("Starting vCPU {}", self.bind_id());
+        self.vcpu
+            .setup_current_cpu(self.vm_id().into())
+            .map_err(|e| anyhow!("{e}"))?;
+        while self.is_active() {
+            debug!("vCPU {} entering guest", self.bind_id());
+            let exit_reason = self.vcpu.run().map_err(|e| anyhow!("{e}"))?;
+            debug!(
+                "vCPU {} exited with reason: {:?}",
+                self.bind_id(),
+                exit_reason
+            );
+            match exit_reason {
+                arm_vcpu::AxVCpuExitReason::Hypercall { nr, args } => todo!(),
+                arm_vcpu::AxVCpuExitReason::MmioRead {
+                    addr,
+                    width,
+                    reg,
+                    reg_width,
+                    signed_ext,
+                } => todo!(),
+                arm_vcpu::AxVCpuExitReason::MmioWrite { addr, width, data } => todo!(),
+                arm_vcpu::AxVCpuExitReason::SysRegRead { addr, reg } => todo!(),
+                arm_vcpu::AxVCpuExitReason::SysRegWrite { addr, value } => todo!(),
+                arm_vcpu::AxVCpuExitReason::ExternalInterrupt => {
+                    axhal::irq::irq_handler(0);
+                }
+                arm_vcpu::AxVCpuExitReason::CpuUp {
+                    target_cpu,
+                    entry_point,
+                    arg,
+                } => {
+                    debug!("vCPU {} requested CPU {} up", self.bind_id(), target_cpu);
+                    self.vm()?.with_machine_running_mut(|running| {
+                        debug!("vCPU {} is bringing up CPU {}", self.bind_id(), target_cpu);
+                        running.cpu_up(CpuHardId::new(target_cpu as _), entry_point, arg)
+                    })??;
+                    self.vcpu.set_gpr(0, 0);
+                }
+                arm_vcpu::AxVCpuExitReason::CpuDown { _state } => todo!(),
+                arm_vcpu::AxVCpuExitReason::SystemDown => {
+                    info!("vCPU {} requested system shutdown", self.bind_id());
+                    self.vm()?.stop()?;
+                }
+                arm_vcpu::AxVCpuExitReason::Nothing => {}
+                arm_vcpu::AxVCpuExitReason::SendIPI {
+                    target_cpu,
+                    target_cpu_aux,
+                    send_to_all,
+                    send_to_self,
+                    vector,
+                } => todo!(),
+                _ => todo!(),
+            }
+        }
+
+        Ok(())
+    }
+}
+
+impl Deref for VCpu {
+    type Target = VCpuCommon;
+
+    fn deref(&self) -> &Self::Target {
+        &self.common
+    }
+}
+
+impl Debug for VCpu {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_struct("VCpu")
+            .field("bind_id", &self.bind_id())
+            .field("hard_id", &self.hard_id())
+            .field("vcpu", &self.vcpu)
+            .finish()
+    }
+}

src/arch/x86_64/hal.rs

@@ -0,0 +1,39 @@
+use alloc::vec::Vec;
+
+use crate::vhal::{
+    ArchHal,
+    cpu::{CpuHardId, CpuId},
+};
+
+use super::cpu::{HCpu, VCpuHal};
+
+pub struct Hal;
+
+impl ArchHal for Hal {
+    fn current_cpu_init(id: CpuId) -> anyhow::Result<HCpu> {
+        info!("Enabling virtualization on cpu {id}");
+        let mut cpu = HCpu::new(id);
+        cpu.init()?;
+        info!("{cpu}");
+        Ok(cpu)
+    }
+
+    fn init() -> anyhow::Result<()> {
+        
+
+        Ok(())
+    }
+
+    fn cpu_list() -> Vec<CpuHardId> {
+        
+    }
+
+    fn cpu_hard_id() -> CpuHardId {
+        let mpidr = MPIDR_EL1.get() as usize;
+        CpuHardId::new(mpidr)
+    }
+
+    fn cache_flush(vaddr: arm_vcpu::HostVirtAddr, size: usize) {
+        dcache_range(CacheOp::CleanAndInvalidate, vaddr.as_usize(), size);
+    }
+}

src/arch/x86_64/mod.rs

@@ -1 +1,2 @@
-
+mod cpu;
+mod hal;