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mips32r2.tex
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%
% Copyright (C) 2014-2019 Anders Sonmark
%
% Copying and distribution of this file, with or without modification,
% are permitted in any medium without royalty provided the copyright
% notice and this notice are preserved. This file is offered as-is,
% without any warranty.
%
\documentclass{sheet}
\usepackage[utf8]{inputenc}
\usepackage[T1]{fontenc}
\usepackage{ae,aecompl}
\usepackage[english]{babel}
\usepackage[a4paper, landscape, margin=.1in]{geometry}
\usepackage{amssymb}
\def\sheetheaderfont{\bfseries}
\def\sheettablefont{\footnotesize\sffamily}
\def\sheetheadercolor{black!10}
\def\sheetrowcolor{black!5}
\def\tabcolsep{2pt}
\def\arraystretch{1.3}
\defsheet{asmtable}{4}{|m{4.2em} m{5.0em}|X|m{0.7em}|}
\defsheet{asmtabledsp}{4}{|m{8.4em} m{3.7em}|X|m{0.7em}|}
\defsheet{asmtabledsp2}{4}{|m{10.2em} m{3.7em}|X|m{0.7em}|}
\defsheet{table-lX}{2}{|l X|}
\defsheet{table-llX}{3}{|l l X|}
\pagefooter{MIPS32r2 version 2 page \thepage}
\begin{document}
\begin{multicols}{3}
\raggedcolumns
\begin{center}
{\Large\bfseries MIPS32r2 Quick Reference}
\end{center}
%
\begin{table-lX}{Keys}
rx, ry, rz & General registers \\
AC0 & Accumulator register 0 (HI:LO) \\
i, p, s, rel, ptr, off & Immediate operand \\
ISA & ISA mode (0=MIPS32, 1=MIPS16e) \\
value$^{\pm}_{ }$ & Value is sign extended \\
value$^{\emptyset}_{ }$ & Value is zero extended \\
$\smul$ $\sdiv$ $\smod$ $\asr$ $\slt$ $\sge$ & Operation is signed \\
\end{table-lX}
%
\begin{asmtable}{Arithmetic Instructions}
ADD & rx, ry, rz & rx = ry $+$ rz & O \\
ADDI & rx, ry, i$^{ }_{16}$ & rx = ry $+$ i$^{\pm}_{ }$ & O \\
ADDIU & rx, ry, i$^{ }_{16}$ & rx = ry $+$ i$^{\pm}_{ }$ & \\
ADDU & rx, ry, rz & rx = ry $+$ rz & \\
DIV & rx, ry & AC0$^{ }_{63:32}$ = rx $\sdiv$ ry; AC0$^{ }_{31:0}$ = rx $\smod$ ry & \\
DIVU & rx, ry & AC0$^{ }_{63:32}$ = rx $\udiv$ ry; AC0$^{ }_{31:0}$ = rx $\umod$ ry & \\
MADD & rx, ry & AC0 = AC0 $+$ rx $\smul$ ry & \\
MADDU & rx, ry & AC0 = AC0 $+$ rx $\umul$ ry & \\
MSUB & rx, ry & AC0 = AC0 $-$ rx $\smul$ ry & \\
MSUBU & rx, ry & AC0 = AC0 $-$ rx $\umul$ ry & \\
MUL & rx, ry, rz & rx = ry $\smul$ rz & \\
MULT & rx, ry & AC0 = rx $\smul$ ry & \\
MULTU & rx, ry & AC0 = rx $\umul$ ry & \\
\textit{NEGU} & rx, ry & rx = 0 $-$ ry & \\
SUB & rx, ry, rz & rx = ry $-$ rz & O \\
SUBU & rx, ry, rz & rx = ry $-$ rz & \\
\end{asmtable}
%
\begin{asmtable}{Load and Store Instructions}
LB & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{\pm}_{8}$ & \\
LBU & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{\emptyset}_{8}$ & \\
LH & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{\pm}_{16}$ & \\
LHU & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{\emptyset}_{16}$ & \\
LL & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]; LL = 1 & \\
LW & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$] & \\
LWL & rx, off$^{ }_{16}$(ry) & s=(ry$+$off$^{\pm}_{ }$)$^{ }_{1:0}$; rx$^{ }_{31:24-s\umul 8}$ = [ry $+$ off$^{\pm}_{ }$]$^{ }_{8+s\umul 8}$ & \\
LWR & rx, off$^{ }_{16}$(ry) & s=(ry$+$off$^{\pm}_{ }$)$^{ }_{1:0}$; rx$^{ }_{31-s\umul 8:0}$ = [ry $+$ off$^{\pm}_{ }$]$^{ }_{32-s\umul 8}$ & \\
SB & rx, off$^{ }_{16}$(ry) & [ry $+$ off$^{\pm}_{ }$]$^{ }_{8}$ = rx$^{ }_{7:0}$ & \\
SC & rx, off$^{ }_{16}$(ry) & if(atomic) [ry $+$ off$^{\pm}_{ }$]=rx; rx=1; else rx=0 & \\
SH & rx, off$^{ }_{16}$(ry) & [ry $+$ off$^{\pm}_{ }$]$^{ }_{16}$ = rx$^{ }_{15:0}$ & \\
SW & rx, off$^{ }_{16}$(ry) & [ry $+$ off$^{\pm}_{ }$] = rx & \\
SWL & rx, off$^{ }_{16}$(ry) & s=(ry$+$off$^{\pm}_{ }$)$^{ }_{1:0}$; [ry $+$ off$^{\pm}_{ }$]$^{ }_{8+s\umul 8}$ = rx$^{ }_{31:24-s\umul 8}$ & \\
SWR & rx, off$^{ }_{16}$(ry) & s=(ry$+$off$^{\pm}_{ }$)$^{ }_{1:0}$; [ry $+$ off$^{\pm}_{ }$]$^{ }_{32-s\umul 8}$ = rx$^{ }_{31-s\umul 8:0}$ & \\
\textit{ULW} & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{unaligned}_{ }$ & \\
\textit{USW} & rx, off$^{ }_{16}$(ry) & [ry $+$ off$^{\pm}_{ }$]$^{unaligned}_{ }$ = rx & \\
\end{asmtable}
%
\begin{asmtable}{Bitwise Instructions}
AND & rx, ry, rz & rx = ry \& rz & \\
ANDI & rx, ry, i$^{ }_{16}$ & rx = ry \& i$^{\emptyset}_{ }$ & \\
CLO & rx, ry & rx = CountLeadingOnes(ry) & \\
CLZ & rx, ry & rx = CountLeadingZeros(ry) & \\
EXT & rx, ry, p, s & rx = ry$^{\emptyset}_{p+s-1:p}$ & 2 \\
INS & rx, ry, p, s & rx$^{ }_{p+s-1:p}$ = ry$^{ }_{s-1:0}$ & 2 \\
NOR & rx, ry, rz & rx = $\sim$(ry | rz) & \\
\textit{NOT} & rx, ry & rx = $\sim$ry & \\
OR & rx, ry, rz & rx = ry | rz & \\
ORI & rx, ry, i$^{ }_{16}$ & rx = ry | i$^{\emptyset}_{ }$ & \\
ROTR & rx, ry, i$^{ }_{5}$ & rx = ry $\ror$ i & \\
ROTRV & rx, ry, rz & rx = ry $\ror$ rz$^{ }_{4:0}$ & \\
SLL & rx, ry, i$^{ }_{5}$ & rx = ry $\lsl$ i & \\
SLLV & rx, ry, rz & rx = ry $\lsl$ rz$^{ }_{4:0}$ & \\
SRA & rx, ry, i$^{ }_{5}$ & rx = ry $\asr$ i & \\
SRAV & rx, ry, rz & rx = ry $\asr$ rz$^{ }_{4:0}$ & \\
SRL & rx, ry, i$^{ }_{5}$ & rx = ry $\lsr$ i & \\
SRLV & rx, ry, rz & rx = ry $\lsr$ rz$^{ }_{4:0}$ & \\
WSBH & rx, ry & rx = ry$^{ }_{23:16}$:ry$^{ }_{31:24}$:ry$^{ }_{7:0}$:ry$^{ }_{15:8}$ & 2 \\
XOR & rx, ry, rz & rx = ry $\oplus$ rz & \\
XORI & rx, ry, i$^{ }_{16}$ & rx = ry $\oplus$ i$^{\emptyset}_{ }$ & \\
\end{asmtable}
%
\begin{asmtable}{Jump and Branch Instructions}
\textit{B} & rel$^{ }_{18}$ & PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
\textit{BAL} & rel$^{ }_{18}$ & RA = PC$+$8; PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
BEQ & rx, ry, rel$^{ }_{18}$ & if (rx $=$ ry) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
\textit{BEQZ} & rx, rel$^{ }_{18}$ & if (rx $=$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
BGEZ & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
BGEZAL & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 0) RA = PC$+$8; PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
BGTZ & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 0 \&\& rx $\ne$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
BLEZ & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 1 || rx $=$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
BLTZ & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 1) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
BLTZAL & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 1) RA = PC$+$8; PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
BNE & rx, ry, rel$^{ }_{18}$ & if (rx $\ne$ ry) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
\textit{BNEZ} & rx, rel$^{ }_{18}$ & if (rx $\ne$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\
J & ptr$^{ }_{28}$ & PC = PC$^{ }_{31:29}$:ptr$^{ }_{28:2}$:0$^{ }_{1:0}$ & D \\
JAL & ptr$^{ }_{28}$ & RA=PC$+$8; PC=PC$^{ }_{31:29}$:ptr$^{ }_{28:2}$:0$^{ }_{1:0}$ & D \\
JALX & ptr$^{ }_{28}$ & ISA=1; RA=PC$+$8; PC=PC$^{ }_{31:29}$:ptr$^{ }_{28:2}$:0$^{ }_{1:0}$ & D \\
JALR & rx, ry & rx=PC$+$8; ISA=ry$^{ }_{0}$; PC=ry$^{ }_{31:1}$:0 & D \\
\textit{JALR} & rx & RA=PC$+$8; ISA=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0 & D \\
JALR.HB & rx, ry & rx=PC$+$8; ISA=ry$^{ }_{0}$; PC=ry$^{ }_{31:1}$:0; ClrHazards & D \\
\textit{JALR.HB} & rx & RA=PC$+$8; ISA=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0; ClrHazards & D \\
JR & rx & ISA=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0 & D \\
JR.HB & rx & ISA=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0; ClrHazards & D \\
\end{asmtable}
%
\begin{asmtable}{Data Transfer Instructions}
\textit{LA} & rx, rel & rx = rel & \\
\textit{LI} & rx, i$^{ }_{32}$ & rx = i & \\
LUI & rx, i$^{ }_{16}$ & rx = i $\lsl$ 16 & \\
MFHI & rx & rx = AC0$^{ }_{63:32}$ & \\
MFLO & rx & rx = AC0$^{ }_{31:0}$ & \\
\textit{MOVE} & rx, ry & rx = ry & \\
MOVN & rx, ry, rz & if (rz $\ne$ 0) rx = ry & \\
MOVZ & rx, ry, rz & if (rz $=$ 0) rx = ry & \\
MTHI & rx & AC0$^{ }_{63:32}$ = rx & \\
MTLO & rx & AC0$^{ }_{31:0}$ = rx & \\
RDHWR & rx, ry & rx = HardwareRegister(ry) & 2 \\
SEB & rx, ry & rx = ry$^{\pm}_{7:0}$ & 2 \\
SEH & rx, ry & rx = ry$^{\pm}_{15:0}$ & 2 \\
SLT & rx, ry, rz & rx = (ry $\slt$ rz ? 1 : 0) & \\
SLTI & rx, ry, i$^{ }_{16}$ & rx = (ry $\slt$ i$^{\pm}_{ }$ ? 1 : 0) & \\
SLTIU & rx, ry, i$^{ }_{16}$ & rx = (ry $\ult$ i$^{\pm}_{ }$ ? 1 : 0) & \\
SLTU & rx, ry, rz & rx = (ry $\ult$ rz ? 1 : 0) & \\
\end{asmtable}
%
\begin{asmtable}{Control Instructions}
CACHE & i$^{ }_{5}$, off$^{ }_{16}$(rx) & CacheOperation(i, rx$+$off$^{\pm}_{ }$) & \\
EHB & & ExecutionHazardBarrier & \\
\textit{NOP} & & & \\
PAUSE & & While(LL $\ne$ 0) Wait & \\
PREF & i$^{ }_{5}$, off$^{ }_{16}$(ry) & PrefetchMemory(ry $+$ off$^{\pm}_{ }$) & \\
SSNOP & & SuperScalarNoOperation & \\
SYNC & stype$^{ }_{5}$ & SyncOperation(stype) & \\
SYNCI & off$^{ }_{16}$(rx) & SyncCacheLines(rx $+$ off$^{\pm}_{ }$) & 2 \\
\end{asmtable}
%
\begin{asmtable}{Trap Instructions}
BREAK & i$^{ }_{20}$ & Exception(Breakpoint) & \\
SYSCALL & code$^{ }_{20}$ & Exception(SystemCall) & \\
TEQ & rx, ry & if (rx $=$ ry) Exception(Trap) & \\
TEQI & rx, i$^{ }_{16}$ & if (rx $=$ i$^{\pm}_{ }$) Exception(Trap) & \\
TGE & rx, ry & if (rx $\sge$ ry) Exception(Trap) & \\
TGEI & rx, i$^{ }_{16}$ & if (rx $\sge$ i$^{\pm}_{ }$) Exception(Trap) & \\
TGEIU & rx, i$^{ }_{16}$ & if (rx $\uge$ i$^{\pm}_{ }$) Exception(Trap) & \\
TGEU & rx, ry & if (rx $\uge$ ry) Exception(Trap) & \\
TLT & rx, ry & if (rx $\slt$ ry) Exception(Trap) & \\
TLTI & rx, i$^{ }_{16}$ & if (rx $\slt$ i$^{\pm}_{ }$) Exception(Trap) & \\
TLTIU & rx, i$^{ }_{16}$ & if (rx $\ult$ i$^{\pm}_{ }$) Exception(Trap) & \\
TLTU & rx, ry & if (rx $\ult$ ry) Exception(Trap) & \\
TNE & rx, ry & if (rx $\ne$ ry) Exception(Trap) & \\
TNEI & rx, i$^{ }_{16}$ & if (rx $\ne$ i$^{\pm}_{ }$) Exception(Trap) & \\
\end{asmtable}
%
\begin{asmtable}{Privileged Instructions}
DI & \{rx\} & rx = STATUS; STATUS$^{ }_{IE}$ = 0 & 2 \\
DERET & & DebugExceptionReturn & \\
EI & \{rx\} & rx = STATUS; STATUS$^{ }_{IE}$ = 1 & 2 \\
ERET & & ExceptionReturn & \\
MFC0 & rx, ry, i$^{ }_{3}$ & rx = Coprocessor0Register[ry, i] & \\
MTC0 & rx, ry, i$^{ }_{3}$ & Coprocessor0Register[ry, i] = rx & \\
RDPGPR & rx, ry & rx = PreviousShadowSet(ry) & 2 \\
SDBBP & code$^{ }_{20}$ & SoftwareDebugBreakpoint & \\
TLBP & & TlbIndex = FindTlbEntry(EntryHi) & \\
TLBR & & Entry:PageMask = TlbEntry[TlbIndex] & \\
TLBWI & & TlbEntry[TlbIndex] = Entry:PageMask & \\
TLBWR & & TlbEntry[TlbRandom] = Entry:PageMask & \\
WAIT & & Wait for interrupt or external request & \\
WRPGPR & rx, ry & PreviousShadowSet(rx) = ry & 2 \\
\end{asmtable}
%
\begin{table-llX}{Cache Operations}
0x00..0x03 & Index & (Writeback and) invalidate instr/data/3rd/2nd cache \\
0x04..0x07 & Index & Load tag instr/data/3rd/2nd cache \\
0x08..0x0b & Index & Store tag instr/data/3rd/2nd cache \\
0x10..0x13 & Address & Invalidate instr/data/3rd/2nd cache \\
0x14 & Address & Fill instruction cache \\
0x15..0x17 & Address & Writeback and invalidate data/3rd/2nd cache \\
0x19..0x1b & Address & Writeback data/3rd/2nd cache \\
0x1c..0x1d & Address & Fetch and lock instruction/data cache \\
\end{table-llX}
%
\begin{table-lX}{RDHWR Register Numbers}
0 & Number of current CPU \\
1 & Address step size to be used with SYNCI instruction \\
2 & High-resolution cycle counter \\
3 & Resolution of the cycle counter \\
29 & User local register \\
\end{table-lX}
%
\begin{table-lX}{Notes}
2 & Only available on MIPS32 Release 2. \\
D & Delay slot of one instruction before jump is executed. \\
O & Exception without modifying the destination register on signed overflow. \\
Q & Only available with DSP Rev2. \\
R & If extended, can also include A*..A3 and any of S2..S8 in reglist. \\
S & The shift count may be 1..8. Extendable to 0..31. \\
X & Immediate can be extended by up to 11 bits (max 16 bits total). \newline The extended immediate is unsigned for CMPI and LI, otherwise signed. \\
\end{table-lX}
%
\begin{table-llX}{General Registers}
0 & ZERO & Always zero \\
1 & AT & \\
2..3 & V0..V1 & Function return value (usable by MIPS16e) \\
4..7 & A0..A3 & Function parameters (usable by MIPS16e) \\
8..15 & T0..T7 & Temporary \\
16..23 & S0..S7 & Must be preserved (S0..S1 usable by MIPS16e) \\
24..25 & T8..T9 & Temporary \\
26..27 & K0..K1 & Kernel use \\
28 & GP & Global pointer \\
29 & SP & Stack pointer \\
30 & FP/S8 & Stack frame pointer, must be preserved \\
31 & RA & Function return address \\
& PC & Program Counter \\
\end{table-llX}
%
\begin{asmtable}{MIPS16e Load and Store Instructions}
LB & rx, i$^{ }_{5}$(ry) & rx = [ry $+$ i$^{\emptyset}$]$^{\pm}_{8}$ & X \\
LBU & rx, i$^{ }_{5}$(ry) & rx = [ry $+$ i$^{\emptyset}$]$^{\emptyset}_{8}$ & X \\
LH & rx, i$^{ }_{6}$(ry) & rx = [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{\pm}_{16}$ & X \\
LHU & rx, i$^{ }_{6}$(ry) & rx = [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{\emptyset}_{16}$ & X \\
LW & rx, i$^{ }_{7}$(ry) & rx = [ry $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{1:0}$] & X \\
LW & rx, i$^{ }_{10}$(PC) & rx = [PC$^{ }_{31:2}$:0$^{ }_{1:0}$ $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] & X \\
LW & rx, i$^{ }_{10}$(SP) & rx = [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] & X \\
SB & rx, i$^{ }_{5}$(ry) & [ry $+$ i$^{\emptyset}_{ }$]$^{ }_{8}$ = rx$^{ }_{8}$ & X \\
SH & rx, i$^{ }_{6}$(ry) & [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{ }_{16}$ = rx$^{ }_{16}$ & X \\
SW & rx, i$^{ }_{7}$(ry) & [ry $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{1:0}$] = rx & X \\
SW & rx, i$^{ }_{10}$(SP) & [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] = rx & X \\
SW & RA, i$^{ }_{10}$(SP) & [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] = RA & X \\
\end{asmtable}
%
\begin{asmtable}{MIPS16e Data Transfer Instructions}
\textit{LA} & rx, rel & rx = rel & \\
LI & rx, i$^{ }_{8}$ & rx = i$^{\emptyset}_{ }$ & X \\
MFHI & rx & rx = AC0$^{ }_{63:32}$ & \\
MFLO & rx & rx = AC0$^{ }_{31:0}$ & \\
MOVE & rx, r32 & rx = r32 & \\
MOVE & r32, ry & r32 = rx & \\
RESTORE & reglist, i$^{ }_{7}$ & SP $+$= i$^{ }_{6:2}$:0$^{ }_{1:0}$; reglist = [SP] & R \\
SAVE & reglist, i$^{ }_{7}$ & [SP] = reglist; SP $-$= i$^{ }_{6:2}$:0$^{ }_{1:0}$ & R \\
SEB & rx & rx = rx$^{\pm}_{7:0}$ & \\
SEH & rx & rx = rx$^{\pm}_{15:0}$ & \\
SLT & rx, ry & T8 = (rx $\slt$ ry ? 1 : 0) & \\
SLTI & rx, i$^{ }_{8}$ & T8 = (rx $\slt$ i$^{\emptyset}_{ }$ ? 1 : 0) & X \\
SLTIU & rx, i$^{ }_{8}$ & T8 = (rx $\ult$ i$^{\emptyset}_{ }$ ? 1 : 0) & X \\
SLTU & rx, ry & T8 = (rx $\ult$ ry ? 1 : 0) & \\
ZEB & rx & rx = rx$^{\emptyset}_{7:0}$ & \\
ZEH & rx & rx = rx$^{\emptyset}_{15:0}$ & \\
\end{asmtable}
%
\begin{asmtable}{MIPS16e Jump and Branch Instructions}
B & rel$^{ }_{12}$ & PC $+$= rel$^{\pm}_{11:1}$:0 & X \\
BEQZ & rx, rel$^{ }_{9}$ & if(rx $=$ 0) PC $+$= rel$^{\pm}_{8:1}$:0 & X \\
BNEZ & rx, rel$^{ }_{9}$ & if(rx $\ne$ 0) PC $+$= rel$^{\pm}_{8:1}$:0 & X \\
BREAK & i$^{ }_{6}$ & Breakpoint trap & X \\
BTEQZ & rel$^{ }_{9}$ & if(T8 $=$ 0) PC $+$= rel$^{\pm}_{8:1}$:0 & X \\
BTNEZ & rel$^{ }_{9}$ & if(T8 $\ne$ 0) PC $+$= rel$^{\pm}_{8:1}$:0 & \\
JAL & ptr$^{ }_{28}$ & RA=PC$+$5; PC=PC$^{ }_{31:28}$:ptr$^{ }_{27:2}$:0$^{ }_{1:0}$ & D \\
JALR & RA, rx & ISA=rx$^{ }_{0}$; RA=PC$+$5; PC=rx$^{ }_{31:1}$:0 & D \\
JALRC & RA, rx & ISA=rx$^{ }_{0}$; RA=PC$+$3; PC=rx$^{ }_{31:1}$:0 & \\
JALX & ptr$^{ }_{28}$ & ISA=0; RA=PC$+$5; PC=PC$^{ }_{31:28}$:ptr$^{ }_{27:2}$:0$^{ }_{1:0}$ & D \\
JR & rx & ISA=rx$^{ }_{0}$; PC = rx$^{ }_{31:1}$:0 & D \\
JR & RA & ISA=RA$^{ }_{0}$; PC = RA$^{ }_{31:1}$:0 & D \\
JRC & rx & ISA=rx$^{ }_{0}$; PC = rx$^{ }_{31:1}$:0 & \\
JRC & RA & ISA=RA$^{ }_{0}$; PC = RA$^{ }_{31:1}$:0 & \\
\textit{NOP} & & & \\
\end{asmtable}
%
\begin{asmtable}{MIPS16e Arithmetic Instructions}
ADDIU & rx, i$^{ }_{8}$ & rx = rx $+$ i$^{\pm}_{ }$ & X \\
ADDIU & rx, ry, i$^{ }_{4}$ & rx = ry $+$ i$^{\pm}_{ }$ & X \\
ADDIU & rx, PC, i$^{ }_{10}$ & rx = PC $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$ & \\
ADDIU & SP, i$^{ }_{11}$ & SP = SP $+$ i$^{\pm}_{10:3}$:0$^{ }_{2:0}$ & X \\
ADDIU & rx, SP, i$^{ }_{10}$ & rx = SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$ & \\
ADDU & rx, ry, rz & rx = ry $+$ rz & \\
DIV & rx, ry & AC0$^{ }_{31:0}$ = rx $\sdiv$ ry; AC0$^{ }_{63:32}$ = rx $\smod$ ry & \\
DIVU & rx, ry & AC0$^{ }_{31:0}$ = rx $\div$ ry; AC0$^{ }_{63:32}$ = rx $\umod$ ry & \\
MULT & rx, ry & AC0 = rx $\smul$ ry & \\
MULTU & rx, ry & AC0 = rx $\umul$ ry & \\
NEG & rx, ry & rx = 0 $-$ ry & \\
SUBU & rx, ry, rz & rx = ry $-$ rz & \\
\end{asmtable}
%
\begin{asmtable}{MIPS16e Bitwise Instructions}
AND & rx, ry & rx = rx \& ry & \\
CMP & rx, ry & T8 = rx $\oplus$ ry & \\
CMPI & rx, i$^{ }_{8}$ & T8 = rx $\oplus$ i$^{\emptyset}_{ }$ & X \\
NOT & rx, ry & rx = $\sim$ry & \\
OR & rx, ry & rx = rx | ry & \\
SLL & rx, ry, i$^{ }_{3}$ & rx = ry $\lsl$ i & S \\
SLLV & rx, ry & rx = rx $\lsl$ ry$^{ }_{4:0}$ & \\
SRA & rx, ry, i$^{ }_{3}$ & rx = ry $\asr$ i & S \\
SRAV & rx, ry & rx = rx $\asr$ ry$^{ }_{4:0}$ & \\
SRL & rx, ry, i$^{ }_{3}$ & rx = ry $\lsr$ i & S \\
SRLV & rx, ry & rx = rx $\lsr$ ry$^{ }_{4:0}$ & \\
XOR & rx, ry & rx = rx $\oplus$ ry & \\
\end{asmtable}
%
\begin{table-lX}{Keys for DSP Instructions}
ac & Accumulator register (AC0, AC1, AC2, or AC3). \\
cc & Condition code (EQ, LE, or LT). \\
a & A or S to add or subtract operand. \\
\_R & Result is rounded (one is added to MSB shifted out). \\
\_S & Result from each operation is saturated. (Signed for Q instructions, Unsigned for U instructions). \\
\_SA & Also saturate the final result (64bit for W instructions, 32bit for (P)H instructions). \\
c, ccond, pos, scount & Flags from DSP Control Register. \\
\end{table-lX}
%
\begin{asmtabledsp}{DSP Bitwise Instructions}
APPEND & rx, ry, i$^{ }_{5}$ & rx = rx$^{ }_{31-i:0}$:ry$^{ }_{i-1:0}$ & Q \\
BALIGN & rx, ry, i$^{ }_{2}$ & rx = rx$^{ }_{31-8i:0}$:ry$^{ }_{31:32-8i}$ & Q \\
BITREV & rx, ry & rx = ReverseBits(ry$^{ }_{15:0}$) & \\
EXTP & rx, ac, i$^{ }_{5}$ & rx = ac$^{\emptyset}_{pos:pos-i}$ & \\
EXTPDP & rx, ac, i$^{ }_{5}$ & rx = ac$^{\emptyset}_{pos:pos-i}$; pos $-$= (i$+$1) & \\
EXTPDPV & rx, ac, rz & rx = ac$^{\emptyset}_{pos:pos-rz^{ }_{4:0}}$; pos $-$= (rz$^{ }_{4:0}$$+$1) & \\
EXTPV & rx, ac, rz & rx = ac$^{\emptyset}_{pos:pos-rz^{ }_{4:0}}$ & \\
EXTR\{\_R\{S\}\}.W & rx, ac, i$^{ }_{5}$ & rx = ac $\asr$ i & \\
EXTR\_S.H & rx, ac, i$^{ }_{5}$ & rx = ac $\asr$ i & \\
EXTRV\{\_R\{S\}\}.W & rx, ac, rz & rx = ac $\asr$ rz$^{ }_{4:0}$ & \\
EXTRV\_S.H & rx, ac, rz & rx = ac $\asr$ rz$^{ }_{4:0}$ & \\
INSV & rx, ry & rx$^{ }_{pos+scount-1:pos}$ = ry$^{ }_{scount-1:0}$ & \\
MTHLIP & rx, ac & ac = ac$^{ }_{31:0}$:rx; pos $+$= 32 & \\
PREPEND & rx, ry, i$^{ }_{5}$ & rx = ry$^{ }_{i-1:0}$:rx$^{ }_{31:i}$ & Q \\
SHLL\{\_S\}.PH & rx, ry, i$^{ }_{5}$ & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $\lsl$ i & \\
SHLL.QB & rx, ry, i$^{ }_{5}$ & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{Bn}$ $\lsl$ i & \\
SHLL\_S.W & rx, ry, i$^{ }_{5}$ & rx = ry $\lsl$ i & \\
SHLLV\{\_S\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $\lsl$ rz$^{ }_{3:0}$ & \\
SHLLV.QB & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{Bn}$ $\lsl$ rz$^{ }_{2:0}$ & \\
SHLLV\_S.W & rx, ry, rz & rx = ry $\lsl$ rz$^{ }_{4:0}$ & \\
SHRA\{\_R\}.PH & rx, ry, i$^{ }_{4}$ & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $\asr$ i & \\
SHRA\{\_R\}.QB & rx, ry, i$^{ }_{3}$ & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{Bn}$ $\asr$ i & Q \\
SHRA\_R.W & rx, ry, i$^{ }_{5}$ & rx = ry $\asr$ i & \\
SHRAV\{\_R\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $\asr$ rz$^{ }_{3:0}$ & \\
SHRAV\{\_R\}.QB & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{Bn}$ $\asr$ rz$^{ }_{2:0}$ & Q \\
SHRAV\_R.W & rx, ry, rz & rx = ry $\asr$ rz$^{ }_{4:0}$ & \\
SHRL.PH & rx, ry, i$^{ }_{4}$ & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $\lsr$ i & Q \\
SHRL.QB & rx, ry, i$^{ }_{3}$ & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{Bn}$ $\lsr$ i & \\
SHRLV.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $\lsr$ rz$^{ }_{3:0}$ & Q \\
SHRLV.QB & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{Bn}$ $\lsr$ rz$^{ }_{2:0}$ & \\
SHILO & ac, i$^{ }_{6}$ & ac = (i $\slt$ 0) ? (ac $\lsl$ -i) : (ac $\lsr$ i) & \\
SHILOV & ac, ry & ac=(ry$^{ }_{5:0}$$\slt$0)?(ac$\lsl$-ry$^{ }_{5:0}$):(ac$\lsr$ry$^{ }_{5:0}$) & \\
\end{asmtabledsp}
%
\begin{asmtabledsp2}{DSP Multiplication Instructions}
DPa.W.PH & ac, ry, rz & ac = ac $\pm$ (ry$^{ }_{H1}$$\smul$rz$^{ }_{H1}$ $+$ ry$^{ }_{H0}$$\smul$rz$^{ }_{H0}$) & Q \\
DPaQ\_S.W.PH & ac, ry, rz & ac = ac $\pm$ (ry$^{ }_{H1}$$\smul$rz$^{ }_{H1}$ $+$ ry$^{ }_{H0}$$\smul$rz$^{ }_{H0}$) & \\
DPaQ\_SA.L.W & ac, ry, rz & ac = ac $\pm$ ry $\smul$ rz & \\
DPaQX\_S\{A\}.W.PH & ac, ry, rz & ac = ac $\pm$ (ry$^{ }_{H1}$$\smul$rz$^{ }_{H0}$ $+$ ry$^{ }_{H0}$$\smul$rz$^{ }_{H1}$) & Q \\
DPaU.H.QBL & ac, ry, rz & ac = ac $\pm$ (ry$^{ }_{B3}$$\umul$rz$^{ }_{B3}$ $+$ ry$^{ }_{B2}$$\umul$rz$^{ }_{B2}$) & \\
DPaU.H.QBR & ac, ry, rz & ac = ac $\pm$ (ry$^{ }_{B1}$$\umul$rz$^{ }_{B1}$ $+$ ry$^{ }_{B0}$$\umul$rz$^{ }_{B0}$) & \\
DPaX.W.PH & ac, ry, rz & ac = ac $\pm$ (ry$^{ }_{H1}$$\smul$rz$^{ }_{H0}$ $+$ ry$^{ }_{H0}$$\smul$rz$^{ }_{H1}$) & Q \\
M\{ADD|SUB\} & ac, ry, rz & ac = ac $\pm$ ry $\smul$ rz & \\
M\{ADD|SUB\}U & ac, ry, rz & ac = ac $\pm$ ry $\umul$ rz & \\
MAQ\_S\{A\}.W.PHL & ac, ry, rz & ac = ac $+$ ry$^{ }_{H1}$ $\smul$ rz$^{ }_{H1}$ & \\
MAQ\_S\{A\}.W.PHR & ac, ry, rz & ac = ac $+$ ry$^{ }_{H0}$ $\smul$ rz$^{ }_{H0}$ & \\
MUL\{\_S\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$$\smul$rz$^{ }_{Hn}$ & Q \\
MULEQ\_S.W.PHL & rx, ry, rz & rx = ry$^{ }_{H1}$ $\smul$ rz$^{ }_{H1}$ & \\
MULEQ\_S.W.PHR & rx, ry, rz & rx = ry$^{ }_{H0}$ $\smul$ rz$^{ }_{H0}$ & \\
MULEU\_S.PH.QBL & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{B(2+n)}$ $\smul$ rz$^{ }_{Hn}$ & \\
MULEU\_S.PH.QBR & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Bn}$ $\smul$ rz$^{ }_{Hn}$ & \\
MULQ\_\{R\}S.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = (ry$^{ }_{Hn}$$\smul$rz$^{ }_{Hn}$)$^{ }_{30:15}$ & Q \\
MULQ\_\{R\}S.W & rx, ry, rz & rx = (ry $\smul$ rz)$^{ }_{62:31}$ & Q \\
MULSA.W.PH & ac, ry, rz & ac = ac $+$ ry$^{ }_{H1}$$\smul$rz$^{ }_{H1}$ $-$ ry$^{ }_{H0}$$\smul$rz$^{ }_{H0}$ & Q \\
MULSAQ\_S.W.PH & ac, ry, rz & ac = ac $+$ ry$^{ }_{H1}$$\smul$rz$^{ }_{H1}$ $-$ ry$^{ }_{H0}$$\smul$rz$^{ }_{H0}$ & \\
MULT & ac, ry, rz & ac = ry $\smul$ rz & \\
MULTU & ac, ry, rz & ac = ry $\umul$ rz & \\
\end{asmtabledsp2}
%
\begin{asmtabledsp2}{DSP Pack Instructions}
PACKRL.PH & rx, ry, rz & rx = ry$^{ }_{H0}$:rz$^{ }_{H1}$ & \\
PRECEQ.W.PHL & rx, ry & rx = ry$^{ }_{H1}$:0$^{ }_{16}$ & \\
PRECEQ.W.PHR & rx, ry & rx = ry$^{ }_{H0}$:0$^{ }_{16}$ & \\
PRECEQU.PH.QBL & rx, ry & rx = 0:ry$^{ }_{B3}$:0$^{ }_{8}$:ry$^{ }_{B2}$:0$^{ }_{7}$ & \\
PRECEQU.PH.QBLA & rx, ry & rx = 0:ry$^{ }_{B3}$:0$^{ }_{8}$:ry$^{ }_{B1}$:0$^{ }_{7}$ & \\
PRECEQU.PH.QBR & rx, ry & rx = 0:ry$^{ }_{B1}$:0$^{ }_{8}$:ry$^{ }_{B0}$:0$^{ }_{7}$ & \\
PRECEQU.PH.QBRA & rx, ry & rx = 0:ry$^{ }_{B2}$:0$^{ }_{8}$:ry$^{ }_{B0}$:0$^{ }_{7}$ & \\
PRECEU.PH.QBL & rx, ry & rx = 0$^{ }_{8}$:ry$^{ }_{B3}$:0$^{ }_{8}$:ry$^{ }_{B2}$ & \\
PRECEU.PH.QBLA & rx, ry & rx = 0$^{ }_{8}$:ry$^{ }_{B3}$:0$^{ }_{8}$:ry$^{ }_{B1}$ & \\
PRECEU.PH.QBR & rx, ry & rx = 0$^{ }_{8}$:ry$^{ }_{B1}$:0$^{ }_{8}$:ry$^{ }_{B0}$ & \\
PRECEU.PH.QBRA & rx, ry & rx = 0$^{ }_{8}$:ry$^{ }_{B2}$:0$^{ }_{8}$:ry$^{ }_{B0}$ & \\
PRECR.QB.PH & rx, ry, rz & rx = ry$^{ }_{B2}$:ry$^{ }_{B0}$:rz$^{ }_{B2}$:rz$^{ }_{B0}$ & Q \\
PRECR\_SRA\{\_R\}.PH.W & rx, ry, i$^{ }_{5}$ & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $\asr$ i & Q \\
PRECRQ\{\_RS\}.PH.W & rx, ry, rz & rx = ry$^{ }_{H1}$:rz$^{ }_{H1}$ & \\
PRECRQ.QB.PH & rx, ry, rz & rx = ry$^{ }_{B3}$:ry$^{ }_{B1}$:rz$^{ }_{B3}$:rz$^{ }_{B1}$ & \\
PRECRQU\_S.QB.PH & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = (ry:rz)$^{ }_{Hn}$ $\asr$ 7 & \\
REPL.PH & rx, i$^{ }_{10}$ & for(n=0..1) rx$^{ }_{Hn}$ = i$^{\pm}_{ }$ & \\
REPL.QB & rx, i$^{ }_{8}$ & for(n=0..3) rx$^{ }_{Bn}$ = i & \\
REPLV.PH & rx, ry & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{H0}$ & \\
REPLV.QB & rx, ry & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{B0}$ & \\
\end{asmtabledsp2}
%
\begin{asmtabledsp}{DSP Arithmetic Instructions}
ABSQ\_S.PH & rx, ry & for(n=0..1) rx$^{ }_{Hn}$ = ABS(ry$^{ }_{Hn}$) & \\
ABSQ\_S.QB & rx, ry & for(n=0..3) rx$^{ }_{Bn}$ = ABS(ry$^{ }_{Bn}$) & Q \\
ABSQ\_S.W & rx, ry & rx = ABS(ry) & \\
ADDQ\{\_S\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $+$ rz$^{ }_{Hn}$ & \\
ADDQ\_S.W & rx, ry, rz & rx = ry $+$ rz & \\
ADDQH\{\_R\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = (ry$^{ }_{Hn}$ $+$ rz$^{ }_{Hn}$) $\lsr$ 1 & Q \\
ADDQH\{\_R\}.W & rx, ry, rz & rx = (ry $+$ rz) $\lsr$ 1 & Q \\
ADDSC & rx, ry, rz & c:rx = ry $+$ rz & \\
ADDU\{\_S\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $+$ rz$^{ }_{Hn}$ & Q \\
ADDU\{\_S\}.QB & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{Bn}$ $+$ rz$^{ }_{Bn}$ & \\
ADDUH\{\_R\}.QB & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = (ry$^{ }_{Bn}$ $+$ rz$^{ }_{Bn}$) $\lsr$ 1 & Q \\
ADDWC & rx, ry, rz & rx = ry $+$ rz $+$ c & \\
CMP.cc.PH & rx, ry & for(n=0..1) ccond$^{ }_{n}$ = rx$^{ }_{Hn}$ $\bar{\circ}$ ry$^{ }_{Hn}$ & \\
CMPGU.cc.QB & rx, ry, rz & rx=0; for(n=0..3) rx$^{ }_{n}$ = ry$^{ }_{Bn}$ $\circ$ rz$^{ }_{Bn}$ & \\
CMPGDU.cc.QB & rx, ry, rz & rx=0; f(n=0..3) rx$^{ }_{n}$=ccond$^{ }_{n}$=ry$^{ }_{Bn}$$\circ$rz$^{ }_{Bn}$ & Q \\
CMPU.cc.PH & rx, ry & for(n=0..1) ccond$^{ }_{n}$ = rx$^{ }_{Hn}$ $\circ$ ry$^{ }_{Hn}$ & \\
MODSUB & rx, ry, rz & rx = (ry $=$ 0) ? rz$^{\emptyset}_{23:8}$ : ry - rz$^{\emptyset}_{7:0}$ & \\
RADDU.W.QB & rx, ry & rx = ry$^{\emptyset}_{B3}$ $+$ ry$^{\emptyset}_{B2}$ $+$ ry$^{\emptyset}_{B1}$ $+$ ry$^{\emptyset}_{B0}$ & \\
SUBQ\{\_S\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $-$ rz$^{ }_{Hn}$ & \\
SUBQ\_S.W & rx, ry, rz & rx = ry $-$ rz & \\
SUBQH\{\_R\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = (ry$^{ }_{Hn}$ $-$ rz$^{ }_{Hn}$) $\lsr$ 1 & Q \\
SUBQH\{\_R\}.W & rx, ry, rz & rx = (ry $-$ rz) $\lsr$ 1 & Q \\
SUBU\{\_S\}.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = ry$^{ }_{Hn}$ $-$ rz$^{ }_{Hn}$ & Q \\
SUBU\{\_S\}.QB & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = ry$^{ }_{Bn}$ $-$ rz$^{ }_{Bn}$ & \\
SUBUH\{\_R\}.QB & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = (ry$^{ }_{Bn}$ $-$ rz$^{ }_{Bn}$) $\lsr$ 1 & Q \\
\end{asmtabledsp}
%
\begin{asmtabledsp}{DSP Data Transfer and Control Instructions}
BPOSGE32 & rel$^{ }_{18}$ & if (pos $\uge$ 32) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & \\
LBUX & rx, ry(rz) & rx = [ry $+$ rz]$^{\emptyset}_{8}$ & \\
LHX & rx, ry(rz) & rx = [ry $+$ rz]$^{\pm}_{16}$ & \\
LWX & rx, ry(rz) & rx = [ry $+$ rz] & \\
MFHI & rx, ac & rx = ac$^{ }_{63:32}$ & \\
MFLO & rx, ac & rx = ac$^{ }_{31:0}$ & \\
MTHI & rx, ac & ac$^{ }_{63:32}$ = rx & \\
MTLO & rx, ac & ac$^{ }_{31:0}$ = rx & \\
PICK.PH & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = (ccond$^{ }_{n}$ ? ry : rz)$^{ }_{Hn}$ & \\
PICK.QB & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = (ccond$^{ }_{n}$ ? ry : rz)$^{ }_{Bn}$ & \\
RDDSP & rx\{, i$^{ }_{10}$\} & rx = DSPC \& mask & \\
WRDSP & rx\{, i$^{ }_{10}$\} & DSPC \& mask = rx & \\
\end{asmtabledsp}
%
\end{multicols}
\end{document}