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%
% Copyright (C) 2014-2020 Anders Sonmark
%
% Copying and distribution of this file, with or without modification,
% are permitted in any medium without royalty provided the copyright
% notice and this notice are preserved. This file is offered as-is,
% without any warranty.
%
\documentclass{sheet}
\usepackage[utf8]{inputenc}
\usepackage[T1]{fontenc}
\usepackage{ae,aecompl}
\usepackage[english]{babel}
\usepackage[a4paper, landscape, margin=.1in]{geometry}
\usepackage{amssymb}
\usepackage{verbatim}
\usepackage{ulem}
\usepackage{makecell}
\def\sheetheaderfont{\bfseries}
\def\sheettablefont{\footnotesize\sffamily}
\def\sheetheadercolor{black!10}
\def\sheetrowcolor{black!5}
\newcolumntype{N}{>{\raggedleft\arraybackslash}m{1.7em}}
\def\tabcolsep{2pt}
\def\arraystretch{1.3}
\defsheet{asmtable}{4}{|m{4.6em} m{6.7em}|X|N|}
\defsheet{asmtable2}{4}{|m{6.5em} m{5.3em}|X|N|}
\defsheet{asmtable3}{4}{|m{5.0em} m{8.0em}|X|N|}
\defsheet{table-lX}{2}{|l X|}
\defsheet{table-lXN}{3}{|l|X|N|}
\defsheet{table-llX}{3}{|l l X|}
\defsheet{table-llXr}{4}{|l l X r|}
\pagefooter{ARM AArch32 version 9 page \thepage}
\begin{document}
\begin{multicols}{3}
\raggedcolumns
\begin{center}
{\Large\bfseries ARM AArch32 Quick Reference}
\end{center}
%
\begin{asmtable}{Arithmetic Instructions}
ADC\{S\} & rx, ry, op2 & rx = ry $+$ op2 $+$ C & \\
ADD\{S\} & rx, ry, op2 & rx = ry $+$ op2 & \\
ADDW & rx, ry, \#i$^{ }_{12}$ & rx = ry $+$ i$^{\emptyset}_{ }$ & T \\
ADR & rx, $\pm$rel$^{ }_{12}$ & rx = PC $+$ rel$^{\pm}_{ }$ & \\
CMN & rx, op2 & rx $+$ op2 & \\
CMP & rx, op2 & rx $-$ op2 & \\
QADD & rx, ry, rz & rx = SATS(ry $+$ rz, 32) & D \\
QDADD & rx, ry, rz & rx = SATS(ry $+$ SATS(2$\times$rz, 32), 32) & D \\
QDSUB & rx, ry, rz & rx = SATS(ry $-$ SATS(2$\times$rz, 32), 32) & D \\
QSUB & rx, ry, rz & rx = SATS(ry $-$ rz, 32) & D \\
RSB\{S\} & rx, ry, op2 & rx = op2 $-$ ry & \\
RSC\{S\} & rx, ry, op2 & rx = op2 $-$ (ry $+$ C) & A \\
SBC\{S\} & rx, ry, op2 & rx = ry $-$ (op2 $+$ C) & \\
SDIV & rx, ry, rz & rx = ry $\sdiv$ rz & 7 \\
SSAT & rx, \#j$^{ }_{5}$, ry\{slr\} & rx = SATS(ry $\lsl\asr$ sh, j)$^{\pm}_{ }$ & 6 \\
SSAT16 & rx, \#j$^{ }_{4}$, ry & rx = SATS(ry$^{\pm}_{H1}$, j)$^{\pm}_{ }$:SATS(ry$^{\pm}_{H0}$, j)$^{\pm}_{ }$ & 6,D \\
SUB\{S\} & rx, ry, op2 & rx = ry $-$ op2 & \\
SUBW & rx, ry, \#i$^{ }_{12}$ & rx = ry $-$ i$^{\emptyset}_{ }$ & T \\
UDIV & rx, ry, rz & rx = ry $\udiv$ rz & 7 \\
USAD8 & rx, ry, rz & rx = $\sum_{n=0}^{3}$($\lvert$ry$^{\emptyset}_{Bn}$$\rvert$ $-$ rz$^{\emptyset}_{Bn}$) & 6,D \\
USADA8 & rx, ry, rz, rw & rx = rw $+$ $\sum_{n=0}^{3}$($\lvert$ry$^{\emptyset}_{Bn}$$\rvert$ $-$ rz$^{\emptyset}_{Bn}$) & 6,D \\
USAT & rx, \#j$^{ }_{5}$, ry\{slr\} & rx = SATU(ry $\lsl\asr$ sh, j)$^{\pm}_{ }$ & 6 \\
USAT16 & rx, \#i$^{ }_{4}$, ry & rx = SATU(ry$^{\pm}_{H1}$, i)$^{\pm}_{ }$:SATU(ry$^{\pm}_{H0}$, i)$^{\pm}_{ }$ & 6,D \\
\end{asmtable}
%
\begin{table-lXN}{Operand 2}
\#i$^{ }_{32}$ & i$^{ }_{8}$ $\ror$ i$^{ }_{4}$:0 & A \\
\#i$^{ }_{32}$ & 0$^{ }_{24}$:i$^{ }_{8}$, 0$^{ }_{8}$:i$^{ }_{8}$0$^{ }_{8}$:i$^{ }_{8}$, i$^{ }_{8}$:0$^{ }_{8}$i$^{ }_{8}$:0$^{ }_{8}$ or i$^{ }_{8}$:i$^{ }_{8}$i$^{ }_{8}$:i$^{ }_{8}$ & T \\
\#i$^{ }_{32}$ & 1:i$^{ }_{7}$ $\lsl$ \{1..24\} & T \\
rz & rz & \\
rz, LSL \#n & rz $\lsl$ \{1..31\} & \\
rz, LSR \#n & rz $\lsr$ \{1..32\} & \\
rz, ASR \#n & rz $\asr$ \{1..32\} & \\
rz, ROR \#n & rz $\ror$ \{1..31\} & \\
rz, RRX & C:rz$^{ }_{31:1}$; C = rz$^{ }_{0}$ & \\
rz, LSL rw & rz $\lsl$ rw & A \\
rz, LSR rw & rz $\lsr$ rw & A \\
rz, ASR rw & rz $\asr$ rw & A \\
rz, ROR rw & rz $\ror$ rw & A \\
\end{table-lXN}
%
\begin{asmtable}{Bitwise and Move Instructions}
AND\{S\} & rx, ry, op2 & rx = ry \& op2 & \\
\textit{ASR\{S\}} & rx, ry, \#j$^{ }_{5}$ & rx = ry $\asr$ j & \\
\textit{ASR\{S\}} & rx, ry, Rs & rx = ry $\asr$ Rs & \\
BFC & rx, \#p, \#n & rx$^{ }_{p+n-1:p}$ = 0$^{ }_{n}$ & 6t \\
BFI & rx, ry, \#p, \#n & rx$^{ }_{p+n-1:p}$ = ry$^{ }_{n-1:0}$ & 6t \\
BIC\{S\} & rx, ry, op2 & rx = ry \& $\sim$op2 & \\
CLZ & rx, ry & rx = CountLeadingZeros(ry) & \\
EOR\{S\} & rx, ry, op2 & rx = ry $\oplus$ op2 & \\
\textit{LSL\{S\}} & rx, ry, \#i$^{ }_{5}$ & rx = ry $\lsl$ i & \\
\textit{LSL\{S\}} & rx, ry, Rs & rx = ry $\lsl$ Rs & \\
\textit{LSR\{S\}} & rx, ry, \#j$^{ }_{5}$ & rx = ry $\lsr$ j & \\
\textit{LSR\{S\}} & rx, ry, Rs & rx = ry $\lsr$ Rs & \\
MOV\{S\} & rx, op2 & rx = op2 & \\
MOVT & rx, \#i$^{ }_{16}$ & rx$^{ }_{31:16}$ = i & 6t \\
MOVW & rx, \#i$^{ }_{16}$ & rx = i$^{\emptyset}_{ }$ & 6t \\
MVN\{S\} & rx, op2 & rx = $\sim$op2 & \\
ORN\{S\} & rx, ry, op2 & rx = ry | $\sim$op2 & T \\
ORR\{S\} & rx, ry, op2 & rx = ry | op2 & \\
RBIT & rx, ry & rx = ReverseBits(ry) & 6t \\
REV & rx, ry & rx = ry$^{ }_{B0}$:ry$^{ }_{B1}$:ry$^{ }_{B2}$:ry$^{ }_{B3}$ & 6 \\
REV16 & rx, ry & rx = ry$^{ }_{B2}$:ry$^{ }_{B3}$:ry$^{ }_{B0}$:ry$^{ }_{B1}$ & 6 \\
REVSH & rx, ry & rx = ry$^{\pm}_{B0}$:ry$^{ }_{B1}$ & 6 \\
\textit{ROR\{S\}} & rx, ry, \#i$^{ }_{5}$ & rx = ry $\ror$ i & \\
\textit{ROR\{S\}} & rx, ry, Rs & rx = ry $\ror$ Rs & \\
\textit{RRX\{S\}} & rx, ry & rx = C:ry$^{ }_{31:1}$; C = ry$^{ }_{0}$ & \\
SBFX & rx, ry, \#p, \#n & rx = ry$^{\pm}_{p+n-1:p}$ & 6t \\
TEQ & rx, op2 & rx $\oplus$ op2 & \\
TST & rx, op2 & rx \& op2 & \\
UBFX & rx, ry, \#p, \#n & rx = ry$^{\emptyset}_{p+n-1:p}$ & 6t \\
\end{asmtable}
%
\begin{asmtable}{Branch and Jump Instructions}
B & rel$^{ }_{26}$ & PC = PC $+$ rel$^{\pm}_{25:2}$:0$^{ }_{1:0}$ & A \\
B & rel$^{ }_{25}$ & PC = PC $+$ rel$^{\pm}_{24:1}$:0 & T \\
Bcc & rel$^{ }_{21}$ & if(cc) PC = PC $+$ rel$^{\pm}_{20:1}$:0 & I \\
BKPT & \#i$^{ }_{16}$ & BreakPoint(i) & I \\
BL & rel$^{ }_{26}$ & LR=PC$^{ }_{31:1}$:0; PC$+$=rel$^{\pm}_{25:2}$:0$^{ }_{1:0}$ & A \\
BL & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1; PC$+$=rel$^{\pm}_{24:1}$:0 & T \\
BLX & rel$^{ }_{26}$ & LR=PC$^{ }_{31:1}$:0; Set=1; PC$+$=rel$^{\pm}_{25:1}$:0 & A \\
BLX & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1; Set=0; PC$+$=rel$^{\pm}_{24:2}$:0$^{ }_{1:0}$ & T \\
BLX & rx & LR=PC$^{ }_{31:1}$:0; Set=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0 & A \\
BX & rx & Set = rx$^{ }_{0}$; PC = rx$^{ }_{31:1}$:0 & A \\
%BXJ & rx & Set=2; PC = rx$^{ }_{31:1}$:0 & \\
TBB & [rx, ry] & PC = PC $+$ 2 $\umul$ [rx $+$ ry]$^{\emptyset}_{8}$ & T \\
TBH & [rx, ry, LSL \#1] & PC = PC $+$ 2 $\umul$ [rx $+$ 2 $\umul$ ry]$^{\emptyset}_{16}$ & T \\
\end{asmtable}
%
\begin{asmtable}{Load and Store Instructions}
LDMDA & rx\{!\}, rlist & rlist = [rx$-$4$\times$cnt$+$4]; if(!) rx$-$=4$\times$cnt & A \\
LDMDB & rx\{!\}, rlist & rlist = [rx $-$ 4$\times$cnt]; if(!) rx$-$=4$\times$cnt & \\
LDM\textit{IA} & rx\{!\}, rlist & rlist = [rx]; if(!) rx $+$= 4$\times$cnt & \\
LDMIB & rx\{!\}, rlist & rlist = [rx $+$ 4]; if(!) rx $+$= 4$\times$cnt & A \\
LDR\{T\} & rx, [addr] & rx = [addr] & \\
LDRB\{T\} & rx, [addr] & rx = [addr]$^{\emptyset}_{8}$ & \\
LDRD & rx, ry, [addr] & ry:rx = [addr] & \\
LDRH\{T\} & rx, [addr] & rx = [addr]$^{\emptyset}_{16}$ & \\
LDRSB\{T\} & rx, [addr] & rx = [addr]$^{\pm}_{8}$ & \\
LDRSH\{T\} & rx, [addr] & rx = [addr]$^{\pm}_{16}$ & \\
\textit{POP} & rlist & rlist = [SP]; SP $+$= 4$\times$cnt & \\
\textit{PUSH} & rlist & SP $-$= 4$\times$cnt; [SP] = rlist & \\
STMDA & rx\{!\}, rlist & [rx$-$4$\times$cnt$+$4] = rlist; if(!) rx$-$=4$\times$cnt & A \\
STMDB & rx\{!\}, rlist & [rx $-$ 4$\times$cnt] = rlist; if(!) rx$-$=4$\times$cnt & \\
STM\textit{IA} & rx\{!\}, rlist & [rx] = rlist; if(!) rx $+$= 4$\times$cnt & \\
STMIB & rx\{!\}, rlist & [rx$+$4] = rlist; if(!) rx $+$= 4$\times$cnt & A \\
STR\{T\} & rx, [addr] & [addr] = rx & \\
STRB\{T\} & rx, [addr] & [addr]$^{ }_{8}$ = rx$^{ }_{B0}$ & \\
STRD & rx, ry, [addr] & [addr] = ry:rx & \\
STRH\{T\} & rx, [addr] & [addr]$^{ }_{16}$ = rx$^{ }_{H0}$ & \\
\end{asmtable}
%
\begin{table-llX}{ARM LDR/STR Addressing Modes}
non-T & [rz\{, \#$\pm$i$^{ }_{8}$\}]\{!\} & addr = rz $+$ i$^{\pm}_{ }$; if(!) rz = addr \\
xxR\{,B\} & [rz\{, \#$\pm$i$^{ }_{12}$\}]\{!\} & addr = rz $+$ i$^{\pm}_{ }$; if(!) rz = addr \\
any & [rz]\{, \#$\pm$i$^{ }_{8}$\} & addr = rz; rz $+$= i$^{\pm}_{ }$ \\
xxR\{,B\}\{T\} & [rz], \#$\pm$i$^{ }_{12}$ & addr = rz; rz $+$= i$^{\pm}_{ }$ \\
non-T & [rz, $\pm$rw]\{!\} & addr = rz $\pm$ rw; if(!) rz = addr \\
xxR\{,B\} & [rz, $\pm$rw\{AS\}]\{!\} & addr = rz $\pm$ AS(rw); if(!) rz = addr \\
any & [rz], $\pm$rw & addr = rz; rz $\pm$= rw \\
xxR\{,B\}\{T\} & [rz], $\pm$rw\{AS\} & addr = rz; rz $\pm$= AS(rw) \\
LD non-T & $\pm$rel$^{ }_{8}$ & addr = PC $+$ rel$^{\pm}_{ }$ \\
LDR\{,B\} & $\pm$rel$^{ }_{12}$ & addr = PC $+$ rel$^{\pm}_{ }$ \\
\end{table-llX}
%
\begin{table-llX}{Thumb2 LDR/STR Addressing Modes}
any & [rz\{, \#i$^{ }_{8}$\}] & addr = rz $+$ i$^{\emptyset}_{ }$ \\
xxR\{,B,H,SB,SH\} & [rz, \#i$^{ }_{12}$] & addr = rz $+$ i$^{\emptyset}_{ }$ \\
xxR\{,B,H,SB,SH\} & [rz, \#$\pm$i$^{ }_{8}$]\{!\} & addr = rz $+$ i$^{\pm}_{ }$; if(!) rz = addr \\
xxR\{,B,H,SB,SH\} & [rz], \#$\pm$i$^{ }_{8}$ & addr = rz; rz $+$= i$^{\pm}_{ }$ \\
xxR\{,B,H,SB,SH\} & [rz,rw\{,LSL \#i$^{ }_{2}$\}] & addr = rz $+$ rw $\lsl$ i \\
LDR\{,B,H,SB,SH\} & $\pm$rel$^{ }_{12}$ & addr = PC $+$ rel$^{\pm}_{ }$ \\
xxRD & [rz\{, \#$\pm$i$^{ }_{10}$\}]\{!\} & addr=rz$+$i$^{\pm}_{9:2}$:0$^{ }_{1:0}$; if(!) rz=addr \\
xxRD & [rz], \#$\pm$i$^{ }_{10}$ & addr = rz; rz $+$= i$^{\pm}_{9:2}$:0$^{ }_{1:0}$ \\
LDRD & $\pm$rel$^{ }_{10}$ & addr = PC $+$ rel$^{\pm}_{9:2}$:0$^{ }_{1:0}$ \\
\end{table-llX}
%
\begin{asmtable}{Multiplication Instructions}
MLA & rx, ry, rz, rw & rx = rw $+$ ry $\umul$ rz & \\
MLA\{S\} & rx, ry, rz, rw & rx = rw $+$ ry $\umul$ rz & A \\
MLS & rx, ry, rz, rw & rx = rw $-$ ry $\umul$ rz & 6t \\
MUL & rx, ry, rz & rx = ry $\umul$ rz & \\
MUL\{S\} & rx, ry, rz & rx = ry $\umul$ rz & A \\
SMLAxy & rx, ry, rz, rw & rx = rw $+$ ry$^{\pm}_{Hx}$ $\smul$ rz$^{\pm}_{Hy}$ & D \\
SMLaD & rx, ry, rz, rw & rx = rw $+$ ry$^{\pm}_{H0}$$\smul$rz$^{\pm}_{H0}$ $\pm$ ry$^{\pm}_{H1}$$\smul$rz$^{\pm}_{H1}$ & 6,D \\
SMLaDX & rx, ry, rz, rw & rx = rw $+$ ry$^{\pm}_{H0}$$\smul$rz$^{\pm}_{H1}$ $\pm$ ry$^{\pm}_{H1}$$\smul$rz$^{\pm}_{H0}$ & D \\
SMLaLD & rx, ry, rz, rw & ry:rx $+$= rz$^{\pm}_{H0}$$\smul$rw$^{\pm}_{H0}$ $\pm$ rz$^{\pm}_{H1}$$\smul$rw$^{\pm}_{H1}$ & 6,D \\
SMLaLDX & rx, ry, rz, rw & ry:rx $+$= rz$^{\pm}_{H0}$$\smul$rw$^{\pm}_{H1}$ $\pm$ rz$^{\pm}_{H1}$$\smul$rw$^{\pm}_{H0}$ & D \\
SMLAL & rx, ry, rz, rw & ry:rx $+$= rz $\smul$ rw & \\
SMLAL\{S\} & rx, ry, rz, rw & ry:rx $+$= rz $\smul$ rw & A \\
SMLALxy & rx, ry, rz, rw & ry:rx $+$= rz$^{\pm}_{Hx}$ $\smul$ rw$^{\pm}_{Hy}$ & D \\
SMLAWy & rx, ry, rz, rw & rx = rw $+$ ry $\smul$ rz$^{\pm}_{Hy}$ & D \\
SMMLa & rx, ry, rz, rw & rx = rw $\pm$ (ry $\smul$ rz)$^{ }_{63:32}$ & 6,D \\
SMMLaR & rx, ry, rz, rw & rx = rw $\pm$ (ry$\smul$rz $+$ 0x80000000)$^{ }_{63:32}$ & D \\
SMMUL & rx, ry, rz & rx = (ry $\smul$ rz)$^{ }_{63:32}$ & 6,D \\
SMMULR & rx, ry, rz & rx = (ry $\smul$ rz $+$ 0x80000000)$^{ }_{63:32}$ & D \\
SMUaD & rx, ry, rz & rx = ry$^{\pm}_{H0}$ $\smul$ rz$^{\pm}_{H0}$ $\pm$ ry$^{\pm}_{H1}$ $\smul$ rz$^{\pm}_{H1}$ & 6,D \\
SMUaDX & rx, ry, rz & rx = ry$^{\pm}_{H0}$ $\smul$ rz$^{\pm}_{H1}$ $\pm$ ry$^{\pm}_{H1}$ $\smul$ rz$^{\pm}_{H0}$ & D \\
SMULxy & rx, ry, rz & rx = ry$^{\pm}_{Hx}$ $\smul$ rz$^{\pm}_{Hy}$ & D \\
SMULL & rx, ry, rz, rw & ry:rx = rz $\smul$ rw & \\
SMULL\{S\} & rx, ry, rz, rw & ry:rx = rz $\smul$ rw & A \\
SMULWy & rx, ry, rz & rx = (ry $\smul$ rz$^{\pm}_{Hy}$)$^{ }_{47:16}$ & D \\
UMAAL & rx, ry, rz, rw & ry:rx = ry $+$ rx $+$ rz $\umul$ rw & D \\
UMLAL & rx, ry, rz, rw & ry:rx $+$= rz $\umul$ rw & \\
UMULL & rx, ry, rz, rw & ry:rx = rz $\umul$ rw & \\
\end{asmtable}
%
\begin{asmtable}{Parallel Instructions}
pADD16 & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = p(ry$^{ }_{Hn}$ $+$ rz$^{ }_{Hn}$) & 6,D \\
pADD8 & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = p(ry$^{ }_{Bn}$ $+$ rz$^{ }_{Bn}$) & 6,D \\
pASX & rx, ry, rz & rx = p(ry$^{ }_{H1}$ $+$ rz$^{ }_{H0}$):p(ry$^{ }_{H0}$ $-$ rz$^{ }_{H1}$) & 6,D \\
pSAX & rx, ry, rz & rx = p(ry$^{ }_{H1}$ $-$ rz$^{ }_{H0}$):p(ry$^{ }_{H0}$ $+$ rz$^{ }_{H1}$) & 6,D \\
pSUB16 & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = p(ry$^{ }_{Hn}$ $-$ rz$^{ }_{Hn}$) & 6,D \\
pSUB8 & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = p(ry$^{ }_{Bn}$ $-$ rz$^{ }_{Bn}$) & 6,D \\
SEL & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = (GEn ? ry : rz)$^{ }_{Bn}$ & 6,D \\
\end{asmtable}
%
\begin{table-lX}{Parallel Instruction Prefixes}
Q & Signed operation, Results are saturated \\
S & Signed operation, Results are truncated \\
SH & Signed operation, Results are right shifted by one \\
U & Unsigned operation, Results are truncated \\
UH & Unsigned operation, Results are right shifted by one \\
UQ & Unsigned operation, Results are saturated \\
\end{table-lX}
%
\begin{asmtable}{Packing and Unpacking Instructions}
PKHBT & rx, ry, rz\{sl\} & rx = (rz $\lsl$ sh)$^{ }_{H1}$:ry$^{ }_{H0}$ & 6,D \\
PKHTB & rx, ry, rz\{sr\} & rx = ry$^{ }_{H1}$:(rz $\asr$ sh)$^{ }_{H0}$ & 6,D \\
SXTAB & rx, ry, rz\{rb\} & rx = ry $+$ (rz $\ror$ sh)$^{\pm}_{B0}$ & 6,D \\
SXTAB16 & rx, ry, rz\{rb\} & for(n=0..1) rx$^{ }_{Hn}$=ry$^{ }_{Hn}$$+$(rz$\ror$sh)$^{\pm}_{B2n}$ & 6,D \\
SXTAH & rx, ry, rz\{rb\} & rx = ry $+$ (rz $\ror$ sh)$^{\pm}_{H0}$ & 6,D \\
SXTB & rx, ry\{rb\} & rx = (ry $\ror$ sh)$^{\pm}_{B0}$ & 6 \\
SXTB16 & rx, ry\{rb\} & for(n=0..1) rx$^{ }_{Hn}$ = (ry $\ror$ sh)$^{\pm}_{B2n}$ & 6,D \\
SXTH & rx, ry\{rb\} & rx = (ry $\ror$ sh)$^{\pm}_{H0}$ & 6 \\
UXTAB & rx, ry, rz\{rb\} & rx = ry $+$ (rz $\ror$ sh)$^{\emptyset}_{B0}$ & 6,D \\
UXTAB16 & rx, ry, rz\{rb\} & for(n=0..1) rx$^{ }_{Hn}$=ry$^{ }_{Hn}$$+$(rz$\ror$sh)$^{\emptyset}_{B2n}$ & 6,D \\
UXTAH & rx, ry, rz\{rb\} & rx = ry $+$ (rz $\ror$ sh)$^{\emptyset}_{H0}$ & 6,D \\
UXTB & rx, ry\{rb\} & rx = (ry $\ror$ sh)$^{\emptyset}_{B0}$ & 6 \\
UXTB16 & rx, ry\{rb\} & for(n=0..1) rx$^{ }_{Hn}$ = (ry $\ror$ sh)$^{\emptyset}_{B2n}$ & 6,D \\
UXTH & rx, ry\{rb\} & rx = (ry $\ror$ sh)$^{\emptyset}_{H0}$ & 6 \\
\end{asmtable}
%
\begin{asmtable}{Exclusive Load and Store Instructions}
CLREX & & ClearExclusiveLocal() & I,6k \\
LDREX & rx, [ry] & rx = [ry]; SetExclusiveMonitor & 6k \\
LDREX & rx, [ry, \#i$^{ }_{10}$] & rx = [ry$+$i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$]; SetExclusiveMonitor & T,6k \\
LDREXB & rx, [ry] & rx = [ry]$^{\emptyset}_{8}$; SetExclusiveMonitor & 6k \\
LDREXD & rx, ry, [rz] & ry:rx = [rz]; SetExclusiveMonitor & 6k \\
LDREXH & rx, [ry] & rx = [ry]$^{\emptyset}_{16}$; SetExclusiveMonitor & 6k \\
STREX & rx,ry,[rz] & if(Pass) [rz] = ry; rx = Pass ? 1 : 0 & 6k \\
STREX & rx,ry,[rz,\#i$^{ }_{10}$] & if(Pass) [rz$+$i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$]=ry; rx=Pass?1:0 & T,6k \\
STREXB & rx,ry,[rz] & if(Pass) [rz]$^{ }_{8}$ = ry$^{ }_{B0}$; rx = Pass?1:0 & 6k \\
STREXD & rx,ry,rz,[rw] & if(Pass) [rw] = rz:ry; rx = Pass?1:0 & 6k \\
STREXH & rx,ry,[rz] & if(Pass) [rz]$^{ }_{16}$ = ry$^{ }_{H0}$; rx = Pass?1:0 & 6k \\
\end{asmtable}
%
\begin{asmtable}{System Instructions}
CPSI\{D,E\} & \{aif\}\{, \#mode\} & \{a\}\{i\}\{f\} = (E ? 1: 0); MODE = mode & 6 \\
CPS & \#mode & MODE = mode & 6 \\
ERET & & PC = LR; CPSR = SPSR & 7 \\
HVC & \#i$^{ }_{16}$ & CallHypervisor(i) & 7 \\
MRS & rx, xPSR & rx = \{CPSR,SPSR\} & \\
MRS & rx, Rbanked & rx = Rbanked & 7 \\
MSR & xPSR, rx & \{CPSR,SPSR\} = rx & \\
MSR & Rbanked, rx & Rbanked = rx & 7 \\
MSR & xPSR\_\{cxsf\}, i & \{CPSR,SPSR\}$^{ }_{f,s,x,c}$ = i$^{ }_{f,s,x,c}$ & A \\
MSR & xPSR\_\{cxsf\}, rx & \{CPSR,SPSR\}$^{ }_{f,s,x,c}$ = rx$^{ }_{f,s,x,c}$ & \\
RFEdi & rx\{!\} & LDMdi rx\{!\}, \{PC, CPSR\} & \\
SMC & \#i$^{ }_{4}$ & CallSecureMonitor(i) & 6k \\
SRSdi & SP\{!\}, \#mode & STMdi SP\_mode\{!\}, \{LR, SPSR\} & 6 \\
\end{asmtable}
%
\begin{asmtable}{Special Instructions}
DBG & \#i$^{ }_{4}$ & DebugHint(i) & 7 \\
DMB & option & DataMemoryBarrier(option) & I,7 \\
DSB & option & DataSynchronizationBarrier(option) & I,7 \\
ISB & SY & InstructionSynchronizationBarrier(SY) & I,7 \\
NOP & & & 6k \\
PLD\{W\} & [addr] & PreloadData(addr) & \\
%PLD\{W\} & [rx, \#i$^{ }_{12}$] & PreloadData(rx $+$ i) & \\
%PLD\{W\} & [rx, \#$-$i$^{ }_{8}$] & PreloadData(rx $-$ i) & \\
%PLD\{W\} & [rx, \#$-$i$^{ }_{12}$] & PreloadData(rx $-$ i) & A \\
%PLD & $\pm$rel$^{ }_{12}$ & PreloadData(PC $\pm$ rel) & \\
%PLD\{W\} & [rx, ry\{, LSL \#i$^{ }_{2}$\}] & PreloadData(rx $+$ ry $\lsl$ i) & \\
%PLD\{W\} & [rx, $\pm$ry\{AS\}] & PreloadData(rx $\pm$ AS(ry)) & A \\
PLI & [addr] & PreloadInstr(addr) & 7 \\
%PLI & [rx, \#i$^{ }_{12}$] & PreloadInstr(rx $+$ i) & 7 \\
%PLI & [rx, \#$-$i$^{ }_{8}$] & PreloadInstr(rx $-$ i) & 7 \\
%PLI & [rx, \#$-$i$^{ }_{12}$] & PreloadInstr(rx $-$ i) & A,7 \\
%PLI & $\pm$rel$^{ }_{12}$ & PreloadInstr(PC $\pm$ rel) & 7\\
%PLI & [rx, ry\{, LSL \#i$^{ }_{2}$\}] & PreloadInstr(rx $+$ ry $\lsl$ i) & 7 \\
%PLI & [rx, $\pm$ry\{AS\}] & PreloadInstr(rx $\pm$ AS(ry)) & A,7 \\
SETEND & \{BE/LE\} & EndianState = \{BE/LE\} & I,6 \\
SEV & & SendEvent() & 6k \\
SVC & \#i$^{ }_{24}$ & CallSupervisor(i) & A \\
UDF & \#i$^{ }_{16}$ & UndefinedException(i) & \\
WFE & & WaitForEvent() & 6k \\
WFI & & WaitForInterrupt() & 6k \\
YIELD & & HintYield() & 6k \\
\end{asmtable}
%
\begin{table-lX}{Keys}
\{S\} & Optional suffix, if present update flags \\
\{t\} & Conditional for additional instructions (T or E) \\
\{T\} & LDR/STR instruction uses user privileges. \\
a & A or S to add or subtract operand. \\
x, y & Selects bottom (B) or top (T) half of register(s) \\
cc & Condition code (can suffix most ARM instructions) \\
di & DA, DB, IA or IB for decrease/increase before/after. \\
i, j & Immediate operand, range 0..max / 1..max+1 \\
rx, ry, rz, rw & General register \\
Rbanked & Banked register \\
rlist & Comma separated list of registers within \{ \}. \\
op2 & Immediate or shifted register \\
xPSR & APSR, CPSR or SPSR \\
SAT\{S,U\}(x,b) & Saturated signed/unsigned b bit value \\
B\{0,1,2,3\} & Selected byte (bits 7:0, 15:8, 23:16 or 31:24) \\
H\{0,1\} & Selected half word (bits 15:0 or 31:16) \\
\{rb\} & Optional rotate (ROR 8, ROR 16 or ROR 24) \\
\{slr\} & Optional shift (LSL \#\{1..31\} or ASR \#\{1..32\}) \\
\{sl\} & Optional left shift (LSL \#\{1..31\}) \\
\{sr\} & Optional right shift (ASR \#\{1..32\}) \\
\{AS\} & ARM shift or rotate (LSL/ROR \#\{1..31\}, LSR/ASR \#\{1..32\} or RRX) \\
value$^{\pm}_{ }$, value$^{\emptyset}_{ }$ & Value is sign/zero extended\\
$\smul$ $\sdiv$ $\asr$ & Operation is signed \\
$\lvert$x$\rvert$ & Absolute of value \\
\end{table-lX}
%
\begin{table-llX}{General Registers}
R0-R3 & & Arguments and return values (useable by Thumb16) \\
R4-R7 & & General purpose (must be preserved, useable by Thumb16) \\
R8-R11 & & General purpose registers (must be preserved) \\
R12 & IP & Intra-procedure-call scratch register \\
R13 & SP & Stack pointer \\
R14 & LR & Return address \\
R15 & PC & Program counter \\
\end{table-llX}
%
\begin{table-llX}{Condition Codes}
EQ & Equal & Z \\
NE & Not equal & !Z \\
CS/HS & Carry set, Unsigned higher or same & C \\
CC/LO & Carry clear, Unsigned lower & !C \\
MI & Minus, Negative & N \\
PL & Plus, Positive or zero & !N \\
VS & Overflow & V \\
VC & No overflow & !V \\
HI & Unsigned higher & C \& !Z \\
LS & Unsigned lower or same & !C | Z \\
GE & Signed greater than or equal & N $=$ V \\
LT & Signed less than & N $\ne$ V \\
GT & Signed greater than & !Z \& N $=$ V \\
LE & Signed less than or equal & Z | N $\ne$ V \\
AL & Always (default) & 1 \\
\end{table-llX}
%
\begin{table-lX}{DMB and DSB Options}
SY & Full system, Read and write \\
(SY)ST & Full system, Write only \\
ISH & Inner shareable, Read and write \\
ISHST & Inner shareable, Write only \\
NSH & Non-shareable, Read and write \\
NSHST & Non-shareable, Write only \\
OSH & Outer shareable, Read and write \\
OSHST & Outer sharable, Write only \\
\end{table-lX}
%
\begin{table-lX}{Notes for Instruction Set}
6,6k,6t,7 & Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv7 \\
A & Only available in ARM mode \\
D & Not available on ARM-M without DSP extension \\
H & Thumb16 instruction can use high registers \\
I & Can't be conditional \\
S & Thumb16 instruction must have S suffix unless in IT block \\
T & Only available in Thumb mode \\
\end{table-lX}
%
\begin{asmtable}{Thumb16 Bitwise and Move Instructions}
AND\{S\} & rx, ry & rx = rx \& ry & S \\
ASR\{S\} & rx, ry, \#j$^{ }_{5}$ & rx = ry $\asr$ j & S \\
ASR\{S\} & rx, ry & rx = rx $\asr$ ry & S \\
BIC\{S\} & rx, ry & rx = rx \& $\sim$ry & S \\
EOR\{S\} & rx, ry & rx = rx $\oplus$ ry & S \\
LSL\{S\} & rx, ry, \#i$^{ }_{5}$ & rx = ry $\lsl$ i & S \\
LSL\{S\} & rx, ry & rx = rx $\lsl$ ry & S \\
LSR\{S\} & rx, ry, \#j$^{ }_{5}$ & rx = ry $\lsr$ j & S \\
LSR\{S\} & rx, ry & rx = rx $\lsr$ ry & S \\
MOV & rx, ry & rx = ry & H \\
MOVS & rx, ry & rx = ry & \\
MOV\{S\} & rx, \#i$^{ }_{8}$ & rx = i$^{\emptyset}_{ }$ & S \\
MVN\{S\} & rx, ry & rx = $\sim$ry & S \\
ORR\{S\} & rx, ry & rx = rx | ry & S \\
REV & rx, ry & rx = ry$^{ }_{7:0}$:ry$^{ }_{15:8}$:ry$^{ }_{23:16}$:ry$^{ }_{31:24}$ & 6 \\
REV16 & rx, ry & rx = ry$^{ }_{23:16}$:ry$^{ }_{31:24}$:ry$^{ }_{7:0}$:ry$^{ }_{15:8}$ & 6 \\
REVSH & rx, ry & rx = ry$^{\pm}_{7:0}$:ry$^{ }_{15:8}$ & 6 \\
ROR\{S\} & rx, ry & rx = rx $\ror$ ry & S \\
SXTB & rx, ry & rx = ry$^{\pm}_{7:0}$ & \\
SXTH & rx, ry & rx = ry$^{\pm}_{15:0}$ & \\
TST & rx, ry & rx \& ry & \\
UXTB & rx, ry & rx = ry$^{\emptyset}_{7:0}$ & 6 \\
UXTH & rx, ry & rx = ry$^{\emptyset}_{15:0}$ & 6 \\
\end{asmtable}
%
\begin{asmtable}{Thumb16 Branch and Special Instructions}
B & rel$^{ }_{12}$ & PC = PC $+$ rel$^{\pm}_{11:1}$:0 & \\
Bcc & rel$^{ }_{9}$ & if(cc) PC = PC $+$ rel$^{\pm}_{8:1}$:0 & I \\
BKPT & \#i$^{ }_{8}$ & BreakPoint(i) & I \\
BL & rel$^{ }_{23}$ & LR=PC$^{ }_{31:1}$:1; PC$+$=rel$^{\pm}_{22:1}$:0 & \\
BLX & rel$^{ }_{23}$ & LR=PC$^{ }_{31:1}$:1; Set=0; PC$+$=rel$^{\pm}_{22:2}$:0$^{ }_{1:0}$ & \\
BLX & rx & LR=PC$^{ }_{31:1}$:1; Set=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0 & \\
BX & rx & Set=rx$^{ }_{0}$; PC = rx$^{ }_{31:1}$:0 & \\
CBNZ & rx, rel$^{ }_{7}$ & if(rx $\ne$ 0) PC $+$= rel$^{\emptyset}_{6:1}$:0 & I,6t \\
CBZ & rx, rel$^{ }_{7}$ & if(rx $\eq$ 0) PC $+$= rel$^{\emptyset}_{6:1}$:0 & I,6t \\
CPSI\{D,E\} & \{aif\} & \{a\}\{i\}\{f\} = (E ? 1 : 0) & 6 \\
IT\{t\{t\{t\}\}\} & cc & if(cc) NextInstruction & I,6t \\
NOP & & & 6k \\
SETEND & \{BE/LE\} & EndianState = \{BE/LE\} & I,6 \\
SEV & & SendEvent() & 7 \\
SVC & \#i$^{ }_{8}$ & CallSupervisor(i) & \\
UDF & \#i$^{ }_{8}$ & UndefinedException(i) & \\
WFE & & WaitForEvent() & 7 \\
WFI & & WaitForInterrupt() & 7 \\
YIELD & & HintYield() & 7 \\
\end{asmtable}
%
\begin{asmtable}{Thumb16 Arithmetic Instructions}
ADC\{S\} & rx, ry & rx = rx $+$ ry $+$ C & S \\
ADD\{S\} & rx, ry, \#i$^{ }_{3}$ & rx = ry $+$ i$^{\emptyset}_{ }$ & S \\
ADD\{S\} & rx, \#i$^{ }_{8}$ & rx = rx $+$ i$^{\emptyset}_{ }$ & S \\
ADD\{S\} & rx, ry, rz & rx = ry $+$ rz & S \\
ADD & rx, ry & rx = rx $+$ ry & H \\
ADD & rx, SP, \#i$^{ }_{8}$ & rx = SP $+$ i$^{\emptyset}_{ }$ & \\
ADD & SP, \#i$^{ }_{9}$ & SP = SP $+$ i$^{\emptyset}_{8:2}$:0$^{ }_{1:0}$ & \\
ADR & rx, rel$^{ }_{10}$ & rx = PC $+$ rel$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$ & \\
CMN & rx, ry & rx $+$ ry & \\
CMP & rx, \#i$^{ }_{8}$ & rx $-$ i$^{\emptyset}_{ }$ & \\
CMP & rx, ry & rx $-$ ry & H \\
MUL\{S\} & rx, ry & rx = rx $\umul$ ry & S \\
RSB\{S\} & rx, ry, \#0 & rx = 0 $-$ ry & S \\
SBC\{S\} & rx, ry & rx = rx $-$ (ry $+$ C) & S \\
SUB\{S\} & rx, ry, \#i$^{ }_{3}$ & rx = ry $-$ i$^{\emptyset}_{ }$ & S \\
SUB\{S\} & rx, \#i$^{ }_{8}$ & rx = rx $-$ i$^{\emptyset}_{ }$ & S \\
SUB\{S\} & rx, ry, rz & rx = ry $-$ rz & S \\
SUB & SP, \#i$^{ }_{9}$ & SP = SP $-$ i$^{\emptyset}_{8:2}$:0$^{ }_{1:0}$ & \\
\end{asmtable}
%
\begin{asmtable}{Thumb16 Load and Store Instructions}
LDM\textit{IA} & rx\{!\}, rlist & rlist = [rx]; if(!) rx $+$= 4$\times$cnt & \\
LDMIA & SP!, rlist & rlist = [SP]; SP $+$= 4$\times$cnt & \\
LDR & rx, [ry\{, \#i$^{ }_{7}$\}] & rx = [ry $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{1:0}$] & \\
LDR & rx, [SP\{, \#i$^{ }_{10}$\}] & rx = [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] & \\
LDR & rx, rel$^{ }_{10}$ & rx = [PC $+$ rel$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] & \\
LDR & rx, [ry, rz] & rx = [ry $+$ rz] & \\
LDRB & rx, [ry\{, \#i$^{ }_{5}$\}] & rx = [ry $+$ i$^{\emptyset}_{ }$]$^{\emptyset}_{8}$ & \\
LDRB & rx, [ry, rz] & rx = [ry $+$ rz]$^{\emptyset}_{8}$ & \\
LDRH & rx, [ry\{, \#i$^{ }_{6}$\}] & rx = [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{\emptyset}_{16}$ & \\
LDRH & rx, [ry, rz] & rx = [ry $+$ rz]$^{\emptyset}_{16}$ & \\
LDRSB & rx, [ry, rz] & rx = [ry $+$ rz]$^{\pm}_{8}$ & \\
LDRSH & rx, [ry, rz] & rx = [ry $+$ rz]$^{\pm}_{16}$ & \\
\textit{POP} & rlist & rlist = [SP]; SP $+$= 4$\times$cnt & \\
\textit{PUSH} & rlist & SP $-$= 4$\times$cnt; [SP] = rlist & \\
STM\textit{IA} & rx!, rlist & [rx] = rlist; rx $+$= 4$\times$cnt & \\
STMDB & SP!, rlist & SP $-$= 4$\times$cnt; [SP] = rlist & \\
STR & rx, [ry\{, \#i$^{ }_{7}$\}] & [ry $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{1:0}$] = rx & \\
STR & rx, [SP\{, \#i$^{ }_{10}$\}] & [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] = rx & \\
STR & rx, [ry, rz] & [ry $+$ rz] = rx & \\
STRB & rx, [ry\{, \#i$^{ }_{5}$\}] & [ry $+$ i$^{\emptyset}_{ }$]$^{ }_{8}$ = rx$^{ }_{7:0}$ & \\
STRB & rx, [ry, rz] & [ry $+$ rz]$^{ }_{8}$ = rx$^{ }_{7:0}$ & \\
STRH & rx, [ry\{, \#i$^{ }_{6}$\}] & [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{ }_{16}$ = rx$^{ }_{15:0}$ & \\
STRH & rx, [ry, rz] & [ry $+$ rz]$^{ }_{16}$ = rx$^{ }_{15:0}$ & \\
\end{asmtable}
%
\newpage
\begin{center}
{\Large\bfseries AArch32 Floating-point and \\* Advanced SIMD Extensions}
\end{center}
%
\begin{asmtable}{Load/Store Instructions}
VLDMDB & rx\{!\}, flist & flist = [rx $-$ f$\times$cnt]; if(!) rx$-$=f$\times$cnt & \\
VLDMIA & rx\{!\}, flist & flist = [rx]; if(!) rx $+$= f$\times$cnt & \\
VLDR & fx,[ry\{,\#$\pm$i$^{ }_{10}$\}] & fx = [ry $+$ i$^{\pm}_{9:2}$0$^{ }_{1:0}$]$^{ }_{f}$ & \\
VLDR & fx, $\pm$rel$^{ }_{10}$ & fx = [PC $+$ rel$^{\pm}_{9:2}$0$^{ }_{1:0}$]$^{ }_{f}$ & \\
VSTMDB & rx\{!\}, flist & [rx $-$ f$\times$cnt] = flist; if(!) rx$-$=f$\times$cnt & \\
VSTMIA & rx\{!\}, flist & flist = [rx]; if(!) rx $+$= f$\times$cnt & \\
VSTR & fx,[ry\{,\#$\pm$i$^{ }_{10}$\}] & [ry $+$ i$^{\pm}_{9:2}$0$^{ }_{1:0}$]$^{ }_{f}$ = fx & \\
\end{asmtable}
%
\begin{asmtable}{SIMD Load/Store Instructions}
VLD1.z & \{dx...\}, [addr] & ...:dx$^{'}_{ }$:dx = [addr]$^{ }_{64 \umul cnt}$ & \\ % z = 8,16,32,64
VLD1.z & \{dx[]...\}, [addr] & (...:dx$^{'}_{ }$:dx)$^{ }_{z*}$ = [addr]$^{ }_{z}$ & \\ % z = 8,16,32
VLD1.z & \{dx[i]\}, [addr] & dx$^{ }_{zi}$ = [addr]$^{ }_{z}$ & \\ % z = 8,16,32
VLD2.z & \{dx...\}, [addr] & ...:dx$^{ }_{z2}$:dx$^{'}_{z1}$:dx$^{ }_{z1}$:dx$^{'}_{z0}$:dx$^{ }_{z0}$=[addr]$^{ }_{64 \umul cnt}$ & \\ % z = 8,16,32
VLD2.z & \{dx[]...\}, [addr] & dx$^{'}_{z*}$:dx$^{ }_{z*}$ = [addr]$^{ }_{2z}$ & \\ % z = 8,16,32
VLD2.z & \{dx[i]...\}, [addr] & dx$^{'}_{zi}$:dx$^{ }_{zi}$ = [addr]$^{ }_{2z}$ & \\ % z = 8,16,32
VLD3.z & \{dx...\}, [addr] & ...:dx$^{'}_{z1}$:dx$^{ }_{z1}$:dx$^{''}_{z0}$:dx$^{'}_{z0}$:dx$^{ }_{z0}$=[addr]$^{ }_{64 \umul cnt}$ & \\ % z = 8,16,32
VLD3.z & \{dx[]...\}, [addr] & dx$^{''}_{z*}$:dx$^{'}_{z*}$:dx$^{ }_{z*}$ = [addr]$^{ }_{3z}$ & \\ % z = 8,16,32
VLD3.z & \{dx[i]...\}, [addr] & dx$^{''}_{zi}$:dx$^{'}_{zi}$:dx$^{ }_{zi}$ = [addr]$^{ }_{3z}$ & \\ % z = 8,16,32
VLD4.z & \{dx...\}, [addr] & ...:dx$^{ }_{z1}$:dx$^{'''}_{z0}$:dx$^{''}_{z0}$:dx$^{'}_{z0}$:dx$^{ }_{z0}$=[addr]$^{ }_{64 \umul cnt}$ & \\ % z = 8,16,32
VLD4.z & \{dx[]...\}, [addr] & dx$^{'''}_{z*}$:dx$^{''}_{z*}$:dx$^{'}_{z*}$:dx$^{ }_{z*}$ = [addr]$^{ }_{4z}$ & \\ % z = 8,16,32
VLD4.z & \{dx[i]...\}, [addr] & dx$^{'''}_{zi}$:dx$^{''}_{zi}$:dx$^{'}_{zi}$:dx$^{ }_{zi}$ = [addr]$^{ }_{4z}$ & \\ % z = 8,16,32
VST1.z & \{dx...\}, [addr] & [addr]$^{ }_{64 \umul cnt}$ = ...:dx$^{'}_{ }$:dx & \\ % z = 8,16,32,64
VST1.z & \{dx[i]\}, [addr] & [addr]$^{ }_{z}$ = dx$^{ }_{zi}$ & \\ % z = 8,16,32
VST2.z & \{dx...\}, [addr] & [addr]$^{ }_{64 \umul cnt}$ = ...:dx$^{'}_{z1}$:dx$^{ }_{z1}$:dx$^{'}_{z0}$:dx$^{ }_{z0}$ & \\ % z = 8,16,32
VST2.z & \{dx[i]...\}, [addr] & [addr]$^{ }_{2z}$ = dx$^{'}_{zi}$:dx$^{ }_{zi}$ & \\ % z = 8,16,32
VST3.z & \{dx...\}, [addr] & [addr]$^{ }_{64 \umul cnt}$=...:dx$^{'}_{z1}$:dx$^{ }_{z1}$:dx$^{''}_{z0}$:dx$^{'}_{z0}$:dx$^{ }_{z0}$ & \\ % z = 8,16,32
VST3.z & \{dx[i]...\}, [addr] & [addr]$^{ }_{3z}$ = dx$^{''}_{zi}$:dx$^{'}_{zi}$:dx$^{ }_{zi}$ & \\ % z = 8,16,32
VST4.z & \{dx...\}, [addr] & [addr]$^{ }_{64 \umul cnt}$=...:dx$^{ }_{z1}$:dx$^{'''}_{z0}$:dx$^{''}_{z0}$:dx$^{'}_{z0}$:dx$^{ }_{z0}$ & \\ % z = 8,16,32
VST4.z & \{dx[i]...\}, [addr] & [addr]$^{ }_{4z}$ = dx$^{'''}_{zi}$:dx$^{''}_{zi}$:dx$^{'}_{zi}$:dx$^{ }_{zi}$ & \\ % z = 8,16,32
\end{asmtable}
%
\begin{table-lX}{VLDx/VSTx Addressing Modes}
rz\{:align\} & addr = rz \\
rz\{:align\}! & addr = rz; rz $+$= (z$\lsr$3) $\times$ cnt \\
rz\{:align\}, rw & addr = rz; rz $+$= rw \\
\end{table-lX}
%
\begin{asmtable2}{SIMD Reciprocal Instructions}
VRECPE.F32 & mx, my & mx$^{ }_{32*}$=RecipEstimateFloat(my$^{ }_{32*}$) & \\
VRECPE.U32 & mx, my & mx$^{ }_{32*}$=RecipEstimateInt(my$^{ }_{32*}$) & \\
VRECPS.F32 & mx, my, mz & mx$^{ }_{32*}$=RecipStepFloat(my$^{ }_{32*}$, mz$^{ }_{32*}$) & \\
VRSQRTE.F32 & mx, my & mx$^{ }_{32*}$=SqrtEstimateFloat(my$^{ }_{32*}$) & \\
VRSQRTE.U32 & mx, my & mx$^{ }_{32*}$=SqrtEstimateInt(my$^{ }_{32*}$) & \\
VRSQRTS.F32 & mx, my, mz & mx$^{ }_{32*}$=SqrtStepFloat(my$^{ }_{32*}$, mz$^{ }_{32*}$) & \\
\end{asmtable2}
%
\begin{asmtable2}{Floating-point Instructions}
VABS.f & fx, fy & fx = $\lvert$fy$\rvert$ & \\
VADD.f & fx, fy, fz & fx = fy $+$ fz & \\
VCMP\{E\}.f & fd, \#0.0 & FPSCR\_nzcv = Compare(fx, 0) & \\
VCMP\{E\}.f & fx, fy & FPSCR\_nzcv = Compare(fx, fy) & \\
VCVT.F32.F64 & sx, dy & sx = Float2Float(dy) & \\
VCVT.F64.F32 & dx, sy & dx = Float2Float(sy) & \\
VCVT.sz.f & fx, fy, \#i$^{ }_{5}$ & fx = Float2Fixed(fy, i)$^{s}_{ }$ & V3 \\ % z = 16,32
VCVT.f.s32 & fx, sy & fx = Int2Float(sy$^{s}_{ }$) & \\
VCVT.f.sz & fx, fy, \#i$^{ }_{5}$ & fx = Fixed2Float(fy$^{s}_{ }$, i) & V3 \\ % z = 16,32
VCVT\{R\}.s32.f & sx, fy & sx = Float2Int(fy)$^{s}_{ }$ & \\
VCVTx.F16.F32 & sx, sy & sx$^{ }_{Hx}$ = Float2Float(sy) & V3 \\
VCVTx.F32.F16 & sx, sy & sx = Float2Float(sy$^{ }_{Hx}$) & V3 \\
VDIV.f & fx, fy, fz & fx = fy $\udiv$ dz & \\
VFMa.f & fx, fy, fz & fx $\pm$= fy $\umul$ fz & V4 \\
VFMNa.f & fx, fy, fz & fx = $-$fx $\pm$ fy $\umul$ fz & V4 \\
VMLa.f & fx, fy, fz & fx $\pm$= $\lfloor$fy $\umul$ fz$\rfloor$ & \\
VMOV.f & fx, \#$\pm$i$^{ }_{7}$ & fx = $\pm$i & V3 \\
VMOV.f & fx, fy & fx = fy & \\
VMUL.f & fx, fy, fz & fx = fy $\umul$ fz & \\
VNEG.f & fx, fy & fx = $-$fy & \\
VNMLa.f & fx, fy, fz & fx = $-$fx $\pm$ $-\lfloor$fy $\umul$ fz$\rfloor$ & \\
VNMUL.f & fx, fy, fz & fx = $-\lfloor$fy $\umul$ fz$\rfloor$ & \\
VSQRT.f & fx, fy & fx = SQRT(fy) & \\
VSUB.f & fx, fy, fz & fx = fy $-$ fz & \\
\end{asmtable2}
%
\begin{asmtable3}{Register Transfer Instructions}
VMOV\{.32\} & dx[i], ry & dx$^{ }_{32i}$ = ry & \\
VMOV\{.32\} & rx, dy[i] & rx = dy$^{ }_{32i}$ & \\
VMOV & sx, ry & sx = ry & \\
VMOV & rx, sy & rx = sy & \\
VMOV & sx, sx$^{'}_{ }$, ry, rz & sx$^{'}_{ }$:sx = rz:ry & \\
VMOV & rx, ry, sz, sz$^{'}_{ }$ & ry:rx = sz$^{'}_{ }$:sz & \\
VMOV & dx, ry, rz & dx = rz:ry & \\
VMOV & rx, ry, dz & ry:rx = dz & \\
VMRS & rx, fpreg & rx = fpreg & \\
VMRS & APSR\_nzcv,FPSCR & APSR\_nzcv = FPSCR\_nzcv & \\
VMSR & fpreg, rx & fpreg = rx & \\
\end{asmtable3}
%
\begin{asmtable3}{SIMD Register Transfer Instructions}
VDUP.z & mx, ry & mx$^{ }_{z*}$ = ry$^{ }_{z}$ & \\ % z = 8,16,32
VDUP.z & mx, dy[i] & mx$^{ }_{z*}$ = dy$^{ }_{zi}$ & \\ % z = 8,16,32
VMOV.z & dx[i], ry & dx$^{ }_{zi}$ = ry$^{ }_{z}$ & \\ % z = 8,16
VMOV.sz & rx, dy[i] & rx = dy$^{s}_{zi}$ & \\ % z = 8,16
VMOV & mx, my & mx = my & \\
\end{asmtable3}
%
\begin{table-lX}{Floating-point System Registers}
FPEXC & Floating-point Exception Control \\
FPSCR & Floating-point Status and Control \\
FPSID & Floating-point System ID \\
MVFR\{0..1\} & Media and VFP Feature \{0..1\} \\
\end{table-lX}
%
\begin{table-llX}{Floating-point Status and Control Register (FPSCR)}
IOC & 0x00000001 & Invalid Operation cumulative exception \\
DZC & 0x00000002 & Division by Zero cumulative exception \\
OFC & 0x00000004 & Overflow cumulative exception \\
UFC & 0x00000008 & Underflow cumulative exception \\
IXC & 0x00000010 & Inexact cumulative exception \\
IDC & 0x00000080 & Input Denormal cumulative exception \\
IOE & 0x00000100 & Invalid Operation exception trap enable \\
DZE & 0x00000200 & Division by Zero exception trap enable \\
OFE & 0x00000400 & Overflow exception trap enable \\
UFE & 0x00000800 & Underflow exception trap enable \\
IXE & 0x00001000 & Inexact exception trap enable \\
IDE & 0x00008000 & Input Denormal exception trap enable \\
%Len & 0x00070000 & VFP vector length \\ % Deprecated
%Stride & 0x00300000 & VFP vector stride \\ % Deprecated
RMode & 0x00c00000 & Rounding mode (RN,RP,RM,RZ) \\
FZ & 0x01000000 & Flush-to-zero mode \\
DN & 0x02000000 & Default NaN mode \\
AHP & 0x04000000 & Alternative half-precision \\
QC & 0x08000000 & Cumulative saturation \\
V & 0x10000000 & Overflow condition flag \\
C & 0x20000000 & Carry condition flag \\
Z & 0x40000000 & Zero condition flag \\
N & 0x80000000 & Negative condition flag \\
\end{table-llX}
%
\begin{table-lX}{Floating-point and SIMD Keys}
s & Operation signess (S or U) \\
z & Data size (8, 16, or 32) \\
f & Floating-point size (F32 or F64) \\
sx, dx, qx & Singleword/doubleword/quadword register \\
fx, fy, fz & Floating-point register (sx or dx depending on data size) \\
mx, my, mz & SIMD register (dx or qx) \\
cm & SIMD comparison operator (GE, GT, LE, or LT) \\
$\lfloor$x$\rfloor$ & Value is rounded \\
x $\lsl\lsr$ y & (y $\ult$ 0) ? (x $\lsr$ $-$y) : (x $\lsl$ y) \\
$\max$ $\min$ & Maximum/minimum value \\
\end{table-lX}
%
\begin{table-lX}{Notes for Floating-point and SIMD Instructions}
V3,V4 & Introduced in VFPv3, VFPv4 \\
SH,S2 & Introduced in SIMD with half-precision floats, SIMDv2 \\
F & Instruction with data type F32 also exists \\
\end{table-lX}
%
\begin{asmtable2}{SIMD Addition and Subtraction Instructions}
VABA.sz & mx, my, mz & mx$^{ }_{z*}$ $\pm$= $\lvert$my$^{ }_{z*}$ $-$ mz$^{ }_{z*}$$\rvert$ & \\ % z = 8,16,32
VABAL.sz & qx, dy, dz & qx$^{ }_{2z*}$ $\pm$= $\lvert$dy$^{ }_{z*}$ $-$ dz$^{ }_{z*}$$\rvert$ & \\ % z = 8,16,32
VABD.sz & mx, my, mz & mx$^{ }_{z*}$ = $\lvert$my$^{ }_{z*}$ $-$ mz$^{ }_{z*}$$\rvert$ & F \\ % z = 8,16,32
VABDL.sz & qx, dy, dz & qx$^{ }_{2z*}$ = $\lvert$dy$^{ }_{z*}$ $-$ dz$^{ }_{z*}$$\rvert$ & \\ % z = 8,16,32
VABS.Sz & mx, my & mx$^{ }_{z*}$ = $\lvert$my$^{ }_{z*}$$\rvert$ & F \\ % z = 8,16,32
VADD.Iz & mx, my, mz & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $+$ mz$^{ }_{z*}$ & F \\ % z = 8,16,32,64
VADDHN.Iz & dx, qy, qz & dx$^{ }_{0\text{.}5z*}$ = (qy$^{ }_{z*}$ $+$ qz$^{ }_{z*}$)$\lsr$z & \\ % z = 16,32,64
VADDL.sz & qx, dy, dz & qx$^{ }_{z*}$ = dy$^{s}_{z*}$ $+$ dz$^{s}_{z*}$ & \\ % z = 8,16,32
VADDW.sz & qx, qy, dz & qx$^{ }_{z*}$ = qy$^{ }_{z*}$ $+$ dz$^{s}_{z*}$ & \\ % z = 8,16,32
VHADD.sz & mx, my, mz & mx$^{ }_{z*}$ = (my$^{s}_{z*}$ $+$ mz$^{s}_{z*}$) $\lsr$ 1 & \\ % z = 8,16,32
VHSUB.sz & mx, my, mz & mx$^{ }_{z*}$ = (my$^{s}_{z*}$ $-$ mz$^{s}_{z*}$) $\lsr$ 1 & \\ % z = 8,16,32
VNEG.Sz & mx, my & mx$^{ }_{z*}$ = 0 $-$ my$^{ }_{z*}$ & F \\ % z = 8,16,32
VPADAL.sz & mx, my & mx$^{ }_{2z*}$ $+$= my$^{ }_{2z*[2z-1:z]}$ $+$ my$^{ }_{2z*[z-1:0]}$ & \\ % z = 8,16,32
VPADD.Iz & dx, dy, dz & dx$^{ }_{z*}$=(dz:dy)$^{ }_{2z*[2z-1:z]}$$+$(dz:dy)$^{ }_{2z*[z-1:0]}$ & F \\ % z = 8,16,32
VPADDL.sz & mx, my & mx$^{ }_{2z*}$ = my$^{ }_{2z*[2z-1:z]}$ $+$ my$^{ }_{2z*[z-1:0]}$ & \\ % z = 8,16,32
VRADDHN.Iz & dx, qy, qz & dx$^{ }_{0\text{.}5z*}$ = $\lfloor$qy$^{ }_{z*}$ $+$ qz$^{ }_{z*}$$\rfloor$ $\lsr$ z & \\ % z = 16,32,64
VRHADD.sz & mx, my, mz & mx$^{ }_{z*}$ = $\lfloor$(my$^{s}_{z*}$ $+$ mz$^{s}_{z*}$) $\lsr$ 1$\rfloor$ & \\ % z = 8,16,32
VRSUBHN.Iz & dx, qy, qz & dx$^{ }_{0\text{.}5z*}$ = $\lfloor$qy$^{ }_{z*}$ $-$ qz$^{ }_{z*}$$\rfloor$ $\lsr$ z & \\ % z = 16,32,64
VQABS.Sz & mx, my & mx$^{ }_{z*}$ = SATS($\lvert$my$^{ }_{z*}$$\rvert$, z) & \\ % z = 8,16,32
VQADD.sz & mx, my, mz & mx$^{ }_{z*}$ = SATs(my$^{ }_{z*}$ $+$ mz$^{ }_{z*}$, z) & \\ % z = 8,16,32,64
VQNEG.Sz & mx, my & mx$^{ }_{z*}$ = SATS(0 - my$^{ }_{z*}$, z) & \\ % z = 8,16,32
VQSUB.sz & mx, my, mz & mx$^{ }_{z*}$ = SATs(my$^{ }_{z*}$ $-$ mz$^{ }_{z*}$, z) & \\ % z = 8,16,32,64
VSUB.Iz & mx, my, mz & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $-$ mz$^{ }_{z*}$ & F \\ % z = 8,16,32,64
VSUBHN.Iz & dx, qy, qz & dx$^{ }_{0\text{.}5z*}$ = (qy$^{ }_{z*}$ $-$ qz$^{ }_{z*}$) $\lsr$ z & \\ % z = 16,32,64
VSUBL.sz & qx, dy, dz & qx$^{ }_{z*}$ = dy$^{s}_{z*}$ $-$ dz$^{s}_{z*}$ & \\ % z = 8,16,32
VSUBW.sz & qx, qy, dz & qx$^{ }_{z*}$ = qy$^{ }_{z*}$ $-$ dz$^{s}_{z*}$ & \\ % z = 8,16,32
\end{asmtable2}
%
\begin{asmtable2}{SIMD Data Convertion Instructions}
VCVT.F16.F32 & dx, qy & dx$^{ }_{16*}$ = Float2Float(qy$^{ }_{32*}$) & SH \\
VCVT.F32.F16 & qx, dy & qx$^{ }_{32*}$ = Float2Float(dy$^{ }_{16*}$) & SH \\
VCVT.F32.s32 & mx, my & mx$^{ }_{32*}$ = Int2Float(my$^{s}_{32*}$) & \\
VCVT.F32.s32 & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{32*}$ = Fixed2Float(my$^{s}_{32*}$, i) & \\
VCVT.s32.F32 & mx, my & mx$^{ }_{32*}$ = Float2Int(my)$^{s}_{32*}$ & \\
VCVT.s32.F32 & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{32*}$ = Float2Fixed(my, i)$^{s}_{32*}$ & \\
VMOVL.sz & qx, dy & qx$^{ }_{2z*}$ = dy$^{\pm}_{z*}$ & \\ % z = 8,16,32
VMOVN.Iz & dx, qy & dx$^{ }_{0\text{.}5z*}$ = qy$^{ }_{z*[0\text{.}5z-1:0]}$ & \\ % z = 16,32,64
VQMOVN.sz & dx, qy & dx$^{ }_{0\text{.}5z*}$ = SATs(qy$^{ }_{z*}$, 0.5z) & \\ % z = 16,32,64
VQMOVUN.Sz & dx, qy & dx$^{ }_{0\text{.}5z*}$ = SATU(qy$^{ }_{z*}$, 0.5z) & \\ % z = 16,32,64
VUZP.z & mx, my & my = ...:my$^{ }_{z3}$:my$^{ }_{z1}$:...:mx$^{ }_{z3}$:mx$^{ }_{z1}$ \newline mx = ...:my$^{ }_{z2}$:my$^{ }_{z0}$:...:mx$^{ }_{z2}$:mx$^{ }_{z0}$ & \\ %z!=64
VZIP.z & mx, my & my:mx = ...:my$^{ }_{z1}$:mx$^{ }_{z1}$:my$^{ }_{z0}$:mx$^{ }_{z0}$ & \\ % z = 8,16,32
\end{asmtable2}
%
\begin{asmtable}{SIMD Bitwise Instructions}
VAND & mx, my, mz & mx = my \& mz & \\
\textit{VAND.Iz} & \{mx, \}mx, \#i & mx$^{ }_{z*}$ \&= i & \\ % z = 8,16,32,64
VBIC & mx, my, mz & mx = my \& $\sim$mz & \\
VBIC.Iz & \{mx, \}mx, \#i & mx$^{ }_{z*}$ \&= $\sim$i & \\ % z = 16,32 (8,64 as instruction alias)
VEOR & mx, my, mz & mx = my $\oplus$ mz & \\
VBIF & mx, my, mz & if(mz$^{ }_{1*}$ $=$ 0) mx$^{ }_{1*}$ = my$^{ }_{1*}$ & \\
VBIT & mx, my, mz & if(mz$^{ }_{1*}$ $=$ 1) mx$^{ }_{1*}$ = my$^{ }_{1*}$ & \\
VBSL & mx, my, mz & mx$^{ }_{1*}$ = mx$^{ }_{1*}$ $=$ 1 ? my$^{ }_{1*}$ : mz$^{ }_{1*}$ & \\
VEXT.z & mx,my,mz,\#i$^{ }_{4}$ & mx$^{ }_{z*}$ = mz$^{ }_{z*[i-1:0]}$:my$^{ }_{z*[z-1:z-i+1]}$ & \\ % z = 8,16,32,64
VMOV.Iz & mx, \#i & mx$^{ }_{z*}$ = i & F \\ % z = 8,16,32,64
VMVN.Iz & mx, \#i & mx$^{ }_{z*}$ = $\sim$i & \\ % z = 16,32
VMVN & mx, my & mx = $\sim$my & \\
VORR.Iz & \{mx, \}mx, \#i & mx$^{ }_{z*}$ |= i & \\ % z = 16,32 (8,64 as instruction alias)
VORR & mx, my, mz & mx = my | mz & \\
VORN & mx, my, mz & mx = my | $\sim$mz & \\
\textit{VORN.Iz} & \{mx, \}mx, \#i & mx$^{ }_{z*}$ |= $\sim$i & \\ % z = 8,16,32,64
\end{asmtable}
%
\begin{asmtable}{SIMD Comparision Instructions}
VACcm.F32 & mx, my, mz & mx$^{ }_{32*}$=$\lvert$my$^{ }_{32*}$$\rvert$ cm $\lvert$mz$^{ }_{32*}$$\rvert$ ?1$^{ }_{32}$:0$^{ }_{32}$ & \\
VCEQ.Iz & mx, my, mz & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\eq$ mz$^{ }_{z*}$ ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & F \\ % z = 8,16,32
VCEQ.Iz & mx, my, \#0 & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\eq$ 0 ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & F \\ % z = 8,16,32
VCcm.sz & mx, my, mz & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $cm^{s}_{ }$ mz$^{ }_{z*}$ s 1$^{ }_{z}$ : 0$^{ }_{z}$ & F \\ % z = 8,16,32
VCcm.Sz & mx, my, \#0 & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\bar{cm}$ 0 ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & F \\ % z = 8,16,32
VMAX.sz & mx, my, mz & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\max^{s}_{ }$ mz$^{ }_{z*}$ & F \\ % z = 8,16,32
VMIN.sz & mx, my, mz & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\min^{s}_{ }$ mz$^{ }_{z*}$ & F \\ % z = 8,16,32
VPMAX.sz & dx, dy, dz & dx$^{ }_{z*}$=(dz:dy)$^{ }_{2z*[2z-1:z]}$$\max^{s}_{ }$dz:dy$^{ }_{2z*[z-1:0]}$ & F \\ % z = 8,16,32
VPMIN.sz & dx, dy, dz & dx$^{ }_{z*}$=(dz:dy)$^{ }_{2z*[2z-1:z]}$$\min^{s}_{ }$dz:dy$^{ }_{2z*[z-1:0]}$ & F \\ % z = 8,16,32
VTST.z & mx, my, mz & mx$^{ }_{z*}$ = (my$^{ }_{z*}$\&mz$^{ }_{z*}$ $\ne$ 0) ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & \\ % z = 8,16,32
\end{asmtable}
%
\begin{asmtable}{SIMD Misc Processing Instructions}
VCLS.Sz & mx, my & mx$^{ }_{z*}$ = CountLeadingSignBits(my$^{ }_{z*}$) & \\ % z = 8,16,32
VCLZ.Iz & mx, my & mx$^{ }_{z*}$ = CountLeadingZeros(my$^{ }_{z*}$) & \\ % z = 8,16,32
VCNT.8 & mx, my & mx$^{ }_{8*}$ = CountOneBits(my$^{ }_{8*}$) & \\
VREV16.8 & mx, my & mx$^{ }_{16*}$ = my$^{ }_{16*[7:0]}$:my$^{ }_{16*[15:8]}$ & \\
VREV32.8 & mx, my & mx$^{ }_{32*}$ = my$^{ }_{32*[7:0]}$:..:my$^{ }_{32*[31:24]}$ & \\
VREV32.16 & mx, my & mx$^{ }_{32*}$ = my$^{ }_{32*[15:0]}$:my$^{ }_{32*[31:16]}$ & \\
VREV64.8 & mx, my & mx$^{ }_{64*}$ = my$^{ }_{64*[15:0]}$:...:my$^{ }_{64*[63:48]}$ & \\
VREV64.16 & mx, my & mx$^{ }_{64*}$ = my$^{ }_{64*[7:0]}$:...:my$^{ }_{64*[63:56]}$ & \\
VREV64.32 & mx, my & mx$^{ }_{64*}$ = my$^{ }_{64*[31:0]}$:my$^{ }_{64*[63:32]}$ & \\
VSWP & mx, my & my:mx = mx:my & \\
VTBL.8 & dx, {dy...}, dz & dx$^{ }_{8*}$ = dz$^{ }_{8*}$ $\ult$ cnt$\umul$8 ? (dy:...)$^{ }_{8dz^{ }_{8*}}$ : 0 & \\
VTBX.8 & dx, {dy...}, dz & if(dz$^{ }_{8*}$ $\ult$ cnt$\umul$8) dx$^{ }_{8*}$ = (dy:...)$^{ }_{8dz^{ }_{8*}}$ & \\
VTRN.z & mx, my & if(even) my$^{ }_{z*}$:mx$^{ }_{z*+1}$ = mx$^{ }_{z*+1}$:my$^{ }_{z*}$ & \\ % z = 8,16,32
\end{asmtable}
%
\begin{asmtable2}{SIMD Shift Instructions}
VQRSHL.sz & mx, my, mz & mx$^{ }_{z*}$ = SATs($\lfloor$my$^{ }_{z*}$ $\lsl\lsr^{s}_{ }$ mz$^{ }_{z*}\rfloor$, z) & \\ % z = 8,16,32,64
VQRSHRN.sz & dx, qy, \#i$^{ }_{5}$ & dx$^{ }_{0\text{.}5z*}$ = SATs($\lfloor$qy$^{ }_{z*}$ $\lsr^{s}_{ }$ i$\rfloor$, z) & \\ % z = 16,32,64
VQRSHRUN.Sz & dx, qy, \#i$^{ }_{5}$ & dx$^{ }_{0\text{.}5z*}$ = SATU($\lfloor$qy$^{\pm}_{z*}$ $\asr$ i$\rfloor$, z) & \\ % z = 16,32,64
VQSHL.sz & mx, my, mz & mx$^{ }_{z*}$ = SATs(my$^{ }_{z*}$ $\lsl\lsr^{s}_{ }$ mz$^{ }_{z*}$, z) & \\ % z = 8,16,32,64
VQSHL.sz & mx, my, \#i$^{ }_{5}$ & mx$^{ }_{z*}$ = SATs(my$^{ }_{z*}$ $\lsl$ i, z) & \\ % z = 8,16,32,64
VQSHLU.Sz & mx, my, \#i$^{ }_{5}$ & mx$^{ }_{z*}$ = SATU(my$^{ }_{z*}$ $\lsl\asr$ i, z) & \\ % z = 8,16,32,64
VQSHRN.sz & dx, qy, \#i$^{ }_{5}$ & dx$^{ }_{0\text{.}5z*}$ = SATs(qy$^{ }_{z*}$ $\lsr^{s}_{ }$ i, z) & \\ % z = 16,32,64
VQSHRUN.Sz & dx, qy, \#i$^{ }_{5}$ & dx$^{ }_{0\text{.}5z*}$ = SATU(qy$^{\pm}_{z*}$ $\asr$ i, z) & \\ % z = 16,32,64
VRSHL.sz & mx, my, mz & mx$^{ }_{z*}$ = $\lfloor$my$^{ }_{z*}$ $\lsl\lsr^{s}_{ }$ mz$^{ }_{z*}\rfloor$ & \\ % z = 8,16,32,64
VRSHR.sz & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{z*}$ = $\lfloor$my$^{ }_{z*}$ $\lsr^{s}_{ }$ i$\rfloor$ & \\ % z = 8,16,32,64
VRSRA.sz & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{z*}$ $+$= $\lfloor$my$^{ }_{z*}$ $\lsr^{s}_{ }$ i$\rfloor$ & \\ % z = 8,16,32,64
VRSHRN.Iz & dx, qy, \#i$^{ }_{5}$ & dx$^{ }_{0\text{.}5z*}$ = $\lfloor$qy$^{ }_{z*}$ $\lsr$ i$\rfloor$ & \\ % z = 16,32,64
VSHL.Iz & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\lsl$ i & \\ % z = 8,16,32,64
VSHL.sz & mx, my, mz & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\lsl\lsr^{s}_{ }$ mz$^{ }_{z*}$ & \\ % z = 8,16,32,64
VSHLL.sz & qx, dy, \#i$^{ }_{5}$ & qx$^{ }_{0\text{.}5z*}$ = dy$^{ }_{z*}$ $\lsl$ i & \\ % z = 8,16,32
VSHLL.Iz & qx, dy, \#z & qx$^{ }_{2z*}$ = dy$^{ }_{z*}$ $\lsl$ z & \\ % z = 8,16,32
VSHR.sz & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\lsr^{s}_{ }$ i & \\ % z = 8,16,32,64
VSHRN.Iz & dx, qy, \#i$^{ }_{5}$ & dx$^{ }_{0\text{.}5z*}$ = qy$^{ }_{z*}$ $\lsr$ i & \\ % z = 16,32,64
VSLI.z & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{z*[z-1:i]}$ = my$^{ }_{z*[z-i-1:0]}$ & \\ % z = 8,16,32,64
VSRA.sz & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{z*}$ $+$= my$^{ }_{z*}$ $\lsr^{s}_{ }$ i & \\ % z = 8,16,32,64
VSRI.z & mx, my, \#i$^{ }_{6}$ & mx$^{ }_{z*[z-i-1:0]}$ = my$^{ }_{z*[z-1:i]}$ & \\ % z = 8,16,32,64
\end{asmtable2}
%
\begin{asmtable2}{SIMD Multiply Instructions}
VFMa.F32 & mx, my, mz & mx$^{ }_{z*}$ $\pm$= my$^{ }_{z*}$ $\umul$ mz$^{ }_{z*}$ & S2 \\
VMLa.Iz & mx, my, mz & mx$^{ }_{z*}$ $\pm$= my$^{ }_{z*}$ $\umul$ mz$^{ }_{z*}$ & F \\ % z = 8,16,32
VMLa.Iz & mx, my, dz[i] & mx$^{ }_{z*}$ $\pm$= my$^{ }_{z*}$ $\umul$ dz$^{ }_{zi}$ & F \\ % z = 16,32
VMLaL.sz & qx, dy, dz & qx$^{ }_{2z*}$ $\pm$= dy$^{ }_{z*}$ $\umul^{s}_{ }$ dz$^{ }_{z*}$ & \\ % z = 8,16,32
VMLaL.sz & qx, dy, dz[i] & qx$^{ }_{2z*}$ $\pm$= dy$^{ }_{z*}$ $\umul^{s}_{ }$ dz$^{ }_{zi}$ & \\ % z = 16,32
VMUL.Iz & mx, my, mz & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\umul$ mz$^{ }_{z*}$ & F \\ % z = 8,16,32
VMUL.Iz & mx, my, dz[i] & mx$^{ }_{z*}$ = my$^{ }_{z*}$ $\umul$ dz$^{ }_{zi}$ & F \\ % z = 16,32
VMUL.P8 & mx, my, mz & mx$^{ }_{8*}$ = my$^{ }_{8*}$ $\ast$ mz$^{ }_{8*}$ & \\
VMULL.P8 & qx, dy, dz & qx$^{ }_{16*}$ = dy$^{ }_{8*}$ $\ast$ dz$^{ }_{8*}$ & \\
VMULL.sz & qx, dy, dz & qx$^{ }_{2z*}$ = dy$^{ }_{z*}$ $\umul^{s}_{ }$ dz$^{ }_{z*}$ & \\ % z = 8,16,32
VMULL.sz & qx, dy, dz[i] & qx$^{ }_{2z*}$ = dy$^{ }_{z*}$ $\umul^{s}_{ }$ dz$^{ }_{zi}$ & \\ % z = 16,32
VQDMLaL.Sz & qx, dy, dz & qx$^{ }_{2z*}$ $\pm$= SATS(2$\smul$dy$^{ }_{z*}$$\smul$dz$^{ }_{z*}$, z) & \\ % z = 16,32
VQDMLaL.Sz & qx, dy, dz[i] & qx$^{ }_{2z*}$ $\pm$= SATS(2$\smul$dy$^{ }_{z*}$$\smul$dz$^{ }_{zi}$, z) & \\ % z = 16,32
VQDMULH.Sz & mx, my, mz & mx$^{ }_{z*}$=SATS(2$\smul$my$^{ }_{z*}$$\smul$mz$^{ }_{z*}$, 2z)$\lsr$z & \\ % z = 16,32
VQDMULH.Sz & mx, my, dz[i] & mx$^{ }_{z*}$=SATS(2$\smul$my$^{ }_{z*}$$\smul$dz$^{ }_{zi}$, 2z)$\lsr$z & \\ % z = 16,32
VQDMULL.Sz & qx, dy, dz & qx$^{ }_{2z*}$=SATS(2$\smul$dy$^{ }_{z*}$$\smul$dz$^{ }_{z*}$, 2z) & \\ % z = 16,32
VQDMULL.Sz & qx, dy, dz[i] & qx$^{ }_{2z*}$=SATS(2$\smul$dy$^{ }_{z*}$$\smul$dz$^{ }_{zi}$, 2z) & \\ % z = 16,32
VQRDMULH.Sz & mx, my, mz & mx$^{ }_{z*}$=SATS($\lfloor$2$\smul$my$^{ }_{z*}$$\smul$mz$^{ }_{z*}$$\rfloor$,2z)$\lsr$z & \\ % z = 16,32
VQRDMULH.Sz & mx, my, dz[i] & mx$^{ }_{z*}$=SATS($\lfloor$2$\smul$my$^{ }_{z*}$$\smul$dz$^{ }_{zi}$$\rfloor$,2z)$\lsr$z & \\ % z = 16,32
\end{asmtable2}
%
\newpage
\begin{center}
{\Large\bfseries ARMv7-A \& ARMv7-R System}
\end{center}
%
\begin{table-llXr}{Current Program Status Register (CPSR)}
M & 0x0000001f & Processor Operating Mode & \\
T & 0x00000020 & Instruction set (JT: 00=ARM, 01=Thumb) & \\
F & 0x00000040 & FIQ exception masked & \\
I & 0x00000080 & IRQ exception masked & \\
A & 0x00000100 & Asynchronous abort masked & 6 \\
E & 0x00000200 & Big-endian operation & 6 \\
IT & 0x0600fc00 & IT state bits & 6t\\
GE\{3..0\} & 0x000f0000 & SIMD Greater than or equal to & 6 \\
J & 0x01000000 & Instr set (JT: 10=Jazelle, 11=ThumbEE) & 6 \\
Q & 0x08000000 & Cumulative saturation bit & \\
V & 0x10000000 & Overflow condition flag & \\
C & 0x20000000 & Carry condition flag & \\
Z & 0x40000000 & Zero condition flag & \\
N & 0x80000000 & Negative condition flag & \\
\end{table-llXr}
%
\begin{table-llXr}{Processor Operating Modes}
usr & 0x10 & User & \\
fiq & 0x11 & FIQ & \\
irq & 0x12 & IRQ & \\
svc & 0x13 & Supervisor & \\
mon & 0x16 & Monitor (Secure only) & S\\
abt & 0x17 & Abort & \\
hyp & 0x1a & Hypervisor (Non-secure only) & V \\
und & 0x1b & Undefined & \\
sys & 0x1f & System & \\
\end{table-llXr}
%
\begin{table-lX}{Vectors}
0x00 & Reset \\
0x04 & Undefined instruction \\
0x08 & Supervisor Call / Secure Monitor Call / Hypervisor Call \\
0x0c & Prefetch abort \\
0x10 & Data abort \\
0x14 & Hyp trap \\
0x18 & IRQ interrupt \\
0x1c & FIQ interrupt \\
\end{table-lX}
%
\begin{table-lX}{Notes for System Registers and Tables}
6,6k,6t,7 & Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv7 \\
%\sout{7} & Removed in ARMv7 \\
A & Only present on ARM-A \\
B & Banked between secure and non-secure usage \\
R & Only present on ARM-R \\
S & Only present with security extensions (Implies 6k,A) \\
V & Only present with virtualization extensions (Implies 7,A) \\
\end{table-lX}
%
\begin{table-llXr}{System Control Register (SCTLR)}
M & 0x00000001 & MMU enabled & B \\
A & 0x00000002 & Alignment check enabled & B \\
C & 0x00000004 & Data and unified caches enabled & B \\
%W & 0x00000008 & Write buffer enabled & \sout{7} \\
CP15BEN & 0x00000020 & CP15 barrier enable & 7,B \\
%B & 0x00000080 & Legacy Big endian BE-32 format & \sout{7} \\
%S & 0x00000100 & System protection & \sout{7} \\
%R & 0x00000200 & ROM protection & \sout{7} \\
SW & 0x00000400 & Enable SWP and SWPB instructions & 6,B \\
Z & 0x00000800 & Program flow prediction enabled & B \\
I & 0x00001000 & Instruction cache enabled & B \\
V & 0x00002000 & High exception vectors & B \\
RR & 0x00004000 & Round Robin select (Non-Secure RO) & \\
%L4 & 0x00008000 & Inhibit thumb interworking & \sout{7} \\
HA & 0x00020000 & Hardware access flag enable & B,S \\
BR & 0x00020000 & Background region enable & 7,R \\
WXN & 0x00080000 & Write force to XN & V \\
DZ & 0x00080000 & Divide by zero causes undefined instruction & 7,R \\
UWXN & 0x00100000 & Unprivileged write forced to XN for PL1 & V \\
FI & 0x00200000 & Fast Interrupts (Non-Secure RO) & 6 \\
%U & 0x00400000 & Unaligned access support & 6,\sout{7} \\
%XP & 0x00800000 & Select virtual memory support model & 6,\sout{7} \\
VE & 0x01000000 & Interrupt Vectors Enable & 6,B \\
EE & 0x02000000 & Exception Endianess & 6,B \\
%L2 & 0x04000000 & Level 2 cache support & 6,\sout{7} \\
NMFI & 0x08000000 & Non-maskable FIQ support (RO) & 6 \\
TRE & 0x10000000 & TEX remap functionality enabled & B,S \\
AFE & 0x20000000 & Access flag enable & B,S \\
TE & 0x40000000 & Thumb exception enable & 6t,B \\
IE & 0x80000000 & Big-endian byte order in instructions & 7,R \\
\end{table-llXr}
%
\begin{table-llX}{Coprocessor Access Control Register (CPACR)}
CP\{0..13\} & 3$\lsl$(2$\umul$\{0..13\}) & CP\{0..13\} access (00=denied, 01=privileged mode only, 11=privileged or user mode) \\
TRCDIS & 0x10000000 & Disable CP14 access to trace registers \\
D32DIS & 0x40000000 & Disable use of D16-D31 registers \\
ASEDIS & 0x80000000 & Disable advanced SIMD functionality \\
\end{table-llX}
%
\begin{table-llXr}{CP15 System Control Registers}
SCTLR & c1,0,c0,0 & System Control Register & \\
ACTLR & c1,0,c0,1 & Auxiliary Control Register & 6,B \\
CPACR & c1,0,c0,2 & Coprocessor Access Control Register & 6 \\
SCR & c1,0,c1,0 & Secure Configuration (Secure only) & S \\
SDER & c1,0,c1,1 & Secure Debug Enable (Secure only) & S \\
NSACR & c1,0,c1,2 & Non-Secure Access Control (Non-Secure RO) & S \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 Security Extension Registers (ARM-A Only)}
VBAR & c12,0,c0,0 & Vector Base Register & B \\
MVBAR & c12,0,c0,1 & Monitor Vector Base Address (Secure only) & \\
ISR & c12,0,c1,0 & Interrupt Status Register (RO) & \\
\end{table-llXr}
%
\begin{table-llXr}{Secure Configuration Register (SCR)}
NS & 0x001 & System state is non-secure unless in Monitor mode & \\
IRQ & 0x002 & IRQs taken to Monitor mode & \\
FIQ & 0x004 & FIQs taken to Monitor mode & \\
EA & 0x008 & External aborts taken to Monitor mode & \\
FW & 0x010 & CPSR.F writeable in non-secure state & \\
AW & 0x020 & CPSR.A writeable in non-secure state & \\
nET & 0x040 & Disable early termination & \\
SCD & 0x080 & Secure monitor call disable & V \\
HCE & 0x100 & Hyp Call enable & V \\
SIF & 0x200 & Secure instruction fetch & V \\
\end{table-llXr}
%
\begin{table-llX}{Non-Secure Access Control Register (NSACR)}
CP\{0..13\} & 1 $\lsl$ \{0..13\} & CP\{0..13\} can be accessed in non-secure state \\
NSD32DIS & 0x00004000 & CPACR.D32DIS is fixed 1 in non-secure state \\
NSASEDIS & 0x00008000 & CPACR.ASEDIS is fixed 1 in non-secure state \\
RFR & 0x00080000 & Reserve FIQ mode for non-secure \\
NSTRCDIS & 0x00100000 & Disable non-secure access to CP14 trace regs \\
\end{table-llX}
%
\begin{table-llXr}{CP15 Memory System Fault Registers}
DFSR & c5,0,c0,0 & Data Fault Status Register & B \\
IFSR & c5,0,c0,1 & Instruction Fault Status Register & 6,B \\
ADFSR & c5,0,c1,0 & Auxiliary DFSR & 7,B \\
AIFSR & c5,0,c1,1 & Auxiliary IFSR & 7,B \\
DFAR & c6,0,c0,0 & Data Fault Address Register & B \\
IFAR & c6,0,c0,2 & Instruction Fault Address Register & 6,B \\
DRBAR & c6,0,c1,0 & Data Region Base Address Register & R \\
IRBAR & c6,0,c1,1 & Instruction Region Base Address Register & R \\
DRSR & c6,0,c1,2 & Data Region Size and Enable Register & R \\
IRSR & c6,0,c1,3 & Instruction Region Size and Enable Register & R \\
DRACR & c6,0,c1,4 & Data Region Access Control Register & R \\
IRACR & c6,0,c1,5 & Instruction Region Access Control Register & R \\
RGNR & c6,0,c2,0 & MPU Region Number Register & R \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 Generic Timer Registers}
CNTFRQ & c14,0,c0,0 & Counter Frequency Reg (Non-Secure RO) & 7 \\
CNTKCTL & c14,0,c1,0 & Timer PL1 Control Register & 7 \\
CNTP\_TVAL & c14,0,c2,0 & PL1 Physical TimerValue Register & 7,B \\
CNTP\_CTL & c14,0,c2,1 & PL1 Physical Timer Control Register & 7,B \\
CNTV\_TVAL & c14,0,c3,0 & Virtual TimerValue Register & 7 \\
CNTV\_CTL & c14,0,c3,1 & Virtual TimerControl Register & 7 \\
CNTPCT & c14,0 & Physical Count Register (RO) & 7 \\
CNTVCT & c14,1 & Virtual Count Register (RO) & 7 \\
CNTP\_CVAL & c14,2 & PL1 Physical Timer CompareValue Register & 7,B \\
CNTV\_CVAL & c14,3 & Virtual Timer CompareValue Register & 7 \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 ID Registers (Read-Only)}
MIDR & c0,0,c0,0 & Main ID Register & \\
CTR & c0,0,c0,1 & Cache Type Register & \\
TCMTR & c0,0,c0,2 & TCM Type Register & \\
TLBTR & c0,0,c0,3 & TLB Type Register & A \\
MPUIR & c0,0,c0,4 & MPU Type Register & R \\
MPIDR & c0,0,c0,5 & Multiprocessor Affinity Register & \\
REVIDR & c0,0,c0,6 & Revision ID & \\
ID\_PFR\{0..1\} & c0,0,c1,\{0..1\} & Processor Feature Registers & 6 \\
ID\_DFR0 & c0,0,c1,2 & Debug Feature Register 0 & 6 \\
ID\_AFR0 & c0,0,c1,3 & Auxiliary Feature Register 0 & 6 \\
ID\_MMFR\{0..3\} & c0,0,c1,\{4..7\} & Memory Model Feature Regs & 6 \\
ID\_ISAR\{0..5\} & c0,0,c2,\{0..5\} & Instruction Set Attribute Regs & 6 \\
CCSIDR & c0,1,c0,0 & Cache Size ID Register & 7 \\
CLIDR & c0,1,c0,1 & Cache Level ID Register & 7 \\
AIDR & c0,1,c0,7 & Auxiliary ID Register & 7 \\
CSSELR & c0,2,c0,0 & Cache Size Selection Register (RW) & 7,B \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 Cache Maintenance Registers (Write Only)}
CP15WFI & c7,0,c0,4 & Wait for interrupt operation & \\
ICIALLUIS & c7,0,c1,0 & Inv all instr caches to PoU Inner Sharable & 7 \\
BPIALLIS & c7,0,c1,6 & Inv all branche predictors Inner Sharable & 7 \\
PAR & c7,0,c4,0 & Physical Address Register (RW) & 7,A,B \\
ICIALLU & c7,0,c5,0 & Invalidate all instruction caches to PoU & \\
ICIMVAU & c7,0,c5,1 & Inv instruction caches by MVA to PoU & \\
% & c7,0,c5,2 & Invalidate instruction cache line by set/way & \sout{7} \\
CP15ISB & c7,0,c5,4 & Instruction Sync Barrier operation & 7 \\
BPIALL & c7,0,c5,6 & Invalidate all branch predictors & \\
BPIMVA & c7,0,c5,7 & Invalidate MVA from branch predictors & \\
% & c7,0,c6,0 & Invalidate data cache & \sout{7} \\
DCIMVAC & c7,0,c6,1 & Inv data cache line my MVA to PoC & \\
DCISW & c7,0,c6,2 & Invalidate data cache line by set/way & \\
% & c7,0,c7,0 & Invalidate unified cache & \sout{7} \\
% & c7,0,c7,1 & Invalidate unified cache line by MVA & \sout{7} \\
% & c7,0,c7,2 & Invalidate unified cache line by set/way & \sout{7} \\
ATS1CPR & c7,0,c8,0 & PL1 read translation (Current state) & 7,A \\
ATS1CPW & c7,0,c8,1 & PL1 write translation (Current state) & 7,A \\
ATS1CUR & c7,0,c8,2 & Unpriv read translation (Current state) & 7,A \\
ATS1CUW & c7,0,c8,3 & Unpriv write translation (Current state) & 7,A \\
ATS12NSOPR & c7,0,c8,4 & PL1 read translation (NS state) & 7,S \\
ATS12NSOPW & c7,0,c8,5 & PL1 write translation (NS state) & 7,S \\
ATS12NSOUR & c7,0,c8,6 & Unprivileged read translation (NS state) & 7,S \\
ATS12NSOUW & c7,0,c8,7 & Unprivileged write translation (NS state) & 7,S \\
% & c7,0,c10,0 & Clean data cache & 6,\sout{7} \\
DCCMVAC & c7,0,c10,1 & Clean data cache line my MVA to PoC & \\
DCCSW & c7,0,c10,2 & Clean data cache line by set/way & \\
% & c7,0,c10,3 & Test and clean data cache & \sout{7} \\
CP15DSB & c7,0,c10,4 & Data Synchronization Barrier operation & 7 \\
CP15DMB & c7,0,c10,5 & Data Memory Barrier operation & 7 \\
% & c7,0,c10,6 & Cache Dirty Status Register & 6,\sout{7} \\
% & c7,0,c11,0 & Clean entire unified cache & \sout{7} \\
DCCMVAU & c7,0,c11,1 & Clean data cache line by MVA to PoU & \\
% & c7,0,c11,2 & Clean unified cache line by set/way & \sout{7} \\
% & c7,0,c13,1 & Prefetch instruction cache line by MVA & \sout{7} \\
% & c7,0,c14,0 & Clean and invalidate data cache & 6,\sout{7} \\
DCCIMVAC & c7,0,c14,1 & Clean and inv data c-line by MVA to PoC & \\
DCCISW & c7,0,c14,2 & Clean and inv data c-line by set/way & \\
% & c7,0,c14,3 & Test and clean and invalidate data cache & \sout{7} \\
% & c7,0,c15,1 & Clean and invalidate unified cache line by MVA & \sout{7} \\
% & c7,0,c15,2 & Clean and invalidate unified cache line by set/way & \sout{7} \\
PAR & c7,0 & Physical Address Register (RW) & 7,A,B \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 Memory Protection and Control Registers (ARM-A only)}
TTBR0 & c2,0,c0,0 & Translation Table Base 0 & B \\
TTBR1 & c2,0,c0,1 & Translation Table Base 1 & 6,B \\
TTBCR & c2,0,c0,2 & Translation Table Base Control & 6,B \\
TTBR0 & c2,0 & Translation Table Base 0 (LPAE only) & 7,B \\