From 7b98df1f6e6c99838831071dea826acb530c33f9 Mon Sep 17 00:00:00 2001 From: Eliza Balas Date: Fri, 19 Apr 2024 13:13:41 +0300 Subject: [PATCH 1/2] arch: arm64: boot: dts: Remove iio channel 2 for TDD in zcu102/ad9081 dt - Add label for the iio-axi-tdd-0 device. - Export only channel 0 and channel 1 for TDD iio device. axi_tdd_0/tdd_channel_0 -> axi_data_offload_tx/sync_ext axi_tdd_0/tdd_channel_1 -> axi_data_offload_rx/sync_ext Signed-off-by: Eliza Balas --- .../dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts index 4961987c52b749..b3f2165329086a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts @@ -30,7 +30,7 @@ clock-names = "s_axi_aclk", "intf_clk"; }; - iio_axi_tdd_0@0 { + iio_axi_tdd_0: iio-axi-tdd-0@0 { compatible = "adi,iio-fake-platform-device"; adi,faked-dev = <&axi_tdd_0>; adi,attribute-names = @@ -44,10 +44,7 @@ "out_channel0_off_raw", "out_channel0_off_ms", "out_channel1_enable", "out_channel1_polarity", "out_channel1_on_raw", "out_channel1_on_ms", - "out_channel1_off_raw", "out_channel1_off_ms", - "out_channel2_enable", "out_channel2_polarity", - "out_channel2_on_raw", "out_channel2_on_ms", - "out_channel2_off_raw", "out_channel2_off_ms"; + "out_channel1_off_raw", "out_channel1_off_ms"; label = "axi-core-tdd"; }; }; From d02cfb2ecf03d0d35fdddec79e3d6fbc85e16cd7 Mon Sep 17 00:00:00 2001 From: Eliza Balas Date: Fri, 19 Apr 2024 15:11:00 +0300 Subject: [PATCH 2/2] arch: arm64: boot: dts: Overwrite the iio TDD node for Stingray dt In the Stingray project, 6 tdd channels are used. The first 2 channels are connected to the sync_ext pins of the data offload cores. axi_tdd_0/tdd_channel_0 -> axi_data_offload_tx/sync_ext axi_tdd_0/tdd_channel_1 -> axi_data_offload_rx/sync_ext The remaining 4 channels are mapped as following: axi_tdd_0/tdd_channel_2 -> tdd_enabled axi_tdd_0/tdd_channel_3 -> tdd_rx_mxfe_en axi_tdd_0/tdd_channel_4 -> tdd_tx_mxfe_en axi_tdd_0/tdd_channel_5 -> tdd_tx_stingray_en While the TDD core is enabled, tdd_channel_2 should always output logic '1', for the tdd_enabled signal. Signed-off-by: Eliza Balas --- .../xilinx/zynqmp-zcu102-rev10-stingray.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-stingray.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-stingray.dts index 13cdc6b74c874f..3f5f983709ac36 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-stingray.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-stingray.dts @@ -373,3 +373,30 @@ &axi_data_offload_tx { /delete-property/ adi,oneshot; }; + +&iio_axi_tdd_0 { + adi,attribute-names = + "version", "core_id", "scratch", "magic", + "sync_soft", "sync_external", "sync_internal", "sync_reset", + "enable", "startup_delay_raw", "startup_delay_ms", + "burst_count", "frame_length_raw", "frame_length_ms", + "state", "internal_sync_period_raw", "internal_sync_period_ms", + "out_channel0_enable", "out_channel0_polarity", + "out_channel0_on_raw", "out_channel0_on_ms", + "out_channel0_off_raw", "out_channel0_off_ms", + "out_channel1_enable", "out_channel1_polarity", + "out_channel1_on_raw", "out_channel1_on_ms", + "out_channel1_off_raw", "out_channel1_off_ms", + "out_channel2_enable", "out_channel2_polarity", + "out_channel2_on_raw", "out_channel2_on_ms", + "out_channel2_off_raw", "out_channel2_off_ms", + "out_channel3_enable", "out_channel3_polarity", + "out_channel3_on_raw", "out_channel3_on_ms", + "out_channel3_off_raw", "out_channel3_off_ms", + "out_channel4_enable", "out_channel4_polarity", + "out_channel4_on_raw", "out_channel4_on_ms", + "out_channel4_off_raw", "out_channel4_off_ms", + "out_channel5_enable", "out_channel5_polarity", + "out_channel5_on_raw", "out_channel5_on_ms", + "out_channel5_off_raw", "out_channel5_off_ms"; +};