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Memory initializers are ignored when synthesizing with Diamond

bug

toolchain:diamond

unsoundness

Status: Open.

#684 In amaranth-lang/amaranth;

· whitequark opened on Mar 12, 2022

<code>AsyncFIFO</code> removes data from read domain during read reset

bug

unsoundness

Status: Open.

#683 In amaranth-lang/amaranth;

· Lunaphied opened on Feb 23, 2022

Time-0 race condition for simulation

backend:verilog

bug

unsoundness

Status: Open.

#594 In amaranth-lang/amaranth;

· RobertBaruch opened on Feb 10, 2021

Memory with async read ports can synthesize to a BRAM on Xilinx platforms

improvement

platform:xilinx-7series

platform:xilinx-spartan-3/6

unsoundness

Status: Open.

#218 In amaranth-lang/amaranth;

· nmigen-issue-migration opened on Sep 20, 2019

r_data is undefined after a simultaneous write to an empty AsyncFIFO

bug

platform:all

unsoundness

Status: Open.

#217 In amaranth-lang/amaranth;

· nmigen-issue-migration opened on Sep 20, 2019

Require signals crossing clock domains to be explicitly marked

feature

meta:needs-rfc

unsoundness

Status: Open.

#6 In amaranth-lang/amaranth;

· nmigen-issue-migration opened on Dec 14, 2018