Open
Description
Version: 9167910
If I remove 1 MHz
in the example from the documentation,
sim.add_clock(Period(MHz=1))
then the VCD ends like this and does not contain any value changes:
...
$dumpvars
1!
0"
0#
b0 $
1%
$end
The minimum time interval is 1 fs. For a 1-0 cycle, the _femtoseconds
must be modified to 2:
amaranth/amaranth/hdl/_time.py
Lines 26 to 30 in 9167910
Motivation: In many designs, the absolute period is irrelevant. In this case, we can use a clock cycle of 2 fs.
If this makes sense, I can open a PR.