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Using sim.add_clock(Period()) (Period without any arguments) leads to an empty VCD file #1603

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@goekce

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@goekce

Version: 9167910

If I remove 1 MHz in the example from the documentation,

sim.add_clock(Period(MHz=1))

(from https://github.com/amaranth-lang/amaranth-lang.github.io/blob/0856ab9702c05600e159de2fc9c4ccbf2dcf3cf6/docs/amaranth/latest/_code/up_counter.py#L71)

then the VCD ends like this and does not contain any value changes:

...
$dumpvars
1!
0"
0#
b0 $
1%
$end

The minimum time interval is 1 fs. For a 1-0 cycle, the _femtoseconds must be modified to 2:

class Period:
def __init__(self, **kwargs):
if not kwargs:
self._femtoseconds = 0
return

Motivation: In many designs, the absolute period is irrelevant. In this case, we can use a clock cycle of 2 fs.

If this makes sense, I can open a PR.

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