add a max7219 based seven segment display for showing calculated pixels and core status

Author: hansfbaier

gateware/arrow_deca.py

@@ -94,6 +94,8 @@ class ArrowDECAPlatform(IntelPlatform, LUNAPlatform):
             pins="J21 J22",
             attrs=Attrs(io_standard="1.5 V")),
 
+        SPIResource(0, clk="P_9:11", copi="P_9:13", cipo=None, cs_n="P_9:15", attrs=Attrs(io_standard="3.3-V LVCMOS")),
+
         Resource("clk60", 0, Pins("H11", dir="i"), Clock(60e6), Attrs(io_standard="1.2 V")),
         Resource("usb", 0, Subsignal("fault", Pins("D8",  dir="i", invert=True),  Attrs(io_standard="1.2 V")),
                            Subsignal("cs",    Pins("J11", dir="o", invert=False), Attrs(io_standard="1.8 V"))),

gateware/deca_mandelbrot.py

@@ -9,6 +9,7 @@
 
 from nmigen_library.debug.ila   import StreamILA, ILACoreParameters
 from nmigen_library.stream      import connect_stream_to_fifo, connect_fifo_to_stream
+from nmigen_library.io.max7219  import SerialLEDArray, NumberToSevenSegmentHex
 
 from luna                import top_level_cli
 from luna.usb2           import USBDevice, USBStreamInEndpoint, USBStreamOutEndpoint
@@ -76,7 +77,7 @@ def elaborate(self, platform):
 
         # Generate our domain clocks/resets.
         m.submodules.car = platform.clock_domain_generator()
-        # Create our USB-to-serial converter.
+
         ulpi = platform.request(platform.default_usb_connection)
         m.submodules.usb = usb = USBDevice(bus=ulpi)
 
@@ -178,11 +179,22 @@ def elaborate(self, platform):
             leds[0].eq(usb.rx_activity_led),
             leds[1].eq(usb.tx_activity_led),
             leds[2].eq(usb.suspended),
-            Cat(leds[3:6]).eq(fractalmanager.busy),
+            Cat(leds[3:6]).eq(fractalmanager.busy_out),
             leds[6].eq(result_fifo.r_en),
             leds[7].eq(result_fifo.r_rdy),
         ]
 
+        spi = platform.request("spi")
+        m.submodules.sevensegment = sevensegment = NumberToSevenSegmentHex(width=32)
+        m.submodules.led_display = led_display= SerialLEDArray(divisor=8, init_delay=16e6)
+        m.d.comb += [
+            sevensegment.number_in.eq((fractalmanager.result_x_out << 16) | fractalmanager.result_y_out),
+            sevensegment.dots_in.eq(fractalmanager.busy_out),
+            *led_display.connect_to_resource(spi),
+            Cat(led_display.digits_in).eq(sevensegment.seven_segment_out),
+            led_display.valid_in.eq(1),
+        ]
+
         return m
 
 if __name__ == "__main__":

gateware/fractalmanager.py

@@ -19,7 +19,10 @@ def __init__(self, *, bitwidth, fraction_bits, no_cores, test=False):
         # I/O
         self.command_stream_in  = StreamInterface(name="command_stream")
         self.pixel_stream_out   = StreamInterface(name="pixel_stream")
-        self.busy               = Signal(no_cores)
+        self.busy_out           = Signal(no_cores)
+
+        self.result_x_out = Signal(16)
+        self.result_y_out = Signal(16)
 
     def elaborate(self, platform: Platform) -> Module:
         m = Module()
@@ -103,10 +106,10 @@ def elaborate(self, platform: Platform) -> Module:
         start    = Array([Signal(                  name=f"start_{n}")  for n in range(no_cores)])
         xs       = Array([Signal(signed(bitwidth), name=f"x_{n}")      for n in range(no_cores)])
         ys       = Array([Signal(signed(bitwidth), name=f"y_{n}")      for n in range(no_cores)])
-        pixel_x = Array([Signal(signed(bitwidth),  name=f"pixelx_{n}") for n in range(no_cores)])
-        pixel_y = Array([Signal(signed(bitwidth),  name=f"pixely_{n}") for n in range(no_cores)])
+        pixel_x  = Array([Signal(signed(bitwidth), name=f"pixelx_{n}") for n in range(no_cores)])
+        pixel_y  = Array([Signal(signed(bitwidth), name=f"pixely_{n}") for n in range(no_cores)])
 
-        m.d.comb += self.busy.eq(~Cat(idle))
+        m.d.comb += self.busy_out.eq(~Cat(idle))
 
         # result collector signals
         done       = Array([Signal(    name=f"done_{n}")    for n in range(no_cores)])
@@ -210,14 +213,18 @@ def elaborate(self, platform: Platform) -> Module:
 
         pixel_out = self.pixel_stream_out
         result_iterations = Signal(32)
-        result_color      = Signal(24)
         result_pixel_x    = Signal(16)
         result_pixel_y    = Signal(16)
         result_escape     = Signal()
         result_maxed      = Signal()
         send_byte         = Signal(8)
         first_result_sent = Signal()
 
+        m.d.comb += [
+            self.result_x_out.eq(result_pixel_x),
+            self.result_y_out.eq(result_pixel_y),
+        ]
+
         # result collector FSM
         with m.FSM(name="result_collector") as fsm:
             with m.State("WAIT"):