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4Kp60 Multi-Sensor HDR Camera Solution System Example Design for Agilex™ 5 Devices
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‎.gitmodules‎

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[submodule "modular-design-toolkit"]
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path = modular-design-toolkit
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url = https://github.com/altera-fpga/modular-design-toolkit.git
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branch = rel/25.1

‎AGX_5E_Altera_Modular_Dk_ISP_designs/AGX_5E_Modular_Devkit_ISP_FF_RD.xml‎

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<!--
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###################################################################################
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# Copyright (C) 2025 Altera Corporation
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#
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# This software and the related documents are Altera copyrighted materials, and
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# your use of them is governed by the express license under which they were
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# provided to you ("License"). Unless the License provides otherwise, you may
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# not use, modify, copy, publish, distribute, disclose or transmit this software
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# or the related documents without Altera's prior written permission.
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#
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# This software and the related documents are provided as is, with no express
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# or implied warranties, other than those that are expressly stated in the License.
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###################################################################################
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###################################################################################
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# Design: AGX_5E_Modular_Devkit_ISP_FF_RD
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#
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# Description: 4Kp60 Multi-Sensor HDR Camera Solution FPGA First System Example Design Demo
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###################################################################################
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-->
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<PROJECT name="agilex5_modkit_vvpisp">
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<DEVKIT>AGX_5E_Modular_Devkit</DEVKIT>
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<FAMILY>Agilex 5</FAMILY>
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<DEVICE>A5ED065BB32AE6SR0</DEVICE>
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<VERSION>25.1</VERSION>
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<QUARTUS_INI_COMMAND>vvp_ocs_enabled=on</QUARTUS_INI_COMMAND>
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<PIP>2</PIP>
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<VID_OUT_RATE>p60</VID_OUT_RATE>
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<VID_OUT_BPS>10</VID_OUT_BPS>
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<MULTI_SENSOR>1</MULTI_SENSOR>
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<EXP_FUSION_EN>1</EXP_FUSION_EN>
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<EN_DEBUG>1</EN_DEBUG>
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<SUBSYSTEM type="clock" name="clock_subsystem">
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<NUM_GEN_CLOCKS>6</NUM_GEN_CLOCKS>
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<GEN_CLK0_NAME>clk_0</GEN_CLK0_NAME>
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<GEN_CLK0_FREQ>297</GEN_CLK0_FREQ>
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<GEN_CLK1_NAME>clk_1</GEN_CLK1_NAME>
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<GEN_CLK1_FREQ>148.5</GEN_CLK1_FREQ>
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<GEN_CLK2_NAME>clk_2</GEN_CLK2_NAME>
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<GEN_CLK2_FREQ>200.0</GEN_CLK2_FREQ>
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<GEN_CLK3_NAME>clk_3</GEN_CLK3_NAME>
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<GEN_CLK3_FREQ>74.25</GEN_CLK3_FREQ>
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<GEN_CLK4_NAME>clk_4</GEN_CLK4_NAME>
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<GEN_CLK4_FREQ>16.0</GEN_CLK4_FREQ>
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<GEN_CLK5_NAME>clk_5</GEN_CLK5_NAME>
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<GEN_CLK5_FREQ>50.0</GEN_CLK5_FREQ>
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<RESET_MIN_LENGTH>3000</RESET_MIN_LENGTH>
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<EXPORT_TO_TOP>1</EXPORT_TO_TOP>
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</SUBSYSTEM>
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<SUBSYSTEM type="hps" name="hps_subsystem">
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<FPGA_EMIF_ENABLED>1</FPGA_EMIF_ENABLED>
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<FPGA_EMIF_WINDOW_BASE_ADDRESS>0x20000000</FPGA_EMIF_WINDOW_BASE_ADDRESS>
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<FPGA_EMIF_WINDOW_CTRL_BASE_ADDRESS>0x04000000</FPGA_EMIF_WINDOW_CTRL_BASE_ADDRESS>
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<FPGA_EMIF_HOST_ADDR_WIDTH>33</FPGA_EMIF_HOST_ADDR_WIDTH>
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<FPGA_EMIF_AGENT_ADDR_WIDTH>25</FPGA_EMIF_AGENT_ADDR_WIDTH>
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<H2F_EXPORT>FULL</H2F_EXPORT>
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<HPS_INIT>AFTER INIT_DONE</HPS_INIT>
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<I2C0_EXT_EN>1</I2C0_EXT_EN>
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<I2C1_EXT_EN>1</I2C1_EXT_EN>
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<I2C0_SCLK>100.0</I2C0_SCLK>
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<I2C1_SCLK>100.0</I2C1_SCLK>
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<HPS_AXI_CLK>200000000</HPS_AXI_CLK>
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<H2F_ADDRESS_WIDTH>34</H2F_ADDRESS_WIDTH>
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<F2SDRAM_ADDR_WIDTH>32</F2SDRAM_ADDR_WIDTH>
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</SUBSYSTEM>
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<SUBSYSTEM type="ocs" name="ocs_subsystem">
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00000000</OFFSET>
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</AVMM_HOST>
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<HPS_AXI_CLK>200000000</HPS_AXI_CLK>
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</SUBSYSTEM>
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<SUBSYSTEM type="cpu" name="niosv_subsystem">
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<CPU_SUBSYSTEM_TYPE>niosv</CPU_SUBSYSTEM_TYPE>
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<APPLICATION_DIR>./../custom_user_subsystems/isp_subsystems/software_dp_tx/.</APPLICATION_DIR>
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<BSP_SETTINGS_FILE>./../custom_user_subsystems/isp_subsystems/software_dp_tx/settings.bsp</BSP_SETTINGS_FILE>
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<CUSTOM_CMAKEFILE>1</CUSTOM_CMAKEFILE>
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<MEMORY_SIZE>0x40000</MEMORY_SIZE>
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<TIMER_TYPE>full</TIMER_TYPE>
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<TIMER_PERIOD>1</TIMER_PERIOD>
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<TIMER_UNITS>USEC</TIMER_UNITS>
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</SUBSYSTEM>
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<SUBSYSTEM type="emif" name="emif">
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<PORT>BANK_2B</PORT>
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<AVMM_EN>1</AVMM_EN>
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</SUBSYSTEM>
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<SUBSYSTEM type="board" name="board_subsystem">
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<USER_LED_TO_AVMM_EN>0</USER_LED_TO_AVMM_EN>
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<USER_PB_TO_AVMM_EN>0</USER_PB_TO_AVMM_EN>
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<USER_DIP_SW_TO_AVMM_EN>0</USER_DIP_SW_TO_AVMM_EN>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" script="./../custom_user_subsystems/isp_subsystems/system/isp_system_create.tcl">
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<FITTER_SEED>7</FITTER_SEED>
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<OPTIMIZATION_MODE>3</OPTIMIZATION_MODE>
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<SYNTH_WYSIWYG>1</SYNTH_WYSIWYG>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="dp_tx" script="./../custom_user_subsystems/isp_subsystems/subsystems/dp_tx_subsystem/dp_tx_create.tcl">
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<I2C_MASTER_IRQ_PRIORITY>2</I2C_MASTER_IRQ_PRIORITY>
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<I2C_MASTER_IRQ_HOST>niosv_subsystem</I2C_MASTER_IRQ_HOST>
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<I2C_BOARD_IRQ_PRIORITY>3</I2C_BOARD_IRQ_PRIORITY>
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<I2C_BOARD_IRQ_HOST>niosv_subsystem</I2C_BOARD_IRQ_HOST>
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<DP_IRQ_PRIORITY>4</DP_IRQ_PRIORITY>
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<DP_IRQ_HOST>niosv_subsystem</DP_IRQ_HOST>
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<AVMM_HOST>
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<NAME>niosv_subsystem</NAME>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="vid_out_subsystem" script="./../custom_user_subsystems/isp_subsystems/subsystems/vid_fr4k_out_subsystem/vid_fr4k_out_create.tcl">
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<VID_OUT_TPG_EN>0</VID_OUT_TPG_EN>
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<PIP_CONV_FIFO_DEPTH>2048</PIP_CONV_FIFO_DEPTH>
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00500000</OFFSET>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="mipi_in_subsystem" script="./../custom_user_subsystems/isp_subsystems/subsystems/mipi_4k_in_subsystem/framos_imx678/mipi_in_framos_imx678_create.tcl">
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00400000</OFFSET>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="isp_in_subsystem" script="./../custom_user_subsystems/isp_subsystems/subsystems/isp_4k_in_subsystem/isp_4k_in_create.tcl">
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00300000</OFFSET>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="isp_subsystem" script="./../custom_user_subsystems/isp_subsystems/subsystems/isp_4k_subsystem/isp_4k_create.tcl">
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<HDR_EN>1</HDR_EN>
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<SMALL_3DLUT>1</SMALL_3DLUT>
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<WARP_SB>1</WARP_SB>
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00200000</OFFSET>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" script="./../custom_user_subsystems/isp_subsystems/subsystems/ocs_modification_subsystem/ocs_modification_create.tcl">
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</SUBSYSTEM>
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</PROJECT>

‎AGX_5E_Altera_Modular_Dk_ISP_designs/AGX_5E_Modular_Devkit_ISP_RD.xml‎

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<!--
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###################################################################################
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# Copyright (C) 2025 Altera Corporation
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#
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# This software and the related documents are Altera copyrighted materials, and
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# your use of them is governed by the express license under which they were
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# provided to you ("License"). Unless the License provides otherwise, you may
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# not use, modify, copy, publish, distribute, disclose or transmit this software
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# or the related documents without Altera's prior written permission.
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#
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# This software and the related documents are provided as is, with no express
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# or implied warranties, other than those that are expressly stated in the License.
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###################################################################################
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###################################################################################
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# Design: AGX_5E_Modular_Devkit_ISP_RD
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#
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# Description: 4Kp60 Multi-Sensor HDR Camera Solution System Example Design Demo
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###################################################################################
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-->
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<PROJECT name="agilex5_modkit_vvpisp">
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<DEVKIT>AGX_5E_Modular_Devkit</DEVKIT>
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<FAMILY>Agilex 5</FAMILY>
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<DEVICE>A5ED065BB32AE6SR0</DEVICE>
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<VERSION>25.1</VERSION>
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<QUARTUS_INI_COMMAND>vvp_ocs_enabled=on</QUARTUS_INI_COMMAND>
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<PIP>2</PIP>
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<VID_OUT_RATE>p60</VID_OUT_RATE>
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<VID_OUT_BPS>10</VID_OUT_BPS>
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<MULTI_SENSOR>1</MULTI_SENSOR>
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<EXP_FUSION_EN>1</EXP_FUSION_EN>
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<EN_DEBUG>1</EN_DEBUG>
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<SUBSYSTEM type="clock" name="clock_subsystem">
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<NUM_GEN_CLOCKS>6</NUM_GEN_CLOCKS>
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<GEN_CLK0_NAME>clk_0</GEN_CLK0_NAME>
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<GEN_CLK0_FREQ>297</GEN_CLK0_FREQ>
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<GEN_CLK1_NAME>clk_1</GEN_CLK1_NAME>
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<GEN_CLK1_FREQ>148.5</GEN_CLK1_FREQ>
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<GEN_CLK2_NAME>clk_2</GEN_CLK2_NAME>
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<GEN_CLK2_FREQ>200.0</GEN_CLK2_FREQ>
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<GEN_CLK3_NAME>clk_3</GEN_CLK3_NAME>
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<GEN_CLK3_FREQ>74.25</GEN_CLK3_FREQ>
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<GEN_CLK4_NAME>clk_4</GEN_CLK4_NAME>
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<GEN_CLK4_FREQ>16.0</GEN_CLK4_FREQ>
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<GEN_CLK5_NAME>clk_5</GEN_CLK5_NAME>
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<GEN_CLK5_FREQ>50.0</GEN_CLK5_FREQ>
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<RESET_MIN_LENGTH>3000</RESET_MIN_LENGTH>
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<EXPORT_TO_TOP>1</EXPORT_TO_TOP>
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</SUBSYSTEM>
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<SUBSYSTEM type="hps" name="hps_subsystem">
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<FPGA_EMIF_ENABLED>1</FPGA_EMIF_ENABLED>
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<FPGA_EMIF_WINDOW_BASE_ADDRESS>0x20000000</FPGA_EMIF_WINDOW_BASE_ADDRESS>
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<FPGA_EMIF_WINDOW_CTRL_BASE_ADDRESS>0x04000000</FPGA_EMIF_WINDOW_CTRL_BASE_ADDRESS>
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<FPGA_EMIF_HOST_ADDR_WIDTH>33</FPGA_EMIF_HOST_ADDR_WIDTH>
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<FPGA_EMIF_AGENT_ADDR_WIDTH>25</FPGA_EMIF_AGENT_ADDR_WIDTH>
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<H2F_EXPORT>FULL</H2F_EXPORT>
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<HPS_INIT>HPS FIRST</HPS_INIT>
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<I2C0_EXT_EN>1</I2C0_EXT_EN>
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<I2C1_EXT_EN>1</I2C1_EXT_EN>
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<I2C0_SCLK>100.0</I2C0_SCLK>
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<I2C1_SCLK>100.0</I2C1_SCLK>
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<HPS_AXI_CLK>200000000</HPS_AXI_CLK>
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<H2F_ADDRESS_WIDTH>34</H2F_ADDRESS_WIDTH>
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<F2SDRAM_ADDR_WIDTH>32</F2SDRAM_ADDR_WIDTH>
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</SUBSYSTEM>
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<SUBSYSTEM type="ocs" name="ocs_subsystem">
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00000000</OFFSET>
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</AVMM_HOST>
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<HPS_AXI_CLK>200000000</HPS_AXI_CLK>
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</SUBSYSTEM>
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<SUBSYSTEM type="cpu" name="niosv_subsystem">
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<CPU_SUBSYSTEM_TYPE>niosv</CPU_SUBSYSTEM_TYPE>
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<APPLICATION_DIR>./../custom_user_subsystems/isp_subsystems/software_dp_tx/.</APPLICATION_DIR>
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<BSP_SETTINGS_FILE>./../custom_user_subsystems/isp_subsystems/software_dp_tx/settings.bsp</BSP_SETTINGS_FILE>
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<CUSTOM_CMAKEFILE>1</CUSTOM_CMAKEFILE>
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<MEMORY_SIZE>0x40000</MEMORY_SIZE>
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<TIMER_TYPE>full</TIMER_TYPE>
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<TIMER_PERIOD>1</TIMER_PERIOD>
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<TIMER_UNITS>USEC</TIMER_UNITS>
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</SUBSYSTEM>
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<SUBSYSTEM type="emif" name="emif">
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<PORT>BANK_2B</PORT>
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<AVMM_EN>1</AVMM_EN>
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</SUBSYSTEM>
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<SUBSYSTEM type="board" name="board_subsystem">
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<USER_LED_TO_AVMM_EN>0</USER_LED_TO_AVMM_EN>
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<USER_PB_TO_AVMM_EN>0</USER_PB_TO_AVMM_EN>
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<USER_DIP_SW_TO_AVMM_EN>0</USER_DIP_SW_TO_AVMM_EN>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" script="./../custom_user_subsystems/isp_subsystems/system/isp_system_create.tcl">
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<FITTER_SEED>7</FITTER_SEED>
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<OPTIMIZATION_MODE>4</OPTIMIZATION_MODE>
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<SYNTH_WYSIWYG>1</SYNTH_WYSIWYG>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="dp_tx" script="./../custom_user_subsystems/isp_subsystems/subsystems/dp_tx_subsystem/dp_tx_create.tcl">
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<I2C_MASTER_IRQ_PRIORITY>2</I2C_MASTER_IRQ_PRIORITY>
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<I2C_MASTER_IRQ_HOST>niosv_subsystem</I2C_MASTER_IRQ_HOST>
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<I2C_BOARD_IRQ_PRIORITY>3</I2C_BOARD_IRQ_PRIORITY>
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<I2C_BOARD_IRQ_HOST>niosv_subsystem</I2C_BOARD_IRQ_HOST>
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<DP_IRQ_PRIORITY>4</DP_IRQ_PRIORITY>
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<DP_IRQ_HOST>niosv_subsystem</DP_IRQ_HOST>
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<AVMM_HOST>
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<NAME>niosv_subsystem</NAME>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="vid_out_subsystem" script="./../custom_user_subsystems/isp_subsystems/subsystems/vid_fr4k_out_subsystem/vid_fr4k_out_create.tcl">
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<VID_OUT_TPG_EN>0</VID_OUT_TPG_EN>
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<PIP_CONV_FIFO_DEPTH>2048</PIP_CONV_FIFO_DEPTH>
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00500000</OFFSET>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="mipi_in_subsystem" script="./../custom_user_subsystems/isp_subsystems/subsystems/mipi_4k_in_subsystem/framos_imx678/mipi_in_framos_imx678_create.tcl">
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00400000</OFFSET>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="isp_in_subsystem" script="./../custom_user_subsystems/isp_subsystems/subsystems/isp_4k_in_subsystem/isp_4k_in_create.tcl">
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00300000</OFFSET>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" name="isp_subsystem" script="./../custom_user_subsystems/isp_subsystems/subsystems/isp_4k_subsystem/isp_4k_create.tcl">
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<HDR_EN>1</HDR_EN>
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<SMALL_3DLUT>1</SMALL_3DLUT>
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<WARP_SB>1</WARP_SB>
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<AVMM_HOST>
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<NAME>hps_subsystem</NAME>
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<OFFSET>0x00200000</OFFSET>
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</AVMM_HOST>
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</SUBSYSTEM>
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<SUBSYSTEM type="user" script="./../custom_user_subsystems/isp_subsystems/subsystems/ocs_modification_subsystem/ocs_modification_create.tcl">
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</SUBSYSTEM>
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</PROJECT>

‎AGX_5E_Altera_Modular_Dk_ISP_designs/README.md‎

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# 4Kp60 Multi-Sensor HDR Camera Solution System Example Design for Agilex™ 5 Devices - Design Variations
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## Overview
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The 4Kp60 Multi-Sensor HDR Camera Solution System Example Design uses the Modular
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Design Toolkit (MDT). The MDT is a method of creating and building Platform
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Designer (PD) based Quartus® projects from a single `.xml` file.
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A different `.xml` file is used for different variations of the design.
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<br>
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<br>
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## 4Kp60 Multi-Sensor HDR Camera Solution System Example Design - FPGA First MDT Flow
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The 4Kp60 Multi-Sensor HDR Camera Solution System Example Design for OpenCore Plus
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(OCP) Quartus® license users.
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[AGX_5E_Modular_Devkit_ISP_FF_RD.xml](https://github.com/altera-fpga/agilex-ed-camera/blob/rel-25.1/AGX_5E_Altera_Modular_Dk_ISP_designs/AGX_5E_Modular_Devkit_ISP_FF_RD.xml)
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<br>
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## 4Kp60 Multi-Sensor HDR Camera Solution System Example Design - HPS First MDT Flow
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The 4Kp60 Multi-Sensor HDR Camera Solution System Example Design for full Quartus®
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license users.
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[AGX_5E_Modular_Devkit_ISP_RD.xml](https://github.com/altera-fpga/agilex-ed-camera/blob/rel-25.1/AGX_5E_Altera_Modular_Dk_ISP_designs/AGX_5E_Modular_Devkit_ISP_RD.xml)
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