pulley: Get f{32,64}_bitwise.wast tests working

Fill out some more misc float ops. cc bytecodealliance#9783
alexcrichton · Dec 11, 2024 · a54c310 · a54c310
1 parent 4ae6140
commit a54c310
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Showing 4 changed files with 65 additions and 5 deletions.
diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.isle b/cranelift/codegen/src/isa/pulley_shared/lower.isle
@@ -645,3 +645,18 @@
 
 (rule (lower (has_type $F32 (sqrt a))) (pulley_fsqrt32 a))
 (rule (lower (has_type $F64 (sqrt a))) (pulley_fsqrt64 a))
+
+;;;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type $F32 (fcopysign a b))) (pulley_fcopysign32 a b))
+(rule (lower (has_type $F64 (fcopysign a b))) (pulley_fcopysign64 a b))
+
+;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type $F32 (fneg a))) (pulley_fneg32 a))
+(rule (lower (has_type $F64 (fneg a))) (pulley_fneg64 a))
+
+;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type $F32 (fabs a))) (pulley_fabs32 a))
+(rule (lower (has_type $F64 (fabs a))) (pulley_fabs64 a))
diff --git a/crates/wast-util/src/lib.rs b/crates/wast-util/src/lib.rs
@@ -400,7 +400,6 @@ impl WastTest {
                 "misc_testsuite/embenchen_ifs.wast",
                 "misc_testsuite/embenchen_primes.wast",
                 "misc_testsuite/int-to-float-splat.wast",
-                "misc_testsuite/issue4890.wast",
                 "misc_testsuite/issue6562.wast",
                 "misc_testsuite/memory-combos.wast",
                 "misc_testsuite/memory64/simd.wast",
@@ -429,10 +428,6 @@ impl WastTest {
                 "misc_testsuite/winch/_simd_load.wast",
                 "misc_testsuite/winch/_simd_multivalue.wast",
                 "misc_testsuite/winch/_simd_store.wast",
-                "spec_testsuite/f32_bitwise.wast",
-                "spec_testsuite/f64_bitwise.wast",
-                "spec_testsuite/float_exprs.wast",
-                "spec_testsuite/float_misc.wast",
                 "spec_testsuite/proposals/annotations/simd_lane.wast",
                 "spec_testsuite/proposals/multi-memory/simd_memory-multi.wast",
                 "spec_testsuite/proposals/relaxed-simd/i16x8_relaxed_q15mulr_s.wast",

diff --git a/pulley/src/interp.rs b/pulley/src/interp.rs
@@ -2203,6 +2203,13 @@ impl OpVisitor for Interpreter<'_> {
         ControlFlow::Continue(())
     }
 
+    fn fcopysign32(&mut self, operands: BinaryOperands<FReg>) -> ControlFlow<Done> {
+        let a = self.state[operands.src1].get_f32();
+        let b = self.state[operands.src2].get_f32();
+        self.state[operands.dst].set_f32(a.copysign(b));
+        ControlFlow::Continue(())
+    }
+
     fn ftrunc32(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
         let a = self.state[src].get_f32();
         self.state[dst].set_f32(a.trunc());
@@ -2233,6 +2240,18 @@ impl OpVisitor for Interpreter<'_> {
         ControlFlow::Continue(())
     }
 
+    fn fneg32(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
+        let a = self.state[src].get_f32();
+        self.state[dst].set_f32(-a);
+        ControlFlow::Continue(())
+    }
+
+    fn fabs32(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
+        let a = self.state[src].get_f32();
+        self.state[dst].set_f32(a.abs());
+        ControlFlow::Continue(())
+    }
+
     fn fadd64(&mut self, operands: BinaryOperands<FReg>) -> ControlFlow<Done> {
         let a = self.state[operands.src1].get_f64();
         let b = self.state[operands.src2].get_f64();
@@ -2334,6 +2353,25 @@ impl OpVisitor for Interpreter<'_> {
         self.state[dst].set_f64(a.sqrt());
         ControlFlow::Continue(())
     }
+
+    fn fcopysign64(&mut self, operands: BinaryOperands<FReg>) -> ControlFlow<Done> {
+        let a = self.state[operands.src1].get_f64();
+        let b = self.state[operands.src2].get_f64();
+        self.state[operands.dst].set_f64(a.copysign(b));
+        ControlFlow::Continue(())
+    }
+
+    fn fneg64(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
+        let a = self.state[src].get_f64();
+        self.state[dst].set_f64(-a);
+        ControlFlow::Continue(())
+    }
+
+    fn fabs64(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
+        let a = self.state[src].get_f64();
+        self.state[dst].set_f64(a.abs());
+        ControlFlow::Continue(())
+    }
 }
 
 impl ExtendedOpVisitor for Interpreter<'_> {

diff --git a/pulley/src/lib.rs b/pulley/src/lib.rs
@@ -500,6 +500,12 @@ macro_rules! for_each_op {
             fnearest32 = Fnearest32 { dst: FReg, src: FReg };
             /// `low32(dst) = ieee_sqrt(low32(src))`
             fsqrt32 = Fsqrt32 { dst: FReg, src: FReg };
+            /// `low32(dst) = ieee_copysign(low32(src1), low32(src2))`
+            fcopysign32 = Fcopysign32 { operands: BinaryOperands<FReg> };
+            /// `low32(dst) = -low32(src)`
+            fneg32 = Fneg32 { dst: FReg, src: FReg };
+            /// `low32(dst) = |low32(src)|`
+            fabs32 = Fabs32 { dst: FReg, src: FReg };
 
             /// `dst = src1 + src2`
             fadd64 = Fadd64 { operands: BinaryOperands<FReg> };
@@ -523,6 +529,12 @@ macro_rules! for_each_op {
             fnearest64 = Fnearest64 { dst: FReg, src: FReg };
             /// `dst = ieee_sqrt(src)`
             fsqrt64 = Fsqrt64 { dst: FReg, src: FReg };
+            /// `dst = ieee_copysign(src1, src2)`
+            fcopysign64 = Fcopysign64 { operands: BinaryOperands<FReg> };
+            /// `dst = -src`
+            fneg64 = Fneg64 { dst: FReg, src: FReg };
+            /// `dst = |src|`
+            fabs64 = Fabs64 { dst: FReg, src: FReg };
         }
     };
 }