diff --git a/PermissionManager/.gitignore b/PermissionManager/.gitignore
new file mode 100644
index 00000000..aa724b77
--- /dev/null
+++ b/PermissionManager/.gitignore
@@ -0,0 +1,15 @@
+*.iml
+.gradle
+/local.properties
+/.idea/caches
+/.idea/libraries
+/.idea/modules.xml
+/.idea/workspace.xml
+/.idea/navEditor.xml
+/.idea/assetWizardSettings.xml
+.DS_Store
+/build
+/captures
+.externalNativeBuild
+.cxx
+local.properties
diff --git a/PermissionManager/.idea/.gitignore b/PermissionManager/.idea/.gitignore
new file mode 100644
index 00000000..26d33521
--- /dev/null
+++ b/PermissionManager/.idea/.gitignore
@@ -0,0 +1,3 @@
+# Default ignored files
+/shelf/
+/workspace.xml
diff --git a/PermissionManager/.idea/compiler.xml b/PermissionManager/.idea/compiler.xml
new file mode 100644
index 00000000..fb7f4a8a
--- /dev/null
+++ b/PermissionManager/.idea/compiler.xml
@@ -0,0 +1,6 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/.idea/gradle.xml b/PermissionManager/.idea/gradle.xml
new file mode 100644
index 00000000..526b4c25
--- /dev/null
+++ b/PermissionManager/.idea/gradle.xml
@@ -0,0 +1,20 @@
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/.idea/misc.xml b/PermissionManager/.idea/misc.xml
new file mode 100644
index 00000000..10a0ff7f
--- /dev/null
+++ b/PermissionManager/.idea/misc.xml
@@ -0,0 +1,33 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/Scrooge b/PermissionManager/Scrooge
new file mode 100644
index 00000000..8b137891
--- /dev/null
+++ b/PermissionManager/Scrooge
@@ -0,0 +1 @@
+
diff --git a/PermissionManager/app/.gitignore b/PermissionManager/app/.gitignore
new file mode 100644
index 00000000..42afabfd
--- /dev/null
+++ b/PermissionManager/app/.gitignore
@@ -0,0 +1 @@
+/build
\ No newline at end of file
diff --git a/PermissionManager/app/appKey.jks b/PermissionManager/app/appKey.jks
new file mode 100644
index 00000000..95ea5aef
Binary files /dev/null and b/PermissionManager/app/appKey.jks differ
diff --git a/PermissionManager/app/build.gradle b/PermissionManager/app/build.gradle
new file mode 100644
index 00000000..02da6ec2
--- /dev/null
+++ b/PermissionManager/app/build.gradle
@@ -0,0 +1,53 @@
+plugins {
+ id 'com.android.application'
+}
+
+android {
+ compileSdk 31
+
+ defaultConfig {
+ applicationId "com.linux.permissionmanager"
+ minSdk 26
+ targetSdk 31
+ versionCode 1
+ versionName "1.0"
+
+ testInstrumentationRunner "androidx.test.runner.AndroidJUnitRunner"
+ externalNativeBuild {
+ cmake {
+ cppFlags '-std=c++17'
+ abiFilters "arm64-v8a" //需要什么构架的so,就在这边添加即
+ }
+ }
+ }
+
+ buildTypes {
+ release {
+ minifyEnabled false
+ proguardFiles getDefaultProguardFile('proguard-android-optimize.txt'), 'proguard-rules.pro'
+ }
+ }
+ compileOptions {
+ sourceCompatibility JavaVersion.VERSION_1_8
+ targetCompatibility JavaVersion.VERSION_1_8
+ }
+ externalNativeBuild {
+ cmake {
+ path file('src/main/cpp/CMakeLists.txt')
+ version '3.18.1'
+ }
+ }
+ buildFeatures {
+ viewBinding true
+ }
+}
+
+dependencies {
+
+ implementation 'androidx.appcompat:appcompat:1.4.1'
+ implementation 'com.google.android.material:material:1.5.0'
+ implementation 'androidx.constraintlayout:constraintlayout:2.1.3'
+ testImplementation 'junit:junit:4.13.2'
+ androidTestImplementation 'androidx.test.ext:junit:1.1.3'
+ androidTestImplementation 'androidx.test.espresso:espresso-core:3.4.0'
+}
\ No newline at end of file
diff --git a/PermissionManager/app/proguard-rules.pro b/PermissionManager/app/proguard-rules.pro
new file mode 100644
index 00000000..481bb434
--- /dev/null
+++ b/PermissionManager/app/proguard-rules.pro
@@ -0,0 +1,21 @@
+# Add project specific ProGuard rules here.
+# You can control the set of applied configuration files using the
+# proguardFiles setting in build.gradle.
+#
+# For more details, see
+# http://developer.android.com/guide/developing/tools/proguard.html
+
+# If your project uses WebView with JS, uncomment the following
+# and specify the fully qualified class name to the JavaScript interface
+# class:
+#-keepclassmembers class fqcn.of.javascript.interface.for.webview {
+# public *;
+#}
+
+# Uncomment this to preserve the line number information for
+# debugging stack traces.
+#-keepattributes SourceFile,LineNumberTable
+
+# If you keep the line number information, uncomment this to
+# hide the original source file name.
+#-renamesourcefileattribute SourceFile
\ No newline at end of file
diff --git a/PermissionManager/app/src/androidTest/java/com/linux/permissionmanager/ExampleInstrumentedTest.java b/PermissionManager/app/src/androidTest/java/com/linux/permissionmanager/ExampleInstrumentedTest.java
new file mode 100644
index 00000000..e63884ad
--- /dev/null
+++ b/PermissionManager/app/src/androidTest/java/com/linux/permissionmanager/ExampleInstrumentedTest.java
@@ -0,0 +1,26 @@
+package com.linux.permissionmanager;
+
+import android.content.Context;
+
+import androidx.test.platform.app.InstrumentationRegistry;
+import androidx.test.ext.junit.runners.AndroidJUnit4;
+
+import org.junit.Test;
+import org.junit.runner.RunWith;
+
+import static org.junit.Assert.*;
+
+/**
+ * Instrumented test, which will execute on an Android device.
+ *
+ * @see Testing documentation
+ */
+@RunWith(AndroidJUnit4.class)
+public class ExampleInstrumentedTest {
+ @Test
+ public void useAppContext() {
+ // Context of the app under test.
+ Context appContext = InstrumentationRegistry.getInstrumentation().getTargetContext();
+ assertEquals("com.linux.permissionmanager", appContext.getPackageName());
+ }
+}
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/AndroidManifest.xml b/PermissionManager/app/src/main/AndroidManifest.xml
new file mode 100644
index 00000000..ac7de7ed
--- /dev/null
+++ b/PermissionManager/app/src/main/AndroidManifest.xml
@@ -0,0 +1,28 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/cpp/CMakeLists.txt b/PermissionManager/app/src/main/cpp/CMakeLists.txt
new file mode 100644
index 00000000..23b18751
--- /dev/null
+++ b/PermissionManager/app/src/main/cpp/CMakeLists.txt
@@ -0,0 +1,54 @@
+# For more information about using CMake with Android Studio, read the
+# documentation: https://d.android.com/studio/projects/add-native-code.html
+
+# Sets the minimum version of CMake required to build the native library.
+
+cmake_minimum_required(VERSION 3.18.1)
+
+# Declares and names the project.
+
+project("permissionmanager")
+
+# Creates and names a library, sets it as either STATIC
+# or SHARED, and provides the relative paths to its source code.
+# You can define multiple libraries, and CMake builds them for you.
+# Gradle automatically packages shared libraries with your APK.
+
+add_library( # Sets the name of the library.
+ permissionmanager
+
+ # Sets the library as a shared library.
+ SHARED
+
+ # Provides a relative path to your source file(s).
+ ../../../../../testRoot/jni/kernel_root_kit/kernel_root_kit_process64_inject.cpp
+ ../../../../../testRoot/jni/kernel_root_kit/kernel_root_kit_ptrace_arm64_utils.cpp
+ ../../../../../testRoot/jni/kernel_root_kit/kernel_root_kit_su_install_helper.cpp
+ ../../../../../testRoot/jni/kernel_root_kit/kernel_root_kit_parasite_app.cpp
+ ../../../../../testRoot/jni/kernel_root_kit/kernel_root_kit_parasite_patch_elf.cpp
+ cJSON.c
+ root.cpp)
+
+# Searches for a specified prebuilt library and stores the path as a
+# variable. Because CMake includes system libraries in the search path by
+# default, you only need to specify the name of the public NDK library
+# you want to add. CMake verifies that the library exists before
+# completing its build.
+
+find_library( # Sets the name of the path variable.
+ log-lib
+
+ # Specifies the name of the NDK library that
+ # you want CMake to locate.
+ log)
+
+# Specifies libraries CMake should link to your target library. You
+# can link multiple libraries, such as libraries you define in this
+# build script, prebuilt third-party libraries, or system libraries.
+
+target_link_libraries( # Specifies the target library.
+ permissionmanager
+
+ # Links the target library to the log library
+ # included in the NDK.
+ ${log-lib})
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/cpp/cJSON.c b/PermissionManager/app/src/main/cpp/cJSON.c
new file mode 100644
index 00000000..c62e9eed
--- /dev/null
+++ b/PermissionManager/app/src/main/cpp/cJSON.c
@@ -0,0 +1,750 @@
+/*
+ Copyright (c) 2009 Dave Gamble
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+/* cJSON */
+/* JSON parser in C. */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "cJSON.h"
+
+static const char *ep;
+
+const char *cJSON_GetErrorPtr(void) {return ep;}
+
+static int cJSON_strcasecmp(const char *s1,const char *s2)
+{
+ if (!s1) return (s1==s2)?0:1;if (!s2) return 1;
+ for(; tolower(*s1) == tolower(*s2); ++s1, ++s2) if(*s1 == 0) return 0;
+ return tolower(*(const unsigned char *)s1) - tolower(*(const unsigned char *)s2);
+}
+
+static void *(*cJSON_malloc)(size_t sz) = malloc;
+static void (*cJSON_free)(void *ptr) = free;
+
+static char* cJSON_strdup(const char* str)
+{
+ size_t len;
+ char* copy;
+
+ len = strlen(str) + 1;
+ if (!(copy = (char*)cJSON_malloc(len))) return 0;
+ memcpy(copy,str,len);
+ return copy;
+}
+
+void cJSON_InitHooks(cJSON_Hooks* hooks)
+{
+ if (!hooks) { /* Reset hooks */
+ cJSON_malloc = malloc;
+ cJSON_free = free;
+ return;
+ }
+
+ cJSON_malloc = (hooks->malloc_fn)?hooks->malloc_fn:malloc;
+ cJSON_free = (hooks->free_fn)?hooks->free_fn:free;
+}
+
+/* Internal constructor. */
+static cJSON *cJSON_New_Item(void)
+{
+ cJSON* node = (cJSON*)cJSON_malloc(sizeof(cJSON));
+ if (node) memset(node,0,sizeof(cJSON));
+ return node;
+}
+
+/* Delete a cJSON structure. */
+void cJSON_Delete(cJSON *c)
+{
+ cJSON *next;
+ while (c)
+ {
+ next=c->next;
+ if (!(c->type&cJSON_IsReference) && c->child) cJSON_Delete(c->child);
+ if (!(c->type&cJSON_IsReference) && c->valuestring) cJSON_free(c->valuestring);
+ if (!(c->type&cJSON_StringIsConst) && c->string) cJSON_free(c->string);
+ cJSON_free(c);
+ c=next;
+ }
+}
+
+/* Parse the input text to generate a number, and populate the result into item. */
+static const char *parse_number(cJSON *item,const char *num)
+{
+ long long n=0,sign=1,scale=0;long long subscale=0,signsubscale=1,temp = 0;
+
+ if (*num=='-') sign=-1,num++; /* Has sign? */
+ if (*num=='0') num++; /* is zero */
+ if (*num>='1' && *num<='9') do n=(n*10.0)+(*num++ -'0'); while (*num>='0' && *num<='9'); /* Number? */
+ if (*num=='.' && num[1]>='0' && num[1]<='9') {num++; do n=(n*10.0)+(*num++ -'0'),scale--; while (*num>='0' && *num<='9');} /* Fractional part? */
+ if (*num=='e' || *num=='E') /* Exponent? */
+ { num++;if (*num=='+') num++; else if (*num=='-') signsubscale=-1,num++; /* With sign? */
+ while (*num>='0' && *num<='9') subscale=(subscale*10)+(*num++ - '0'); /* Number? */
+ }
+ temp = n;
+ n=sign*n*pow(10.0,(scale+subscale*signsubscale)); /* number = +/- number.fraction * 10^+/- exponent */
+
+ item->valuedouble=(double)n; //convert double
+ item->valueint= temp; //convert long long
+ item->type=cJSON_Number;
+ return num;
+}
+
+static int pow2gt (int x) { --x; x|=x>>1; x|=x>>2; x|=x>>4; x|=x>>8; x|=x>>16; return x+1; }
+
+typedef struct {char *buffer; int length; int offset; } printbuffer;
+
+static char* ensure(printbuffer *p,int needed)
+{
+ char *newbuffer;int newsize;
+ if (!p || !p->buffer) return 0;
+ needed+=p->offset;
+ if (needed<=p->length) return p->buffer+p->offset;
+
+ newsize=pow2gt(needed);
+ newbuffer=(char*)cJSON_malloc(newsize);
+ if (!newbuffer) {cJSON_free(p->buffer);p->length=0,p->buffer=0;return 0;}
+ if (newbuffer) memcpy(newbuffer,p->buffer,p->length);
+ cJSON_free(p->buffer);
+ p->length=newsize;
+ p->buffer=newbuffer;
+ return newbuffer+p->offset;
+}
+
+static int update(printbuffer *p)
+{
+ char *str;
+ if (!p || !p->buffer) return 0;
+ str=p->buffer+p->offset;
+ return p->offset+strlen(str);
+}
+
+/* Render the number nicely from the given item into a string. */
+static char *print_number(cJSON *item,printbuffer *p)
+{
+ char *str=0;
+ double d=item->valuedouble;
+ if (d==0)
+ {
+ if (p) str=ensure(p,2);
+ else str=(char*)cJSON_malloc(2); /* special case for 0. */
+ if (str) strcpy(str,"0");
+ }
+ else if (fabs(((double)item->valueint)-d)<=DBL_EPSILON && d<=INT_MAX && d>=INT_MIN)
+ {
+ if (p) str=ensure(p,21);
+ else str=(char*)cJSON_malloc(21); /* 2^64+1 can be represented in 21 chars. */
+ if (str) sprintf(str,"%lld",item->valueint);
+ }
+ else
+ {
+ if (p) str=ensure(p,64);
+ else str=(char*)cJSON_malloc(64); /* This is a nice tradeoff. */
+ if (str)
+ {
+ if (fabs(floor(d)-d)<=DBL_EPSILON && fabs(d)<1.0e60)sprintf(str,"%.0f",d);
+ else if (fabs(d)<1.0e-6 || fabs(d)>1.0e9) sprintf(str,"%e",d);
+ else sprintf(str,"%f",d);
+ }
+ }
+ return str;
+}
+
+static unsigned parse_hex4(const char *str)
+{
+ unsigned h=0;
+ if (*str>='0' && *str<='9') h+=(*str)-'0'; else if (*str>='A' && *str<='F') h+=10+(*str)-'A'; else if (*str>='a' && *str<='f') h+=10+(*str)-'a'; else return 0;
+ h=h<<4;str++;
+ if (*str>='0' && *str<='9') h+=(*str)-'0'; else if (*str>='A' && *str<='F') h+=10+(*str)-'A'; else if (*str>='a' && *str<='f') h+=10+(*str)-'a'; else return 0;
+ h=h<<4;str++;
+ if (*str>='0' && *str<='9') h+=(*str)-'0'; else if (*str>='A' && *str<='F') h+=10+(*str)-'A'; else if (*str>='a' && *str<='f') h+=10+(*str)-'a'; else return 0;
+ h=h<<4;str++;
+ if (*str>='0' && *str<='9') h+=(*str)-'0'; else if (*str>='A' && *str<='F') h+=10+(*str)-'A'; else if (*str>='a' && *str<='f') h+=10+(*str)-'a'; else return 0;
+ return h;
+}
+
+/* Parse the input text into an unescaped cstring, and populate item. */
+static const unsigned char firstByteMark[7] = { 0x00, 0x00, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC };
+static const char *parse_string(cJSON *item,const char *str)
+{
+ const char *ptr=str+1;char *ptr2;char *out;int len=0;unsigned uc,uc2;
+ if (*str!='\"') {ep=str;return 0;} /* not a string! */
+
+ while (*ptr!='\"' && *ptr && ++len) if (*ptr++ == '\\') ptr++; /* Skip escaped quotes. */
+
+ out=(char*)cJSON_malloc(len+1); /* This is how long we need for the string, roughly. */
+ if (!out) return 0;
+
+ ptr=str+1;ptr2=out;
+ while (*ptr!='\"' && *ptr)
+ {
+ if (*ptr!='\\') *ptr2++=*ptr++;
+ else
+ {
+ ptr++;
+ switch (*ptr)
+ {
+ case 'b': *ptr2++='\b'; break;
+ case 'f': *ptr2++='\f'; break;
+ case 'n': *ptr2++='\n'; break;
+ case 'r': *ptr2++='\r'; break;
+ case 't': *ptr2++='\t'; break;
+ case 'u': /* transcode utf16 to utf8. */
+ uc=parse_hex4(ptr+1);ptr+=4; /* get the unicode char. */
+
+ if ((uc>=0xDC00 && uc<=0xDFFF) || uc==0) break; /* check for invalid. */
+
+ if (uc>=0xD800 && uc<=0xDBFF) /* UTF16 surrogate pairs. */
+ {
+ if (ptr[1]!='\\' || ptr[2]!='u') break; /* missing second-half of surrogate. */
+ uc2=parse_hex4(ptr+3);ptr+=6;
+ if (uc2<0xDC00 || uc2>0xDFFF) break; /* invalid second-half of surrogate. */
+ uc=0x10000 + (((uc&0x3FF)<<10) | (uc2&0x3FF));
+ }
+
+ len=4;if (uc<0x80) len=1;else if (uc<0x800) len=2;else if (uc<0x10000) len=3; ptr2+=len;
+
+ switch (len) {
+ case 4: *--ptr2 =((uc | 0x80) & 0xBF); uc >>= 6;
+ case 3: *--ptr2 =((uc | 0x80) & 0xBF); uc >>= 6;
+ case 2: *--ptr2 =((uc | 0x80) & 0xBF); uc >>= 6;
+ case 1: *--ptr2 =(uc | firstByteMark[len]);
+ }
+ ptr2+=len;
+ break;
+ default: *ptr2++=*ptr; break;
+ }
+ ptr++;
+ }
+ }
+ *ptr2=0;
+ if (*ptr=='\"') ptr++;
+ item->valuestring=out;
+ item->type=cJSON_String;
+ return ptr;
+}
+
+/* Render the cstring provided to an escaped version that can be printed. */
+static char *print_string_ptr(const char *str,printbuffer *p)
+{
+ const char *ptr;char *ptr2,*out;int len=0,flag=0;unsigned char token;
+
+ for (ptr=str;*ptr;ptr++) flag|=((*ptr>0 && *ptr<32)||(*ptr=='\"')||(*ptr=='\\'))?1:0;
+ if (!flag)
+ {
+ len=ptr-str;
+ if (p) out=ensure(p,len+3);
+ else out=(char*)cJSON_malloc(len+3);
+ if (!out) return 0;
+ ptr2=out;*ptr2++='\"';
+ strcpy(ptr2,str);
+ ptr2[len]='\"';
+ ptr2[len+1]=0;
+ return out;
+ }
+
+ if (!str)
+ {
+ if (p) out=ensure(p,3);
+ else out=(char*)cJSON_malloc(3);
+ if (!out) return 0;
+ strcpy(out,"\"\"");
+ return out;
+ }
+ ptr=str;while ((token=*ptr) && ++len) {if (strchr("\"\\\b\f\n\r\t",token)) len++; else if (token<32) len+=5;ptr++;}
+
+ if (p) out=ensure(p,len+3);
+ else out=(char*)cJSON_malloc(len+3);
+ if (!out) return 0;
+
+ ptr2=out;ptr=str;
+ *ptr2++='\"';
+ while (*ptr)
+ {
+ if ((unsigned char)*ptr>31 && *ptr!='\"' && *ptr!='\\') *ptr2++=*ptr++;
+ else
+ {
+ *ptr2++='\\';
+ switch (token=*ptr++)
+ {
+ case '\\': *ptr2++='\\'; break;
+ case '\"': *ptr2++='\"'; break;
+ case '\b': *ptr2++='b'; break;
+ case '\f': *ptr2++='f'; break;
+ case '\n': *ptr2++='n'; break;
+ case '\r': *ptr2++='r'; break;
+ case '\t': *ptr2++='t'; break;
+ default: sprintf(ptr2,"u%04x",token);ptr2+=5; break; /* escape and print */
+ }
+ }
+ }
+ *ptr2++='\"';*ptr2++=0;
+ return out;
+}
+/* Invote print_string_ptr (which is useful) on an item. */
+static char *print_string(cJSON *item,printbuffer *p) {return print_string_ptr(item->valuestring,p);}
+
+/* Predeclare these prototypes. */
+static const char *parse_value(cJSON *item,const char *value);
+static char *print_value(cJSON *item,int depth,int fmt,printbuffer *p);
+static const char *parse_array(cJSON *item,const char *value);
+static char *print_array(cJSON *item,int depth,int fmt,printbuffer *p);
+static const char *parse_object(cJSON *item,const char *value);
+static char *print_object(cJSON *item,int depth,int fmt,printbuffer *p);
+
+/* Utility to jump whitespace and cr/lf */
+static const char *skip(const char *in) {while (in && *in && (unsigned char)*in<=32) in++; return in;}
+
+/* Parse an object - create a new root, and populate. */
+cJSON *cJSON_ParseWithOpts(const char *value,const char **return_parse_end,int require_null_terminated)
+{
+ const char *end=0;
+ cJSON *c=cJSON_New_Item();
+ ep=0;
+ if (!c) return 0; /* memory fail */
+
+ end=parse_value(c,skip(value));
+ if (!end) {cJSON_Delete(c);return 0;} /* parse failure. ep is set. */
+
+ /* if we require null-terminated JSON without appended garbage, skip and then check for a null terminator */
+ if (require_null_terminated) {end=skip(end);if (*end) {cJSON_Delete(c);ep=end;return 0;}}
+ if (return_parse_end) *return_parse_end=end;
+ return c;
+}
+/* Default options for cJSON_Parse */
+cJSON *cJSON_Parse(const char *value) {return cJSON_ParseWithOpts(value,0,0);}
+
+/* Render a cJSON item/entity/structure to text. */
+char *cJSON_Print(cJSON *item) {return print_value(item,0,1,0);}
+char *cJSON_PrintUnformatted(cJSON *item) {return print_value(item,0,0,0);}
+
+char *cJSON_PrintBuffered(cJSON *item,int prebuffer,int fmt)
+{
+ printbuffer p;
+ p.buffer=(char*)cJSON_malloc(prebuffer);
+ p.length=prebuffer;
+ p.offset=0;
+ return print_value(item,0,fmt,&p);
+ return p.buffer;
+}
+
+
+/* Parser core - when encountering text, process appropriately. */
+static const char *parse_value(cJSON *item,const char *value)
+{
+ if (!value) return 0; /* Fail on null. */
+ if (!strncmp(value,"null",4)) { item->type=cJSON_NULL; return value+4; }
+ if (!strncmp(value,"false",5)) { item->type=cJSON_False; return value+5; }
+ if (!strncmp(value,"true",4)) { item->type=cJSON_True; item->valueint=1; return value+4; }
+ if (*value=='\"') { return parse_string(item,value); }
+ if (*value=='-' || (*value>='0' && *value<='9')) { return parse_number(item,value); }
+ if (*value=='[') { return parse_array(item,value); }
+ if (*value=='{') { return parse_object(item,value); }
+
+ ep=value;return 0; /* failure. */
+}
+
+/* Render a value to text. */
+static char *print_value(cJSON *item,int depth,int fmt,printbuffer *p)
+{
+ char *out=0;
+ if (!item) return 0;
+ if (p)
+ {
+ switch ((item->type)&255)
+ {
+ case cJSON_NULL: {out=ensure(p,5); if (out) strcpy(out,"null"); break;}
+ case cJSON_False: {out=ensure(p,6); if (out) strcpy(out,"false"); break;}
+ case cJSON_True: {out=ensure(p,5); if (out) strcpy(out,"true"); break;}
+ case cJSON_Number: out=print_number(item,p);break;
+ case cJSON_String: out=print_string(item,p);break;
+ case cJSON_Array: out=print_array(item,depth,fmt,p);break;
+ case cJSON_Object: out=print_object(item,depth,fmt,p);break;
+ }
+ }
+ else
+ {
+ switch ((item->type)&255)
+ {
+ case cJSON_NULL: out=cJSON_strdup("null"); break;
+ case cJSON_False: out=cJSON_strdup("false");break;
+ case cJSON_True: out=cJSON_strdup("true"); break;
+ case cJSON_Number: out=print_number(item,0);break;
+ case cJSON_String: out=print_string(item,0);break;
+ case cJSON_Array: out=print_array(item,depth,fmt,0);break;
+ case cJSON_Object: out=print_object(item,depth,fmt,0);break;
+ }
+ }
+ return out;
+}
+
+/* Build an array from input text. */
+static const char *parse_array(cJSON *item,const char *value)
+{
+ cJSON *child;
+ if (*value!='[') {ep=value;return 0;} /* not an array! */
+
+ item->type=cJSON_Array;
+ value=skip(value+1);
+ if (*value==']') return value+1; /* empty array. */
+
+ item->child=child=cJSON_New_Item();
+ if (!item->child) return 0; /* memory fail */
+ value=skip(parse_value(child,skip(value))); /* skip any spacing, get the value. */
+ if (!value) return 0;
+
+ while (*value==',')
+ {
+ cJSON *new_item;
+ if (!(new_item=cJSON_New_Item())) return 0; /* memory fail */
+ child->next=new_item;new_item->prev=child;child=new_item;
+ value=skip(parse_value(child,skip(value+1)));
+ if (!value) return 0; /* memory fail */
+ }
+
+ if (*value==']') return value+1; /* end of array */
+ ep=value;return 0; /* malformed. */
+}
+
+/* Render an array to text */
+static char *print_array(cJSON *item,int depth,int fmt,printbuffer *p)
+{
+ char **entries;
+ char *out=0,*ptr,*ret;int len=5;
+ cJSON *child=item->child;
+ int numentries=0,i=0,fail=0;
+ size_t tmplen=0;
+
+ /* How many entries in the array? */
+ while (child) numentries++,child=child->next;
+ /* Explicitly handle numentries==0 */
+ if (!numentries)
+ {
+ if (p) out=ensure(p,3);
+ else out=(char*)cJSON_malloc(3);
+ if (out) strcpy(out,"[]");
+ return out;
+ }
+
+ if (p)
+ {
+ /* Compose the output array. */
+ i=p->offset;
+ ptr=ensure(p,1);if (!ptr) return 0; *ptr='['; p->offset++;
+ child=item->child;
+ while (child && !fail)
+ {
+ print_value(child,depth+1,fmt,p);
+ p->offset=update(p);
+ if (child->next) {len=fmt?2:1;ptr=ensure(p,len+1);if (!ptr) return 0;*ptr++=',';if(fmt)*ptr++=' ';*ptr=0;p->offset+=len;}
+ child=child->next;
+ }
+ ptr=ensure(p,2);if (!ptr) return 0; *ptr++=']';*ptr=0;
+ out=(p->buffer)+i;
+ }
+ else
+ {
+ /* Allocate an array to hold the values for each */
+ entries=(char**)cJSON_malloc(numentries*sizeof(char*));
+ if (!entries) return 0;
+ memset(entries,0,numentries*sizeof(char*));
+ /* Retrieve all the results: */
+ child=item->child;
+ while (child && !fail)
+ {
+ ret=print_value(child,depth+1,fmt,0);
+ entries[i++]=ret;
+ if (ret) len+=strlen(ret)+2+(fmt?1:0); else fail=1;
+ child=child->next;
+ }
+
+ /* If we didn't fail, try to malloc the output string */
+ if (!fail) out=(char*)cJSON_malloc(len);
+ /* If that fails, we fail. */
+ if (!out) fail=1;
+
+ /* Handle failure. */
+ if (fail)
+ {
+ for (i=0;itype=cJSON_Object;
+ value=skip(value+1);
+ if (*value=='}') return value+1; /* empty array. */
+
+ item->child=child=cJSON_New_Item();
+ if (!item->child) return 0;
+ value=skip(parse_string(child,skip(value)));
+ if (!value) return 0;
+ child->string=child->valuestring;child->valuestring=0;
+ if (*value!=':') {ep=value;return 0;} /* fail! */
+ value=skip(parse_value(child,skip(value+1))); /* skip any spacing, get the value. */
+ if (!value) return 0;
+
+ while (*value==',')
+ {
+ cJSON *new_item;
+ if (!(new_item=cJSON_New_Item())) return 0; /* memory fail */
+ child->next=new_item;new_item->prev=child;child=new_item;
+ value=skip(parse_string(child,skip(value+1)));
+ if (!value) return 0;
+ child->string=child->valuestring;child->valuestring=0;
+ if (*value!=':') {ep=value;return 0;} /* fail! */
+ value=skip(parse_value(child,skip(value+1))); /* skip any spacing, get the value. */
+ if (!value) return 0;
+ }
+
+ if (*value=='}') return value+1; /* end of array */
+ ep=value;return 0; /* malformed. */
+}
+
+/* Render an object to text. */
+static char *print_object(cJSON *item,int depth,int fmt,printbuffer *p)
+{
+ char **entries=0,**names=0;
+ char *out=0,*ptr,*ret,*str;int len=7,i=0,j;
+ cJSON *child=item->child;
+ int numentries=0,fail=0;
+ size_t tmplen=0;
+ /* Count the number of entries. */
+ while (child) numentries++,child=child->next;
+ /* Explicitly handle empty object case */
+ if (!numentries)
+ {
+ if (p) out=ensure(p,fmt?depth+4:3);
+ else out=(char*)cJSON_malloc(fmt?depth+4:3);
+ if (!out) return 0;
+ ptr=out;*ptr++='{';
+ if (fmt) {*ptr++='\n';for (i=0;ioffset;
+ len=fmt?2:1; ptr=ensure(p,len+1); if (!ptr) return 0;
+ *ptr++='{'; if (fmt) *ptr++='\n'; *ptr=0; p->offset+=len;
+ child=item->child;depth++;
+ while (child)
+ {
+ if (fmt)
+ {
+ ptr=ensure(p,depth); if (!ptr) return 0;
+ for (j=0;joffset+=depth;
+ }
+ print_string_ptr(child->string,p);
+ p->offset=update(p);
+
+ len=fmt?2:1;
+ ptr=ensure(p,len); if (!ptr) return 0;
+ *ptr++=':';if (fmt) *ptr++='\t';
+ p->offset+=len;
+
+ print_value(child,depth,fmt,p);
+ p->offset=update(p);
+
+ len=(fmt?1:0)+(child->next?1:0);
+ ptr=ensure(p,len+1); if (!ptr) return 0;
+ if (child->next) *ptr++=',';
+ if (fmt) *ptr++='\n';*ptr=0;
+ p->offset+=len;
+ child=child->next;
+ }
+ ptr=ensure(p,fmt?(depth+1):2); if (!ptr) return 0;
+ if (fmt) for (i=0;ibuffer)+i;
+ }
+ else
+ {
+ /* Allocate space for the names and the objects */
+ entries=(char**)cJSON_malloc(numentries*sizeof(char*));
+ if (!entries) return 0;
+ names=(char**)cJSON_malloc(numentries*sizeof(char*));
+ if (!names) {cJSON_free(entries);return 0;}
+ memset(entries,0,sizeof(char*)*numentries);
+ memset(names,0,sizeof(char*)*numentries);
+
+ /* Collect all the results into our arrays: */
+ child=item->child;depth++;if (fmt) len+=depth;
+ while (child)
+ {
+ names[i]=str=print_string_ptr(child->string,0);
+ entries[i++]=ret=print_value(child,depth,fmt,0);
+ if (str && ret) len+=strlen(ret)+strlen(str)+2+(fmt?2+depth:0); else fail=1;
+ child=child->next;
+ }
+
+ /* Try to allocate the output string */
+ if (!fail) out=(char*)cJSON_malloc(len);
+ if (!out) fail=1;
+
+ /* Handle failure */
+ if (fail)
+ {
+ for (i=0;ichild;int i=0;while(c)i++,c=c->next;return i;}
+cJSON *cJSON_GetArrayItem(cJSON *array,int item) {cJSON *c=array->child; while (c && item>0) item--,c=c->next; return c;}
+cJSON *cJSON_GetObjectItem(cJSON *object,const char *string) {cJSON *c=object->child; while (c && cJSON_strcasecmp(c->string,string)) c=c->next; return c;}
+
+/* Utility for array list handling. */
+static void suffix_object(cJSON *prev,cJSON *item) {prev->next=item;item->prev=prev;}
+/* Utility for handling references. */
+static cJSON *create_reference(cJSON *item) {cJSON *ref=cJSON_New_Item();if (!ref) return 0;memcpy(ref,item,sizeof(cJSON));ref->string=0;ref->type|=cJSON_IsReference;ref->next=ref->prev=0;return ref;}
+
+/* Add item to array/object. */
+void cJSON_AddItemToArray(cJSON *array, cJSON *item) {cJSON *c=array->child;if (!item) return; if (!c) {array->child=item;} else {while (c && c->next) c=c->next; suffix_object(c,item);}}
+void cJSON_AddItemToObject(cJSON *object,const char *string,cJSON *item) {if (!item) return; if (item->string) cJSON_free(item->string);item->string=cJSON_strdup(string);cJSON_AddItemToArray(object,item);}
+void cJSON_AddItemToObjectCS(cJSON *object,const char *string,cJSON *item) {if (!item) return; if (!(item->type&cJSON_StringIsConst) && item->string) cJSON_free(item->string);item->string=(char*)string;item->type|=cJSON_StringIsConst;cJSON_AddItemToArray(object,item);}
+void cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item) {cJSON_AddItemToArray(array,create_reference(item));}
+void cJSON_AddItemReferenceToObject(cJSON *object,const char *string,cJSON *item) {cJSON_AddItemToObject(object,string,create_reference(item));}
+
+cJSON *cJSON_DetachItemFromArray(cJSON *array,int which) {cJSON *c=array->child;while (c && which>0) c=c->next,which--;if (!c) return 0;
+ if (c->prev) c->prev->next=c->next;if (c->next) c->next->prev=c->prev;if (c==array->child) array->child=c->next;c->prev=c->next=0;return c;}
+void cJSON_DeleteItemFromArray(cJSON *array,int which) {cJSON_Delete(cJSON_DetachItemFromArray(array,which));}
+cJSON *cJSON_DetachItemFromObject(cJSON *object,const char *string) {int i=0;cJSON *c=object->child;while (c && cJSON_strcasecmp(c->string,string)) i++,c=c->next;if (c) return cJSON_DetachItemFromArray(object,i);return 0;}
+void cJSON_DeleteItemFromObject(cJSON *object,const char *string) {cJSON_Delete(cJSON_DetachItemFromObject(object,string));}
+
+/* Replace array/object items with new ones. */
+void cJSON_InsertItemInArray(cJSON *array,int which,cJSON *newitem) {cJSON *c=array->child;while (c && which>0) c=c->next,which--;if (!c) {cJSON_AddItemToArray(array,newitem);return;}
+ newitem->next=c;newitem->prev=c->prev;c->prev=newitem;if (c==array->child) array->child=newitem; else newitem->prev->next=newitem;}
+void cJSON_ReplaceItemInArray(cJSON *array,int which,cJSON *newitem) {cJSON *c=array->child;while (c && which>0) c=c->next,which--;if (!c) return;
+ newitem->next=c->next;newitem->prev=c->prev;if (newitem->next) newitem->next->prev=newitem;
+ if (c==array->child) array->child=newitem; else newitem->prev->next=newitem;c->next=c->prev=0;cJSON_Delete(c);}
+void cJSON_ReplaceItemInObject(cJSON *object,const char *string,cJSON *newitem){int i=0;cJSON *c=object->child;while(c && cJSON_strcasecmp(c->string,string))i++,c=c->next;if(c){newitem->string=cJSON_strdup(string);cJSON_ReplaceItemInArray(object,i,newitem);}}
+
+/* Create basic types: */
+cJSON *cJSON_CreateNull(void) {cJSON *item=cJSON_New_Item();if(item)item->type=cJSON_NULL;return item;}
+cJSON *cJSON_CreateTrue(void) {cJSON *item=cJSON_New_Item();if(item)item->type=cJSON_True;return item;}
+cJSON *cJSON_CreateFalse(void) {cJSON *item=cJSON_New_Item();if(item)item->type=cJSON_False;return item;}
+cJSON *cJSON_CreateBool(int b) {cJSON *item=cJSON_New_Item();if(item)item->type=b?cJSON_True:cJSON_False;return item;}
+cJSON *cJSON_CreateNumber(double num) {cJSON *item=cJSON_New_Item();if(item){item->type=cJSON_Number;item->valuedouble=num;item->valueint=(long long)num;}return item;}
+cJSON *cJSON_CreateString(const char *string) {cJSON *item=cJSON_New_Item();if(item){item->type=cJSON_String;item->valuestring=cJSON_strdup(string);}return item;}
+cJSON *cJSON_CreateArray(void) {cJSON *item=cJSON_New_Item();if(item)item->type=cJSON_Array;return item;}
+cJSON *cJSON_CreateObject(void) {cJSON *item=cJSON_New_Item();if(item)item->type=cJSON_Object;return item;}
+
+/* Create Arrays: */
+cJSON *cJSON_CreateIntArray(const int *numbers,int count) {int i;cJSON *n=0,*p=0,*a=cJSON_CreateArray();for(i=0;a && ichild=n;else suffix_object(p,n);p=n;}return a;}
+cJSON *cJSON_CreateFloatArray(const float *numbers,int count) {int i;cJSON *n=0,*p=0,*a=cJSON_CreateArray();for(i=0;a && ichild=n;else suffix_object(p,n);p=n;}return a;}
+cJSON *cJSON_CreateDoubleArray(const double *numbers,int count) {int i;cJSON *n=0,*p=0,*a=cJSON_CreateArray();for(i=0;a && ichild=n;else suffix_object(p,n);p=n;}return a;}
+cJSON *cJSON_CreateStringArray(const char **strings,int count) {int i;cJSON *n=0,*p=0,*a=cJSON_CreateArray();for(i=0;a && ichild=n;else suffix_object(p,n);p=n;}return a;}
+
+/* Duplication */
+cJSON *cJSON_Duplicate(cJSON *item,int recurse)
+{
+ cJSON *newitem,*cptr,*nptr=0,*newchild;
+ /* Bail on bad ptr */
+ if (!item) return 0;
+ /* Create new item */
+ newitem=cJSON_New_Item();
+ if (!newitem) return 0;
+ /* Copy over all vars */
+ newitem->type=item->type&(~cJSON_IsReference),newitem->valueint=item->valueint,newitem->valuedouble=item->valuedouble;
+ if (item->valuestring) {newitem->valuestring=cJSON_strdup(item->valuestring); if (!newitem->valuestring) {cJSON_Delete(newitem);return 0;}}
+ if (item->string) {newitem->string=cJSON_strdup(item->string); if (!newitem->string) {cJSON_Delete(newitem);return 0;}}
+ /* If non-recursive, then we're done! */
+ if (!recurse) return newitem;
+ /* Walk the ->next chain for the child. */
+ cptr=item->child;
+ while (cptr)
+ {
+ newchild=cJSON_Duplicate(cptr,1); /* Duplicate (with recurse) each item in the ->next chain */
+ if (!newchild) {cJSON_Delete(newitem);return 0;}
+ if (nptr) {nptr->next=newchild,newchild->prev=nptr;nptr=newchild;} /* If newitem->child already set, then crosswire ->prev and ->next and move on */
+ else {newitem->child=newchild;nptr=newchild;} /* Set newitem->child and move to it */
+ cptr=cptr->next;
+ }
+ return newitem;
+}
+
+void cJSON_Minify(char *json)
+{
+ char *into=json;
+ while (*json)
+ {
+ if (*json==' ') json++;
+ else if (*json=='\t') json++; /* Whitespace characters. */
+ else if (*json=='\r') json++;
+ else if (*json=='\n') json++;
+ else if (*json=='/' && json[1]=='/') while (*json && *json!='\n') json++; /* double-slash comments, to end of line. */
+ else if (*json=='/' && json[1]=='*') {while (*json && !(*json=='*' && json[1]=='/')) json++;json+=2;} /* multiline comments. */
+ else if (*json=='\"'){*into++=*json++;while (*json && *json!='\"'){if (*json=='\\') *into++=*json++;*into++=*json++;}*into++=*json++;} /* string literals, which are \" sensitive. */
+ else *into++=*json++; /* All other characters. */
+ }
+ *into=0; /* and null-terminate. */
+}
diff --git a/PermissionManager/app/src/main/cpp/cJSON.h b/PermissionManager/app/src/main/cpp/cJSON.h
new file mode 100644
index 00000000..f61a9af0
--- /dev/null
+++ b/PermissionManager/app/src/main/cpp/cJSON.h
@@ -0,0 +1,149 @@
+/*
+ Copyright (c) 2009 Dave Gamble
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+#ifndef cJSON__h
+#define cJSON__h
+#include
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* cJSON Types: */
+#define cJSON_False 0
+#define cJSON_True 1
+#define cJSON_NULL 2
+#define cJSON_Number 3
+#define cJSON_String 4
+#define cJSON_Array 5
+#define cJSON_Object 6
+
+#define cJSON_IsReference 256
+#define cJSON_StringIsConst 512
+
+/* The cJSON structure: */
+typedef struct cJSON {
+ struct cJSON *next,*prev; /* next/prev allow you to walk array/object chains. Alternatively, use GetArraySize/GetArrayItem/GetObjectItem */
+ struct cJSON *child; /* An array or object item will have a child pointer pointing to a chain of the items in the array/object. */
+
+ int type; /* The type of the item, as above. */
+
+ char *valuestring; /* The item's string, if type==cJSON_String */
+ long long valueint; /* The item's number, if type==cJSON_Number */
+ double valuedouble; /* The item's number, if type==cJSON_Number */
+
+ char *string; /* The item's name string, if this item is the child of, or is in the list of subitems of an object. */
+} cJSON;
+
+typedef struct cJSON_Hooks {
+ void *(*malloc_fn)(size_t sz);
+ void (*free_fn)(void *ptr);
+} cJSON_Hooks;
+
+/* Supply malloc, realloc and free functions to cJSON */
+extern void cJSON_InitHooks(cJSON_Hooks* hooks);
+
+
+/* Supply a block of JSON, and this returns a cJSON object you can interrogate. Call cJSON_Delete when finished. */
+extern cJSON *cJSON_Parse(const char *value);
+/* Render a cJSON entity to text for transfer/storage. Free the char* when finished. */
+extern char *cJSON_Print(cJSON *item);
+/* Render a cJSON entity to text for transfer/storage without any formatting. Free the char* when finished. */
+extern char *cJSON_PrintUnformatted(cJSON *item);
+/* Render a cJSON entity to text using a buffered strategy. prebuffer is a guess at the final size. guessing well reduces reallocation. fmt=0 gives unformatted, =1 gives formatted */
+extern char *cJSON_PrintBuffered(cJSON *item,int prebuffer,int fmt);
+/* Delete a cJSON entity and all subentities. */
+extern void cJSON_Delete(cJSON *c);
+
+/* Returns the number of items in an array (or object). */
+extern int cJSON_GetArraySize(cJSON *array);
+/* Retrieve item number "item" from array "array". Returns NULL if unsuccessful. */
+extern cJSON *cJSON_GetArrayItem(cJSON *array,int item);
+/* Get item "string" from object. Case insensitive. */
+extern cJSON *cJSON_GetObjectItem(cJSON *object,const char *string);
+
+/* For analysing failed parses. This returns a pointer to the parse error. You'll probably need to look a few chars back to make sense of it. Defined when cJSON_Parse() returns 0. 0 when cJSON_Parse() succeeds. */
+extern const char *cJSON_GetErrorPtr(void);
+
+/* These calls create a cJSON item of the appropriate type. */
+extern cJSON *cJSON_CreateNull(void);
+extern cJSON *cJSON_CreateTrue(void);
+extern cJSON *cJSON_CreateFalse(void);
+extern cJSON *cJSON_CreateBool(int b);
+extern cJSON *cJSON_CreateNumber(double num);
+extern cJSON *cJSON_CreateString(const char *string);
+extern cJSON *cJSON_CreateArray(void);
+extern cJSON *cJSON_CreateObject(void);
+
+/* These utilities create an Array of count items. */
+extern cJSON *cJSON_CreateIntArray(const int *numbers,int count);
+extern cJSON *cJSON_CreateFloatArray(const float *numbers,int count);
+extern cJSON *cJSON_CreateDoubleArray(const double *numbers,int count);
+extern cJSON *cJSON_CreateStringArray(const char **strings,int count);
+
+/* Append item to the specified array/object. */
+extern void cJSON_AddItemToArray(cJSON *array, cJSON *item);
+extern void cJSON_AddItemToObject(cJSON *object,const char *string,cJSON *item);
+extern void cJSON_AddItemToObjectCS(cJSON *object,const char *string,cJSON *item); /* Use this when string is definitely const (i.e. a literal, or as good as), and will definitely survive the cJSON object */
+/* Append reference to item to the specified array/object. Use this when you want to add an existing cJSON to a new cJSON, but don't want to corrupt your existing cJSON. */
+extern void cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item);
+extern void cJSON_AddItemReferenceToObject(cJSON *object,const char *string,cJSON *item);
+
+/* Remove/Detatch items from Arrays/Objects. */
+extern cJSON *cJSON_DetachItemFromArray(cJSON *array,int which);
+extern void cJSON_DeleteItemFromArray(cJSON *array,int which);
+extern cJSON *cJSON_DetachItemFromObject(cJSON *object,const char *string);
+extern void cJSON_DeleteItemFromObject(cJSON *object,const char *string);
+
+/* Update array items. */
+extern void cJSON_InsertItemInArray(cJSON *array,int which,cJSON *newitem); /* Shifts pre-existing items to the right. */
+extern void cJSON_ReplaceItemInArray(cJSON *array,int which,cJSON *newitem);
+extern void cJSON_ReplaceItemInObject(cJSON *object,const char *string,cJSON *newitem);
+
+/* Duplicate a cJSON item */
+extern cJSON *cJSON_Duplicate(cJSON *item,int recurse);
+/* Duplicate will create a new, identical cJSON item to the one you pass, in new memory that will
+need to be released. With recurse!=0, it will duplicate any children connected to the item.
+The item->next and ->prev pointers are always zero on return from Duplicate. */
+
+/* ParseWithOpts allows you to require (and check) that the JSON is null terminated, and to retrieve the pointer to the final byte parsed. */
+extern cJSON *cJSON_ParseWithOpts(const char *value,const char **return_parse_end,int require_null_terminated);
+
+extern void cJSON_Minify(char *json);
+
+/* Macros for creating things quickly. */
+#define cJSON_AddNullToObject(object,name) cJSON_AddItemToObject(object, name, cJSON_CreateNull())
+#define cJSON_AddTrueToObject(object,name) cJSON_AddItemToObject(object, name, cJSON_CreateTrue())
+#define cJSON_AddFalseToObject(object,name) cJSON_AddItemToObject(object, name, cJSON_CreateFalse())
+#define cJSON_AddBoolToObject(object,name,b) cJSON_AddItemToObject(object, name, cJSON_CreateBool(b))
+#define cJSON_AddNumberToObject(object,name,n) cJSON_AddItemToObject(object, name, cJSON_CreateNumber(n))
+#define cJSON_AddStringToObject(object,name,s) cJSON_AddItemToObject(object, name, cJSON_CreateString(s))
+
+/* When assigning an integer value, it needs to be propagated to valuedouble too. */
+#define cJSON_SetIntValue(object,val) ((object)?(object)->valueint=(object)->valuedouble=(val):(val))
+#define cJSON_SetNumberValue(object,val) ((object)?(object)->valueint=(object)->valuedouble=(val):(val))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/PermissionManager/app/src/main/cpp/root.cpp b/PermissionManager/app/src/main/cpp/root.cpp
new file mode 100644
index 00000000..ed0da3b5
--- /dev/null
+++ b/PermissionManager/app/src/main/cpp/root.cpp
@@ -0,0 +1,385 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../../../../../testRoot/jni/kernel_root_kit/kernel_root_kit_umbrella.h"
+#include "../../../../../testRoot/jni/testRoot.h"
+#include "urlEncodeUtils.h"
+#include "cJSON.h"
+using namespace std;
+
+std::string g_last_su_full_path;
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_testRoot(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey) {
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ std::string result;
+ kernel_root::fork_pipe_info finfo;
+ ssize_t err = 0;
+ if(fork_pipe_child_process(finfo)) {
+ err = kernel_root::get_root(strRootKey.c_str());
+ result = "getRoot:";
+ result += std::to_string(err);
+ result += "\n\n";
+ if(err == 0) {
+ result += get_capability_info();
+ result += "\n\n";
+ }
+ write_errcode_from_child(finfo, err);
+ write_string_from_child(finfo, result);
+ _exit(0);
+ return 0;
+ }
+ err = 0;
+ if(!wait_fork_child_process(finfo)) {
+ err = -1120001;
+ } else {
+ if(!read_errcode_from_child(finfo, err)) {
+ err = -1120002;
+ } else if(!read_string_from_child(finfo, result)) {
+ err = -1120003;
+ }
+ }
+ return env->NewStringUTF(result.c_str());
+}
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_runRootCmd(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey,
+ jstring cmd) {
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ str1 = env->GetStringUTFChars(cmd, 0);
+ string strCmd= str1;
+ env->ReleaseStringUTFChars(cmd, str1);
+
+
+ ssize_t err;
+ string result = kernel_root::run_root_cmd(strRootKey.c_str(), strCmd.c_str(), err);
+ stringstream sstr;
+ sstr << "runRootCmd err:" << err << ", result:" << result;
+ return env->NewStringUTF(sstr.str().c_str());
+}
+
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_runInit64ProcessCmd(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey,
+ jstring cmd) {
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ str1 = env->GetStringUTFChars(cmd, 0);
+ string strCmd= str1;
+ env->ReleaseStringUTFChars(cmd, str1);
+
+
+ ssize_t err;
+ string result = kernel_root::safe_run_init64_cmd_wrapper(strRootKey.c_str(), strCmd.c_str(), err);
+
+ stringstream sstr;
+ sstr << "runInit64Cmd err:" << err << ", result:" << result;
+ return env->NewStringUTF(sstr.str().c_str());
+}
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_installSu(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey,
+ jstring basePath) {
+
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ str1 = env->GetStringUTFChars(basePath, 0);
+ string strBasePath= str1;
+ env->ReleaseStringUTFChars(basePath, str1);
+
+ stringstream sstr;
+ //安装su工具套件
+ ssize_t err;
+ std::string su_hide_full_path = kernel_root::safe_install_su(strRootKey.c_str(), strBasePath.c_str(), err);
+ sstr << "install su err:" << err<<", su_hide_full_path:" << su_hide_full_path << std::endl;
+ g_last_su_full_path = su_hide_full_path;
+ if (err == 0) {
+ sstr << "installSu done."<< std::endl;
+ }
+ return env->NewStringUTF(sstr.str().c_str());
+}
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_getLastInstallSuFullPath(
+ JNIEnv* env,
+ jobject /* this */) {
+ return env->NewStringUTF(g_last_su_full_path.c_str());
+}
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_uninstallSu(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey,
+ jstring basePath) {
+
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ str1 = env->GetStringUTFChars(basePath, 0);
+ string strBasePath= str1;
+ env->ReleaseStringUTFChars(basePath, str1);
+
+ stringstream sstr;
+
+ ssize_t err = kernel_root::safe_uninstall_su(strRootKey.c_str(), strBasePath.c_str());
+ sstr << "uninstallSu err:" << err << std::endl;
+ if (err != 0) {
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+ g_last_su_full_path.clear();
+ sstr << "uninstallSu done.";
+ return env->NewStringUTF(sstr.str().c_str());
+}
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_autoSuEnvInject(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey,
+ jstring targetProcessCmdline) {
+
+ if(g_last_su_full_path.empty()) {
+ return env->NewStringUTF("【错误】请先安装部署su");
+ }
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ str1 = env->GetStringUTFChars(targetProcessCmdline, 0);
+ string strTargetProcessCmdline = str1;
+ env->ReleaseStringUTFChars(targetProcessCmdline, str1);
+
+ stringstream sstr;
+
+ //杀光所有历史进程
+ std::set out;
+ ssize_t err = kernel_root::safe_find_all_cmdline_process(strRootKey.c_str(), strTargetProcessCmdline.c_str(), out);
+ sstr << "find_all_cmdline_process err:"<< err<<", cnt:"<NewStringUTF(sstr.str().c_str());
+ }
+ std::string kill_cmd;
+ for (pid_t t : out) {
+ err = kernel_root::safe_kill_process(strRootKey.c_str(), t);
+ sstr << "kill_ret err:"<< err << std::endl;
+ if (err != 0) {
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+ }
+ pid_t pid;
+ err = kernel_root::safe_wait_and_find_cmdline_process(strRootKey.c_str(), strTargetProcessCmdline.c_str(), 60*1000, pid);
+
+ std::string folder_path = g_last_su_full_path;
+ int n = folder_path.find_last_of("/");
+ if(n != -1) {
+ folder_path = folder_path.substr(0,n);
+ }
+ sstr << "autoSuEnvInject("<< err<<", " << folder_path <<")" << std::endl;
+ if (err != 0) {
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+ err = kernel_root::safe_inject_process_env64_PATH_wrapper(strRootKey.c_str(), pid, folder_path.c_str());
+ sstr << "autoSuEnvInject ret val:" << err << std::endl;
+ if (err != 0) {
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+ sstr << "autoSuEnvInject done.";
+ return env->NewStringUTF(sstr.str().c_str());
+}
+
+
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_getAllCmdlineProcess(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey) {
+ std::stringstream ss;
+
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ std::string strRootKey = str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ std::map pid_map;
+ ssize_t err = kernel_root::safe_get_all_cmdline_process(strRootKey.c_str(), pid_map);
+ if(err != 0) {
+ ss << "get_all_cmdline_process err:"<< err<< std::endl;
+ return env->NewStringUTF(ss.str().c_str());
+ }
+ cJSON *root = cJSON_CreateArray();
+ for (auto iter = pid_map.begin(); iter != pid_map.end(); iter++ ) {
+ cJSON *item = cJSON_CreateObject();
+ size_t len = iter->second.length();
+ size_t max_encoded_len = 3 * len + 1;
+ shared_ptr spData(new (std::nothrow) char[max_encoded_len], std::default_delete());
+ memset(spData.get(), 0, max_encoded_len);
+ url_encode(const_cast(iter->second.c_str()), spData.get());
+ cJSON_AddNumberToObject(item, "pid", iter->first);
+ cJSON_AddStringToObject(item, "name", spData.get());
+ cJSON_AddItemToArray(root, item);
+ }
+ ss << cJSON_Print(root);
+ cJSON_Delete(root);
+ return env->NewStringUTF(ss.str().c_str());
+}
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_parasitePrecheckApp(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey,
+ jstring targetProcessCmdline) {
+
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ str1 = env->GetStringUTFChars(targetProcessCmdline, 0);
+ string strTargetProcessCmdline = str1;
+ env->ReleaseStringUTFChars(targetProcessCmdline, str1);
+
+ stringstream sstr;
+ std::set test_pid;
+ ssize_t err = kernel_root::safe_find_all_cmdline_process(strRootKey.c_str(), strTargetProcessCmdline.c_str(), test_pid);
+ if (err != 0) {
+ sstr << "find_all_cmdline_process err:"<< err<<", cnt:"<< test_pid.size() << std::endl;
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+ if (test_pid.size() == 0) {
+ sstr << "目标进程不存在" << std::endl;
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+
+ std::map so_path_list;
+ err = kernel_root::safe_parasite_precheck_app(strRootKey.c_str(), strTargetProcessCmdline.c_str(), so_path_list);
+ if (err) {
+ sstr << "parasite_precheck_app ret val:" << err << std::endl;
+ if(err == -9904) {
+ sstr << "此目标APP为32位应用,无法寄生" << err << std::endl;
+ }
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+
+ if (!so_path_list.size()) {
+ sstr << "无法检测到目标APP的JNI环境,目标APP暂不可被寄生;您可重新运行目标APP后重试;或将APP进行手动加固(加壳),因为加固(加壳)APP后,APP会被产生JNI环境,方可寄生!" << std::endl;
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+
+ cJSON *root = cJSON_CreateArray();
+ for (auto iter = so_path_list.begin(); iter != so_path_list.end(); iter++) {
+ cJSON *item = cJSON_CreateObject();
+ size_t len = iter->first.length();
+ size_t max_encoded_len = 3 * len + 1;
+ std::shared_ptr spData(new (std::nothrow) char[max_encoded_len], std::default_delete());
+ memset(spData.get(), 0, max_encoded_len);
+ url_encode(const_cast(iter->first.c_str()), spData.get());
+ cJSON_AddStringToObject(item, "name", spData.get());
+ cJSON_AddNumberToObject(item, "status", iter->second);
+ cJSON_AddItemToArray(root, item);
+ }
+ sstr << cJSON_Print(root);
+ cJSON_Delete(root);
+ return env->NewStringUTF(sstr.str().c_str());
+
+}
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_parasiteImplantApp(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey,
+ jstring targetProcessCmdline,
+ jstring targetSoFullPath) {
+
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ str1 = env->GetStringUTFChars(targetProcessCmdline, 0);
+ string strTargetProcessCmdline = str1;
+ env->ReleaseStringUTFChars(targetProcessCmdline, str1);
+
+ str1 = env->GetStringUTFChars(targetSoFullPath, 0);
+ string strTargetSoFullPath = str1;
+ env->ReleaseStringUTFChars(targetSoFullPath, str1);
+
+ stringstream sstr;
+ ssize_t err = kernel_root::safe_parasite_implant_app(strRootKey.c_str(), strTargetProcessCmdline.c_str(), strTargetSoFullPath.c_str());
+ if (err != 0) {
+ sstr << "parasite_implant_app err:"<< err << std::endl;
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+ sstr << "parasiteImplantApp done.";
+ return env->NewStringUTF(sstr.str().c_str());
+
+}
+
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_linux_permissionmanager_MainActivity_parasiteImplantSuEnv(
+ JNIEnv* env,
+ jobject /* this */,
+ jstring rootKey,
+ jstring targetProcessCmdline,
+ jstring targetSoFullPath) {
+ if(g_last_su_full_path.empty()) {
+ return env->NewStringUTF("【错误】请先安装部署su");
+ }
+
+ const char *str1 = env->GetStringUTFChars(rootKey, 0);
+ string strRootKey= str1;
+ env->ReleaseStringUTFChars(rootKey, str1);
+
+ str1 = env->GetStringUTFChars(targetProcessCmdline, 0);
+ string strTargetProcessCmdline = str1;
+ env->ReleaseStringUTFChars(targetProcessCmdline, str1);
+
+ str1 = env->GetStringUTFChars(targetSoFullPath, 0);
+ string strTargetSoFullPath = str1;
+ env->ReleaseStringUTFChars(targetSoFullPath, str1);
+
+ std::string folder = g_last_su_full_path;
+ int n = folder.find_last_of("/");
+ folder = folder.substr(0, n);
+
+ stringstream sstr;
+ ssize_t err = kernel_root::safe_parasite_implant_su_env(strRootKey.c_str(), strTargetProcessCmdline.c_str(), strTargetSoFullPath.c_str(), folder);
+ if (err != 0) {
+ sstr << "parasite_implant_su_env err:"<< err << std::endl;
+ return env->NewStringUTF(sstr.str().c_str());
+ }
+ sstr << "parasiteImplantSuEnv done.";
+ return env->NewStringUTF(sstr.str().c_str());
+
+}
+
diff --git a/PermissionManager/app/src/main/cpp/urlEncodeUtils.h b/PermissionManager/app/src/main/cpp/urlEncodeUtils.h
new file mode 100644
index 00000000..0d1482f7
--- /dev/null
+++ b/PermissionManager/app/src/main/cpp/urlEncodeUtils.h
@@ -0,0 +1,74 @@
+#ifndef URL_ENCODE_UTILS_H_
+#define URL_ENCODE_UTILS_H_
+#include
+#include
+
+static inline char to_hex(char code) {
+ static char hex[] = "0123456789ABCDEF";
+ return hex[code & 15];
+}
+static inline char from_hex(char ch) {
+ return isdigit(ch) ? ch - '0' : tolower(ch) - 'a' + 10;
+}
+
+/*
+//使用例子
+int main() {
+ char str[] = "你好,世界";
+ char encoded_str[256];
+ url_encode(str, encoded_str);
+ printf("Encoded URL: %s\n", encoded_str);
+ return 0;
+}
+*/
+static void url_encode(char *str, char *encoded_str) {
+ char *pstr = str, *buf = encoded_str;
+ while (*pstr) {
+ unsigned char c = *pstr;
+ if (c <= 0x7F) { // ASCII
+ if (isalnum(c) || c == '-' || c == '_' || c == '.' || c == '~') {
+ *buf++ = c;
+ } else if (c == ' ') {
+ *buf++ = '+';
+ } else {
+ *buf++ = '%', *buf++ = to_hex(c >> 4), *buf++ = to_hex(c & 15);
+ }
+ } else { // Non-ASCII
+ while (c) {
+ *buf++ = '%', *buf++ = to_hex(c >> 4), *buf++ = to_hex(c & 15);
+ c = *(++pstr);
+ }
+ continue;
+ }
+ pstr++;
+ }
+ *buf = '\0';
+}
+/*
+//使用例子
+int main() {
+ char url[] = "%E4%BD%A0%E5%A5%BD%EF%BC%8C%E4%B8%96%E7%95%8C"; // "你好,世界"的URL编码
+ char decoded_str[256];
+ url_decode(url, decoded_str);
+ printf("Decoded URL: %s\n", decoded_str);
+ return 0;
+}
+*/
+static void url_decode(char *str, char *decoded_str) {
+ char *pstr = str, *buf = decoded_str;
+ while (*pstr) {
+ if (*pstr == '%') {
+ if (pstr[1] && pstr[2]) {
+ *buf++ = from_hex(pstr[1]) << 4 | from_hex(pstr[2]);
+ pstr += 2;
+ }
+ } else if (*pstr == '+') {
+ *buf++ = ' ';
+ } else {
+ *buf++ = *pstr;
+ }
+ pstr++;
+ }
+ *buf = '\0';
+}
+#endif
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/java/com/linux/permissionmanager/Adapter/SelectAppRecyclerAdapter.java b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Adapter/SelectAppRecyclerAdapter.java
new file mode 100644
index 00000000..8713f088
--- /dev/null
+++ b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Adapter/SelectAppRecyclerAdapter.java
@@ -0,0 +1,119 @@
+package com.linux.permissionmanager.Adapter;
+
+import android.content.Context;
+import android.graphics.drawable.Drawable;
+import android.os.Handler;
+import android.os.Message;
+import android.text.Html;
+import android.view.LayoutInflater;
+import android.view.View;
+import android.view.ViewGroup;
+import android.widget.ImageView;
+import android.widget.PopupWindow;
+import android.widget.TextView;
+
+import androidx.annotation.NonNull;
+import androidx.recyclerview.widget.RecyclerView;
+
+import com.linux.permissionmanager.Model.SelectAppRecyclerItem;
+import com.linux.permissionmanager.R;
+
+import java.util.ArrayList;
+import java.util.List;
+
+public class SelectAppRecyclerAdapter extends RecyclerView.Adapter {
+ public static class ViewHolder extends RecyclerView.ViewHolder {
+ public View v;
+ public ImageView select_app_icon;
+ public TextView select_app_text;
+ public TextView select_package_name;
+ public ViewHolder(View v) {
+ super(v);
+ this.v = v;
+ }
+
+ }
+
+ private int resourceId;
+ private List objects;
+ private PopupWindow popupWindow;
+ private Handler selectAppCallback;
+ private Context ctx;
+ public SelectAppRecyclerAdapter(Context ctx, int textViewResourceId, List objects, PopupWindow popupWindow, Handler selectAppCallback) {
+ this.resourceId = textViewResourceId;
+ this.objects = new ArrayList<>(objects);
+ this. popupWindow = popupWindow;
+ this. selectAppCallback = selectAppCallback;
+ this. ctx = ctx;
+ }
+
+ public void updateList(List newList) {
+ objects.clear();
+ objects.addAll(newList);
+ notifyDataSetChanged();
+ }
+
+
+ public List getList() {
+ return objects;
+ }
+
+
+ @NonNull
+ @Override
+ public ViewHolder onCreateViewHolder(@NonNull ViewGroup parent, int viewType) {
+ View v =LayoutInflater.from(parent.getContext()).inflate(resourceId,parent,false);
+ SelectAppRecyclerAdapter.ViewHolder holder = new SelectAppRecyclerAdapter.ViewHolder(v);
+
+ holder.select_app_icon = v.findViewById(R.id.select_app_icon);
+ holder.select_app_text=v.findViewById(R.id.select_app_text) ;
+ holder.select_package_name=v.findViewById(R.id.select_package_name) ;
+ return holder;
+ }
+
+
+ @Override
+ public void onBindViewHolder(@NonNull SelectAppRecyclerAdapter.ViewHolder holder, int position) {
+ SelectAppRecyclerItem appItem=objects.get(position);
+ String showName = appItem.getShowName(ctx);
+ String packageName = appItem.getPackageName();
+ Drawable icon = appItem.getDrawable(ctx);
+
+ //图标+进程PID+名字+内存
+ holder.select_app_icon.setImageDrawable(icon);
+ String showText=""+showName +" "
+ +" "+" ("+packageName+")"+"";
+
+ holder.select_app_text.setText(Html.fromHtml(showText));
+ holder.select_package_name.setText(packageName);
+
+ //item被点击
+ holder.v.setOnClickListener(new ClickRecyclerItemListener(appItem));
+ }
+
+
+ @Override
+ public int getItemCount() {
+ return objects.size();
+ }
+
+ @Override
+ public int getItemViewType(int position) {
+ return position;
+ }
+
+
+ class ClickRecyclerItemListener implements View.OnClickListener {
+ SelectAppRecyclerItem appItem;
+ public ClickRecyclerItemListener( SelectAppRecyclerItem appItem){
+ this.appItem =appItem;
+ }
+ @Override
+ public void onClick(View v) {
+ popupWindow.dismiss();
+ Message msg = new Message();
+ msg.obj = (SelectAppRecyclerItem)appItem;
+ selectAppCallback.sendMessage(msg);
+ }
+ }
+}
diff --git a/PermissionManager/app/src/main/java/com/linux/permissionmanager/Adapter/SelectFileRecyclerAdapter.java b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Adapter/SelectFileRecyclerAdapter.java
new file mode 100644
index 00000000..a39437ba
--- /dev/null
+++ b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Adapter/SelectFileRecyclerAdapter.java
@@ -0,0 +1,109 @@
+package com.linux.permissionmanager.Adapter;
+
+import android.content.Context;
+import android.graphics.Color;
+import android.os.Handler;
+import android.os.Message;
+import android.text.Html;
+import android.view.LayoutInflater;
+import android.view.View;
+import android.view.ViewGroup;
+import android.widget.ImageView;
+import android.widget.PopupWindow;
+import android.widget.TextView;
+
+import androidx.annotation.NonNull;
+import androidx.recyclerview.widget.RecyclerView;
+
+import com.linux.permissionmanager.Model.SelectFileRecyclerItem;
+import com.linux.permissionmanager.R;
+
+import java.util.ArrayList;
+import java.util.List;
+public class SelectFileRecyclerAdapter extends RecyclerView.Adapter {
+ public static class ViewHolder extends RecyclerView.ViewHolder {
+ public View v;
+ public TextView select_file_name;
+ public TextView select_file_desc;
+ public ViewHolder(View v) {
+ super(v);
+ this.v = v;
+ }
+ }
+ private int resourceId;
+ private List objects;
+ private PopupWindow popupWindow;
+ private Handler selectFileCallback;
+ private Context ctx;
+ public SelectFileRecyclerAdapter(Context ctx, int textViewResourceId, List objects, PopupWindow popupWindow, Handler selectFileCallback) {
+ this.resourceId = textViewResourceId;
+ this.objects = new ArrayList<>(objects);
+ this. popupWindow = popupWindow;
+ this. selectFileCallback = selectFileCallback;
+ this. ctx = ctx;
+ }
+
+ public void updateList(List newList) {
+ objects.clear();
+ objects.addAll(newList);
+ notifyDataSetChanged();
+ }
+
+
+ public List getList() {
+ return objects;
+ }
+
+
+ @NonNull
+ @Override
+ public ViewHolder onCreateViewHolder(@NonNull ViewGroup parent, int viewType) {
+ View v =LayoutInflater.from(parent.getContext()).inflate(resourceId,parent,false);
+ SelectFileRecyclerAdapter.ViewHolder holder = new SelectFileRecyclerAdapter.ViewHolder(v);
+
+ holder.select_file_name=v.findViewById(R.id.select_file_name) ;
+ holder.select_file_desc=v.findViewById(R.id.select_file_desc) ;
+ return holder;
+ }
+
+ @Override
+ public void onBindViewHolder(@NonNull ViewHolder holder, int position) {
+ SelectFileRecyclerItem fileItem=objects.get(position);
+ String fileName = fileItem.getFileName();
+ String fileDesc = fileItem.getFileDesc();
+ Color fileDescColor = fileItem.getFileDescColor();
+ String hexColor = String.format("#%06X", (0xFFFFFF & fileDescColor.toArgb()));
+
+ String showText=""+fileName +" ";
+ String showDesc=""+fileDesc +" ";
+ holder.select_file_name.setText(Html.fromHtml(showText));
+ holder.select_file_desc.setText(Html.fromHtml(showDesc));
+
+ holder.v.setOnClickListener(new ClickRecyclerItemListener(fileItem));
+ }
+
+ @Override
+ public int getItemCount() {
+ return objects.size();
+ }
+
+ @Override
+ public int getItemViewType(int position) {
+ return position;
+ }
+
+
+ class ClickRecyclerItemListener implements View.OnClickListener {
+ SelectFileRecyclerItem fileItem;
+ public ClickRecyclerItemListener(SelectFileRecyclerItem fileItem){
+ this.fileItem =fileItem;
+ }
+ @Override
+ public void onClick(View v) {
+ popupWindow.dismiss();
+ Message msg = new Message();
+ msg.obj = (SelectFileRecyclerItem)fileItem;
+ selectFileCallback.sendMessage(msg);
+ }
+ }
+}
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/java/com/linux/permissionmanager/MainActivity.java b/PermissionManager/app/src/main/java/com/linux/permissionmanager/MainActivity.java
new file mode 100644
index 00000000..17177031
--- /dev/null
+++ b/PermissionManager/app/src/main/java/com/linux/permissionmanager/MainActivity.java
@@ -0,0 +1,778 @@
+package com.linux.permissionmanager;
+
+import android.annotation.SuppressLint;
+import android.app.AlertDialog;
+import android.app.ProgressDialog;
+import android.content.ClipData;
+import android.content.ClipboardManager;
+import android.content.Context;
+import android.content.DialogInterface;
+import android.content.SharedPreferences;
+import android.content.pm.ApplicationInfo;
+import android.content.pm.PackageInfo;
+import android.graphics.Color;
+import android.graphics.drawable.ColorDrawable;
+import android.graphics.drawable.Drawable;
+import android.os.Bundle;
+import android.os.Handler;
+import android.os.Message;
+import android.text.Editable;
+import android.text.TextWatcher;
+import android.view.Gravity;
+import android.view.View;
+import android.view.ViewGroup;
+import android.widget.Button;
+import android.widget.CheckBox;
+import android.widget.CompoundButton;
+import android.widget.EditText;
+import android.widget.LinearLayout;
+import android.widget.PopupWindow;
+import android.widget.TextView;
+import android.widget.Toast;
+
+import androidx.annotation.NonNull;
+import androidx.appcompat.app.AppCompatActivity;
+import androidx.recyclerview.widget.LinearLayoutManager;
+import androidx.recyclerview.widget.RecyclerView;
+
+import com.linux.permissionmanager.Adapter.SelectAppRecyclerAdapter;
+import com.linux.permissionmanager.Adapter.SelectFileRecyclerAdapter;
+import com.linux.permissionmanager.Model.PopupWindowOnTouchClose;
+import com.linux.permissionmanager.Model.SelectAppRecyclerItem;
+import com.linux.permissionmanager.Model.SelectFileRecyclerItem;
+import com.linux.permissionmanager.Utils.ScreenInfoUtils;
+
+import org.json.JSONArray;
+import org.json.JSONObject;
+
+import java.net.URLDecoder;
+import java.nio.file.Path;
+import java.nio.file.Paths;
+import java.util.ArrayList;
+import java.util.HashMap;
+import java.util.List;
+import java.util.Map;
+import java.util.concurrent.atomic.AtomicReference;
+
+public class MainActivity extends AppCompatActivity implements View.OnClickListener {
+ private String rootKey = "bz4kKoPVSAG1tnwlcs1PJ1qp6HtVymj60CoTgsjmMd1UALve";
+ private String suBasePath = "/data/local/tmp";
+ private String lastInputCmd = "id";
+ private SharedPreferences m_shareSave;
+ private ProgressDialog m_loadingDlg = null;
+ private final String[] RECOMMEND_FILES = {"libc++_shared.so"};
+
+ static {
+ System.loadLibrary("permissionmanager");
+ }
+ @Override
+ protected void onCreate(Bundle savedInstanceState) {
+ super.onCreate(savedInstanceState);
+ setContentView(R.layout.activity_main);
+
+ m_shareSave = getSharedPreferences("zhcs", Context.MODE_PRIVATE);
+ try {
+ rootKey = m_shareSave.getString("rootKey", rootKey);
+ } catch (Exception e) {
+ }
+ try {
+ lastInputCmd = m_shareSave.getString("lastInputCmd", lastInputCmd);
+ } catch (Exception e) {
+ }
+
+ showUserInputRootKeyDlg();
+
+ Button test_root_btn = findViewById(R.id.test_root_btn);
+ Button run_root_cmd_btn = findViewById(R.id.run_root_cmd_btn);
+ Button run_init_process_cmd_btn = findViewById(R.id.run_init_process_cmd_btn);
+ Button su_env_install_btn = findViewById(R.id.su_env_install_btn);
+ Button su_env_inject_btn = findViewById(R.id.su_env_inject_btn);
+ Button clean_su_btn = findViewById(R.id.clean_su_btn);
+ Button implant_app_btn = findViewById(R.id.implant_app_btn);
+ Button copy_info_btn = findViewById(R.id.copy_info_btn);
+ Button clean_info_btn = findViewById(R.id.clean_info_btn);
+
+ test_root_btn.setOnClickListener(this);
+ run_root_cmd_btn.setOnClickListener(this);
+ run_init_process_cmd_btn.setOnClickListener(this);
+ su_env_install_btn.setOnClickListener(this);
+ su_env_inject_btn.setOnClickListener(this);
+ clean_su_btn.setOnClickListener(this);
+ implant_app_btn.setOnClickListener(this);
+ copy_info_btn.setOnClickListener(this);
+ clean_info_btn.setOnClickListener(this);
+
+ }
+
+ @Override
+ public void onClick(View v) {
+ switch (v.getId()) {
+ case R.id.test_root_btn:
+ appendConsoleMsg(testRoot(rootKey));
+ break;
+ case R.id.run_root_cmd_btn:
+ showUserInputRootCmdDlg(false);
+ break;
+ case R.id.run_init_process_cmd_btn:
+ showUserInputRootCmdDlg(true);
+ break;
+ case R.id.su_env_install_btn:
+ onClickSuEnvInstallBtn();
+ break;
+ case R.id.su_env_inject_btn:
+ showSelectSuInjectModeDlg();
+ break;
+ case R.id.clean_su_btn:
+ appendConsoleMsg(uninstallSu(rootKey,suBasePath));
+ break;
+ case R.id.implant_app_btn:
+ onClickImplantAppBtn();
+ break;
+ case R.id.copy_info_btn:
+ copyConsoleMsg();
+ break;
+ case R.id.clean_info_btn:
+ cleanConsoleMsg();
+ break;
+ default:
+ break;
+ }
+ }
+ public void showUserInputRootKeyDlg() {
+ Handler inputCallback = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+ String inputTxt = (String)msg.obj;
+ rootKey = inputTxt;
+ SharedPreferences.Editor mEdit = m_shareSave.edit();
+ mEdit.putString("rootKey", rootKey);
+ mEdit.commit();
+ super.handleMessage(msg);
+ }
+ };
+ showInputDlg(rootKey,"请输入ROOT权限的KEY", inputCallback);
+ }
+
+ public void showUserInputRootCmdDlg(boolean isKernelCmd) {
+ Handler inputCallback = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+ String inputTxt = (String)msg.obj;
+ lastInputCmd = inputTxt;
+ SharedPreferences.Editor mEdit = m_shareSave.edit();
+ mEdit.putString("lastInputCmd", lastInputCmd);
+ mEdit.commit();
+ appendConsoleMsg(inputTxt + "\n"
+ + (isKernelCmd ? runInit64ProcessCmd(rootKey, inputTxt) : runRootCmd(rootKey, inputTxt)));
+ super.handleMessage(msg);
+ }
+ };
+
+ showInputDlg(lastInputCmd, isKernelCmd ? "输入ROOT命令" : "输入普通命令", inputCallback);
+ }
+
+ public void showInputDlg(String defaultText, String title, Handler confirmCallback) {
+ final EditText inputTxt = new EditText(MainActivity.this);
+ inputTxt.setText(defaultText);
+ inputTxt.setFocusable(true);
+ inputTxt.setSelection(defaultText.length(), 0);
+ AlertDialog.Builder builder = new AlertDialog.Builder(MainActivity.this);
+ builder.setTitle(title).setIcon(android.R.drawable.ic_dialog_info).setView(inputTxt)
+ .setNegativeButton("取消", new DialogInterface.OnClickListener() {
+ @Override
+ public void onClick(DialogInterface dialog, int which) {
+ dialog.dismiss();
+ }
+ });
+ builder.setPositiveButton("确定", new DialogInterface.OnClickListener() {
+ public void onClick(DialogInterface dialog, int which) {
+ String text = inputTxt.getText().toString();
+ Message msg = new Message();
+ msg.obj = text;
+ confirmCallback.sendMessage(msg);
+ }
+ });
+ AlertDialog dialog = builder.create();
+ dialog.show();
+ }
+
+ private void showMsgDlg(String title, String msg, Drawable icon) {
+ AlertDialog.Builder builder = new AlertDialog.Builder(this);
+ builder.setTitle(title);
+ builder.setMessage(msg);
+ if(icon != null) {
+ builder.setIcon(icon);
+ }
+ builder.setPositiveButton("确定", new DialogInterface.OnClickListener() {
+ public void onClick(DialogInterface dialog, int id) {
+ dialog.dismiss();
+ }
+ });
+ AlertDialog dialog = builder.create();
+ dialog.show();
+ }
+
+ public void onClickSuEnvInstallBtn() {
+ //1.安装su工具
+ String insRet = installSu(rootKey, suBasePath);
+ appendConsoleMsg(insRet);
+ if(insRet.indexOf("installSu done.") != -1) {
+ //2.复制su的路径到剪贴板
+ String suFullPath = getLastInstallSuFullPath();
+ appendConsoleMsg("lastInstallSuFullPath:" + suFullPath);
+ showMsgDlg("温馨提示",
+ "安装部署su成功,su路径已复制到剪贴板。", null);
+ copyEditText(suFullPath);
+ appendConsoleMsg("安装部署su成功,su路径已复制到剪贴板");
+ }
+ }
+
+ private void suTempInject() {
+ Handler selectInjectSuAppCallback = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+
+ SelectAppRecyclerItem appItem = (SelectAppRecyclerItem) msg.obj;
+
+ if (m_loadingDlg == null) {
+ m_loadingDlg = new ProgressDialog(MainActivity.this);
+ m_loadingDlg.setCancelable(false);
+ }
+ m_loadingDlg.setTitle("");
+ m_loadingDlg.setMessage("请现在手动启动APP [" + appItem.getShowName(MainActivity.this) + "]");
+ m_loadingDlg.show();
+
+ new Thread() {
+ public void run() {
+ String autoSuEnvInjectRet = autoSuEnvInject(rootKey, appItem.getPackageName());
+ runOnUiThread(new Runnable() {
+ public void run() {
+ appendConsoleMsg(autoSuEnvInjectRet);
+ m_loadingDlg.cancel();
+
+ if(autoSuEnvInjectRet.indexOf("autoSuEnvInject done.")!= -1) {
+ showMsgDlg("提示",
+ "已授予ROOT权限至APP [" + appItem.getShowName(MainActivity.this) + "]",
+ appItem.getDrawable(MainActivity.this));
+ }
+
+ }
+ });
+ }
+ }.start();
+ super.handleMessage(msg);
+ }
+ };
+ showSelectAppDlg(selectInjectSuAppCallback);
+ }
+
+ private void suForeverInject() {
+ Handler selectImplantSuEnvCallback = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+ SelectAppRecyclerItem appItem = (SelectAppRecyclerItem) msg.obj;
+ if (m_loadingDlg == null) {
+ m_loadingDlg = new ProgressDialog(MainActivity.this);
+ m_loadingDlg.setCancelable(false);
+ }
+ m_loadingDlg.setTitle("");
+ m_loadingDlg.setMessage("请现在手动启动APP [" + appItem.getShowName(MainActivity.this) + "]");
+ m_loadingDlg.show();
+ new Thread() {
+ public void run() {
+ String parasitePrecheckAppRet = parasitePrecheckApp(rootKey, appItem.getPackageName());
+ runOnUiThread(new Runnable() {
+ public void run() {
+ m_loadingDlg.cancel();
+ Map fileList = parseSoFullPathInfo(parasitePrecheckAppRet);
+ if (fileList.size() == 0 && !parasitePrecheckAppRet.isEmpty()) {
+ appendConsoleMsg(parasitePrecheckAppRet);
+ return;
+ }
+ Handler selectFileCallback = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+ SelectFileRecyclerItem fileItem = (SelectFileRecyclerItem) msg.obj;
+ String parasiteImplantSuEnvRet = parasiteImplantSuEnv(rootKey, appItem.getPackageName(), fileItem.getFilePath());
+ appendConsoleMsg(parasiteImplantSuEnvRet);
+ if(parasiteImplantSuEnvRet.indexOf("parasiteImplantSuEnv done.")!= -1) {
+ showMsgDlg("提示",
+ "已永久寄生su环境至APP [" + appItem.getShowName(MainActivity.this) + "]",
+ appItem.getDrawable(MainActivity.this));
+ }
+ super.handleMessage(msg);
+ }
+ };
+ showSelectFileDlg(fileList, selectFileCallback);
+ }
+ });
+ }
+ }.start();
+ super.handleMessage(msg);
+ }
+ };
+ View view = showSelectAppDlg(selectImplantSuEnvCallback);
+ CheckBox show_system_app_ckbox = view.findViewById(R.id.show_system_app_ckbox);
+ CheckBox show_thirty_app_ckbox = view.findViewById(R.id.show_thirty_app_ckbox);
+ CheckBox show_running_app_ckbox = view.findViewById(R.id.show_running_app_ckbox);
+ show_system_app_ckbox.setChecked(false);
+ show_system_app_ckbox.setEnabled(false);
+
+ show_thirty_app_ckbox.setChecked(true);
+ show_thirty_app_ckbox.setEnabled(false);
+
+ show_running_app_ckbox.setChecked(true);
+ show_running_app_ckbox.setEnabled(false);
+ }
+
+ public void showSelectSuInjectModeDlg() {
+ final String[] items = {"临时授权su", "永久授权su"};
+ AlertDialog.Builder builder = new AlertDialog.Builder(this);
+ builder.setTitle("请选择一个选项");
+ builder.setSingleChoiceItems(items, -1, new DialogInterface.OnClickListener() {
+ @Override
+ public void onClick(DialogInterface dialog, int which) {
+ dialog.dismiss();
+ if(which == 0) {
+ suTempInject();
+ } else if(which == 1) {
+ suForeverInject();
+ }
+ }
+ });
+ builder.setNegativeButton("取消", new DialogInterface.OnClickListener() {
+ @Override
+ public void onClick(DialogInterface dialog, int which) {
+ dialog.dismiss();
+ }
+ });
+ AlertDialog dialog = builder.create();
+ dialog.show();
+ }
+
+ public void onClickImplantAppBtn() {
+ showMsgDlg("建议", "为了实现最佳隐蔽性,推荐寄生到能常驻后台且联网的APP上,如音乐类、播放器类、运动类、广播类、社交聊天类APP", null);
+ Handler selectImplantAppCallback = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+ SelectAppRecyclerItem appItem = (SelectAppRecyclerItem) msg.obj;
+ if (m_loadingDlg == null) {
+ m_loadingDlg = new ProgressDialog(MainActivity.this);
+ m_loadingDlg.setCancelable(false);
+ }
+ m_loadingDlg.setTitle("");
+ m_loadingDlg.setMessage("请现在手动启动APP [" + appItem.getShowName(MainActivity.this) + "]");
+ m_loadingDlg.show();
+ new Thread() {
+ public void run() {
+ String parasitePrecheckAppRet = parasitePrecheckApp(rootKey, appItem.getPackageName());
+ runOnUiThread(new Runnable() {
+ public void run() {
+ m_loadingDlg.cancel();
+ Map fileList = parseSoFullPathInfo(parasitePrecheckAppRet);
+ if (fileList.size() == 0 && !parasitePrecheckAppRet.isEmpty()) {
+ appendConsoleMsg(parasitePrecheckAppRet);
+ return;
+ }
+ Handler selectFileCallback = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+ SelectFileRecyclerItem fileItem = (SelectFileRecyclerItem) msg.obj;
+ String parasiteImplantAppRet = parasiteImplantApp(rootKey, appItem.getPackageName(), fileItem.getFilePath());
+ appendConsoleMsg(parasiteImplantAppRet);
+ if(parasiteImplantAppRet.indexOf("parasiteImplantApp done.")!= -1) {
+ showMsgDlg("提示",
+ "已经寄生到APP [" + appItem.getShowName(MainActivity.this) + "]",
+ appItem.getDrawable(MainActivity.this));
+ }
+ super.handleMessage(msg);
+ }
+ };
+ showSelectFileDlg(fileList, selectFileCallback);
+ }
+ });
+ }
+ }.start();
+ super.handleMessage(msg);
+ }
+ };
+ View view = showSelectAppDlg(selectImplantAppCallback);
+ CheckBox show_system_app_ckbox = view.findViewById(R.id.show_system_app_ckbox);
+ CheckBox show_thirty_app_ckbox = view.findViewById(R.id.show_thirty_app_ckbox);
+ CheckBox show_running_app_ckbox = view.findViewById(R.id.show_running_app_ckbox);
+ show_system_app_ckbox.setChecked(false);
+ show_system_app_ckbox.setEnabled(false);
+ show_thirty_app_ckbox.setChecked(true);
+ show_thirty_app_ckbox.setEnabled(false);
+ show_running_app_ckbox.setChecked(true);
+ show_running_app_ckbox.setEnabled(false);
+ }
+
+ public void appendConsoleMsg(String msg) {
+ EditText console_edit = findViewById(R.id.console_edit);
+ StringBuffer txt = new StringBuffer();
+ txt.append(console_edit.getText().toString());
+ if (txt.length() != 0) {
+ txt.append("\n");
+ }
+ txt.append(msg);
+ txt.append("\n");
+ console_edit.setText(txt.toString());
+ console_edit.setSelection(txt.length());
+ }
+
+ public void copyConsoleMsg() {
+ EditText edit = findViewById(R.id.console_edit);
+ copyEditText(edit.getText().toString());
+ Toast.makeText(this, "复制成功", Toast.LENGTH_SHORT).show();
+ }
+
+ public void cleanConsoleMsg() {
+ EditText console_edit = findViewById(R.id.console_edit);
+ console_edit.setText("");
+ }
+
+ public void copyEditText(String text) {
+ ClipboardManager cm = (ClipboardManager) getSystemService(Context.CLIPBOARD_SERVICE);
+ ClipData mClipData = ClipData.newPlainText("Label", text);
+ cm.setPrimaryClip(mClipData);
+ }
+
+ public View showSelectAppDlg(Handler selectAppCallback) {
+ final PopupWindow popupWindow = new PopupWindow(this);
+
+ View view = View.inflate(this, R.layout.select_app_wnd, null);
+ popupWindow.setContentView(view);
+
+ popupWindow.setHeight(ViewGroup.LayoutParams.MATCH_PARENT);
+ popupWindow.setWidth(ViewGroup.LayoutParams.MATCH_PARENT);
+ popupWindow.setBackgroundDrawable(new ColorDrawable(0x9B000000));
+ popupWindow.setOutsideTouchable(true);
+ popupWindow.setFocusable(true);
+ popupWindow.setTouchable(true);
+
+ //全屏
+ View parent = View.inflate(MainActivity.this, R.layout.activity_main, null);
+ popupWindow.showAtLocation(parent, Gravity.NO_GRAVITY, 0, 0);
+ popupWindow.showAsDropDown(parent, 0, 0);
+
+ popupWindow.setOnDismissListener(new PopupWindow.OnDismissListener() {
+ @Override
+ public void onDismiss() {
+ }
+ });
+
+ final int screenWidth = ScreenInfoUtils.getRealWidth(this);
+ final int screenHeight = ScreenInfoUtils.getRealHeight(this);
+
+ final double centerWidth = ((double) screenWidth) * 0.80;
+ final double centerHeight = ((double) screenHeight) * 0.90;
+
+ LinearLayout center_layout = (LinearLayout) view.findViewById(R.id.center_layout);
+ android.view.ViewGroup.LayoutParams lp = center_layout.getLayoutParams();
+ lp.width = (int) centerWidth;
+ lp.height = (int) centerHeight;
+
+ //点击阴影部分可关闭窗口
+ popupWindow.setTouchInterceptor(new PopupWindowOnTouchClose(popupWindow,
+ screenWidth, screenHeight, (int) centerWidth, (int) centerHeight));
+
+ List appList = new ArrayList<>();
+ List packages = getPackageManager().getInstalledPackages(0);
+
+ for (int i = 0; i < packages.size(); i++) {
+ PackageInfo packageInfo = packages.get(i);
+ String packageName = packageInfo.applicationInfo.packageName;
+ if(packageName.equals(getPackageName())){
+ continue;
+ }
+ appList.add(new SelectAppRecyclerItem(packageInfo));
+ }
+
+ SelectAppRecyclerAdapter adapter = new SelectAppRecyclerAdapter(
+ MainActivity.this, R.layout.select_app_recycler_item, appList, popupWindow, selectAppCallback);
+ RecyclerView select_app_recycler_view = (RecyclerView) view.findViewById(R.id.select_app_recycler_view);
+ LinearLayoutManager linearLayoutManager = new LinearLayoutManager(this);
+ linearLayoutManager.setOrientation(LinearLayoutManager.VERTICAL);
+ select_app_recycler_view.setLayoutManager(linearLayoutManager);
+ select_app_recycler_view.setAdapter(adapter);
+
+ // 获取正在运行的APP
+ String runningApp = getAllCmdlineProcess(rootKey);
+ Map processMap = parseProcessInfo(runningApp);
+ if(processMap.size() == 0 && !runningApp.isEmpty()) {
+ appendConsoleMsg(runningApp);
+ }
+
+ TextView clear_search_btn = view.findViewById(R.id.clear_search_btn);
+ EditText search_edit = view.findViewById(R.id.search_edit);
+ CheckBox show_system_app_ckbox = view.findViewById(R.id.show_system_app_ckbox);
+ CheckBox show_thirty_app_ckbox = view.findViewById(R.id.show_thirty_app_ckbox);
+ CheckBox show_running_app_ckbox = view.findViewById(R.id.show_running_app_ckbox);
+ show_system_app_ckbox.setEnabled(true);
+ show_thirty_app_ckbox.setEnabled(true);
+ show_running_app_ckbox.setEnabled(true);
+ Map finalProcessMap = processMap;
+ @SuppressLint("HandlerLeak") Handler updateAppListFunc = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+ List newAppList = new ArrayList<>();
+ String filterText = search_edit.getText().toString();
+ for(SelectAppRecyclerItem item : appList) {
+ PackageInfo pack = item.getPackageInfo();
+ if(!show_system_app_ckbox.isChecked()) {
+ if ((pack.applicationInfo.flags & ApplicationInfo.FLAG_SYSTEM) != 0) { //系统应用
+ continue;
+ }
+ }
+ if(!show_thirty_app_ckbox.isChecked()) {
+ if ((pack.applicationInfo.flags & ApplicationInfo.FLAG_SYSTEM) == 0) { //第三方应用
+ continue;
+ }
+ }
+ if (show_running_app_ckbox.isChecked()) {
+ boolean isFound = finalProcessMap.values().stream()
+ .anyMatch(value -> value.contains(item.getPackageName()));
+ if (!isFound) {
+ continue;
+ }
+ }
+ if(item.getPackageName().indexOf(filterText) != -1 || item.getShowName(MainActivity.this).indexOf(filterText) != -1) {
+ newAppList.add(item);
+ }
+ }
+ adapter.updateList(newAppList);
+ super.handleMessage(msg);
+ }
+ };
+ search_edit.addTextChangedListener(new TextWatcher() {
+ @Override
+ public void beforeTextChanged(CharSequence s, int start, int count, int after) {
+ }
+ @Override
+ public void onTextChanged(CharSequence s, int start, int before, int count) {
+ String text = s.toString();
+ if(text.length() > 0) {
+ clear_search_btn.setVisibility(View.VISIBLE);
+ } else {
+ clear_search_btn.setVisibility(View.GONE);
+ }
+ updateAppListFunc.sendMessage(new Message());
+ }
+ @Override
+ public void afterTextChanged(Editable s) {
+ }
+ });
+ clear_search_btn.setOnClickListener(new View.OnClickListener() {
+ @Override
+ public void onClick(View v) {
+ search_edit.setText("");
+ }
+ });
+
+ show_system_app_ckbox.setOnCheckedChangeListener(new CompoundButton.OnCheckedChangeListener() {
+ @Override
+ public void onCheckedChanged(CompoundButton buttonView, boolean isChecked) {
+ updateAppListFunc.sendMessage(new Message());
+ }
+ });
+ show_thirty_app_ckbox.setOnCheckedChangeListener(new CompoundButton.OnCheckedChangeListener() {
+ @Override
+ public void onCheckedChanged(CompoundButton buttonView, boolean isChecked) {
+ updateAppListFunc.sendMessage(new Message());
+ }
+ });
+ show_running_app_ckbox.setOnCheckedChangeListener(new CompoundButton.OnCheckedChangeListener() {
+ @Override
+ public void onCheckedChanged(CompoundButton buttonView, boolean isChecked) {
+ updateAppListFunc.sendMessage(new Message());
+ }
+ });
+ updateAppListFunc.sendMessage(new Message());
+ return view;
+ }
+
+ private boolean checkIsRecommendFile(String filePath) {
+ Path path = Paths.get(filePath);
+ String fileName = path.getFileName().toString();
+ for (String recommendFile : RECOMMEND_FILES) {
+ if (recommendFile.equals(fileName)) {
+ return true;
+ }
+ }
+ return false;
+ }
+
+ public View showSelectFileDlg(Map filePath, Handler selectFileCallback) {
+ final PopupWindow popupWindow = new PopupWindow(this);
+
+ View view = View.inflate(this, R.layout.select_file_wnd, null);
+ popupWindow.setContentView(view);
+
+ popupWindow.setHeight(ViewGroup.LayoutParams.MATCH_PARENT);
+ popupWindow.setWidth(ViewGroup.LayoutParams.MATCH_PARENT);
+ popupWindow.setBackgroundDrawable(new ColorDrawable(0x9B000000));
+ popupWindow.setOutsideTouchable(true);
+ popupWindow.setFocusable(true);
+ popupWindow.setTouchable(true);
+
+ //全屏
+ View parent = View.inflate(MainActivity.this, R.layout.activity_main, null);
+ popupWindow.showAtLocation(parent, Gravity.NO_GRAVITY, 0, 0);
+ popupWindow.showAsDropDown(parent, 0, 0);
+
+ popupWindow.setOnDismissListener(new PopupWindow.OnDismissListener() {
+ @Override
+ public void onDismiss() {
+ }
+ });
+
+ final int screenWidth = ScreenInfoUtils.getRealWidth(this);
+ final int screenHeight = ScreenInfoUtils.getRealHeight(this);
+
+ final double centerWidth = ((double) screenWidth) * 0.80;
+ final double centerHeight = ((double) screenHeight) * 0.90;
+
+ LinearLayout center_layout = (LinearLayout) view.findViewById(R.id.center_layout);
+ android.view.ViewGroup.LayoutParams lp = center_layout.getLayoutParams();
+ lp.width = (int) centerWidth;
+ lp.height = (int) centerHeight;
+
+ //点击阴影部分可关闭窗口
+ popupWindow.setTouchInterceptor(new PopupWindowOnTouchClose(popupWindow,
+ screenWidth, screenHeight, (int) centerWidth, (int) centerHeight));
+
+ List fileList = new ArrayList<>();
+ for (Map.Entry entry : filePath.entrySet()) {
+ String strFilePath = entry.getKey();
+ Integer status = entry.getValue();
+ if(status != 1) {
+ continue;
+ }
+ String strFileDesc = checkIsRecommendFile(strFilePath) ? "(推荐,正在运行)" : "(正在运行)";
+ fileList.add(new SelectFileRecyclerItem(strFilePath, strFileDesc, Color.valueOf(0xFFFFFFFF)));
+ }
+ for (Map.Entry entry : filePath.entrySet()) {
+ String strFilePath = entry.getKey();
+ Integer status = entry.getValue();
+ if(status != 2) {
+ continue;
+ }
+ String strFileDesc ="(未运行)";
+ fileList.add(new SelectFileRecyclerItem(strFilePath, strFileDesc, Color.valueOf(Color.GRAY)));
+ }
+
+ SelectFileRecyclerAdapter adapter = new SelectFileRecyclerAdapter(
+ MainActivity.this, R.layout.select_file_recycler_item, fileList, popupWindow, selectFileCallback);
+ RecyclerView select_file_recycler_view = (RecyclerView) view.findViewById(R.id.select_file_recycler_view);
+ LinearLayoutManager linearLayoutManager = new LinearLayoutManager(this);
+ linearLayoutManager.setOrientation(LinearLayoutManager.VERTICAL);
+ select_file_recycler_view.setLayoutManager(linearLayoutManager);
+ select_file_recycler_view.setAdapter(adapter);
+
+ TextView clear_search_btn = view.findViewById(R.id.clear_search_btn);
+ EditText search_edit = view.findViewById(R.id.search_edit);
+
+ @SuppressLint("HandlerLeak") Handler updateFileListFunc = new Handler() {
+ @Override
+ public void handleMessage(@NonNull Message msg) {
+ List newFileList = new ArrayList<>();
+ String filterText = search_edit.getText().toString();
+ for(SelectFileRecyclerItem item : fileList) {
+ String fileName = item.getFileName();
+ if(fileName.indexOf(filterText) != -1) {
+ newFileList.add(item);
+ }
+ }
+ adapter.updateList(newFileList);
+ super.handleMessage(msg);
+ }
+ };
+ search_edit.addTextChangedListener(new TextWatcher() {
+ @Override
+ public void beforeTextChanged(CharSequence s, int start, int count, int after) {
+
+ }
+
+ @Override
+ public void onTextChanged(CharSequence s, int start, int before, int count) {
+ String text = s.toString();
+ if(text.length() > 0) {
+ clear_search_btn.setVisibility(View.VISIBLE);
+ } else {
+ clear_search_btn.setVisibility(View.GONE);
+ }
+ updateFileListFunc.sendMessage(new Message());
+ }
+
+ @Override
+ public void afterTextChanged(Editable s) {
+ }
+ });
+ clear_search_btn.setOnClickListener(new View.OnClickListener() {
+ @Override
+ public void onClick(View v) {
+ search_edit.setText("");
+ }
+ });
+ updateFileListFunc.sendMessage(new Message());
+ return view;
+ }
+
+ private Map parseProcessInfo(String jsonStr) {
+ Map processMap = new HashMap<>();
+ try {
+ JSONArray jsonArray = new JSONArray(jsonStr);
+ for (int i = 0; i < jsonArray.length(); i++) {
+ JSONObject jsonObject = jsonArray.getJSONObject(i);
+ int pid = jsonObject.getInt("pid");
+ String encodedValue = jsonObject.getString("name");
+ String name = URLDecoder.decode(encodedValue, "UTF-8");
+ processMap.put(pid, name);
+ }
+ } catch (Exception e) {
+ e.printStackTrace();
+ }
+ return processMap;
+ }
+
+ public Map parseSoFullPathInfo(String jsonStr) {
+ Map soPathMap = new HashMap<>();
+ try {
+ JSONArray jsonArray = new JSONArray(jsonStr);
+ for (int i = 0; i < jsonArray.length(); i++) {
+ JSONObject jsonObject = jsonArray.getJSONObject(i);
+ String encodedValue = jsonObject.getString("name");
+ String name = URLDecoder.decode(encodedValue, "UTF-8");
+ int pid = jsonObject.getInt("status");
+ soPathMap.put(name,pid);
+ }
+ } catch (Exception e) {
+ e.printStackTrace();
+ }
+ return soPathMap;
+ }
+
+ public native String testRoot(String rootKey);
+
+ public native String runRootCmd(String rootKey, String cmd);
+
+ public native String runInit64ProcessCmd(String rootKey, String cmd);
+
+ public native String installSu(String rootKey, String basePath);
+
+ public native String getLastInstallSuFullPath();
+
+ public native String uninstallSu(String rootKey, String basePath);
+
+ public native String autoSuEnvInject(String rootKey, String targetProcessCmdline);
+
+ public native String getAllCmdlineProcess(String rootKey);
+
+ public native String parasitePrecheckApp(String rootKey, String targetProcessCmdline);
+
+ public native String parasiteImplantApp(String rootKey, String targetProcessCmdline, String targetSoFullPath);
+
+ public native String parasiteImplantSuEnv(String rootKey, String targetProcessCmdline, String targetSoFullPath);
+
+}
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/PopupWindowOnTouchClose.java b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/PopupWindowOnTouchClose.java
new file mode 100644
index 00000000..ca4889d7
--- /dev/null
+++ b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/PopupWindowOnTouchClose.java
@@ -0,0 +1,48 @@
+package com.linux.permissionmanager.Model;
+
+import android.view.MotionEvent;
+import android.view.View;
+import android.widget.PopupWindow;
+
+public class PopupWindowOnTouchClose implements View.OnTouchListener {
+ private boolean lastVailedDown = true;
+ private int screenWidth, screenHeight, centerWidth, centerHeight;
+ private PopupWindow popupWindow;
+
+ public PopupWindowOnTouchClose(PopupWindow popupWindow, int screenWidth, int screenHeight, int centerWidth, int centerHeight) {
+ this.popupWindow = popupWindow;
+ this.screenWidth = screenWidth;
+ this.screenHeight = screenHeight;
+ this.centerWidth = centerWidth;
+ this.centerHeight = centerHeight;
+ }
+
+ private boolean isValiedRegion(View v, MotionEvent event) {
+ int x = (int) event.getX();
+ int y = (int) event.getY();
+ double wndLeft = (screenWidth - centerWidth) / 2;
+ double wndTop = (screenHeight - centerHeight) / 2;
+ if (x < wndLeft || x > wndLeft + centerWidth || y < wndTop || y > wndTop + centerHeight) {
+ return false;
+ }
+ return true;
+ }
+
+ @Override
+ public boolean onTouch(View v, MotionEvent event) {
+
+ if (event.getAction() == MotionEvent.ACTION_DOWN) {
+ lastVailedDown = isValiedRegion(v, event);
+ } else if (event.getAction() == MotionEvent.ACTION_UP) {
+ if (!lastVailedDown) {
+ if (!isValiedRegion(v, event)) {
+ popupWindow.dismiss();
+ }
+ }
+ }
+ return false;
+ }
+}
+
+
+
diff --git a/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/SelectAppRecyclerItem.java b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/SelectAppRecyclerItem.java
new file mode 100644
index 00000000..3c6b4f82
--- /dev/null
+++ b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/SelectAppRecyclerItem.java
@@ -0,0 +1,31 @@
+package com.linux.permissionmanager.Model;
+
+import android.content.Context;
+import android.content.pm.PackageInfo;
+import android.graphics.drawable.Drawable;
+
+public class SelectAppRecyclerItem {
+ private PackageInfo packageInfo;
+
+ public SelectAppRecyclerItem(PackageInfo packageInfo){
+ this.packageInfo = packageInfo;
+ }
+
+ public PackageInfo getPackageInfo() {
+ return packageInfo;
+ }
+
+ public String getShowName(Context ctx) {
+ String showName = this.packageInfo.applicationInfo.loadLabel(ctx.getPackageManager()).toString();
+ return showName;
+ }
+ public String getPackageName() {
+ String packageName = this.packageInfo.applicationInfo.packageName;
+ return packageName;
+ }
+ public Drawable getDrawable(Context ctx) {
+ Drawable icon = this.packageInfo.applicationInfo.loadIcon(ctx.getPackageManager());
+ return icon;
+ }
+
+}
diff --git a/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/SelectFileRecyclerItem.java b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/SelectFileRecyclerItem.java
new file mode 100644
index 00000000..bf15017b
--- /dev/null
+++ b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Model/SelectFileRecyclerItem.java
@@ -0,0 +1,37 @@
+package com.linux.permissionmanager.Model;
+
+import android.graphics.Color;
+import android.os.Build;
+
+import androidx.annotation.RequiresApi;
+
+import java.nio.file.Path;
+import java.nio.file.Paths;
+
+public class SelectFileRecyclerItem {
+ private String filePath;
+ private String fileDesc;
+ private Color fileDescColor;
+
+ public SelectFileRecyclerItem(String filePath, String fileDesc, Color fileDescColor){
+ this.filePath = filePath;
+ this.fileDesc = fileDesc;
+ this.fileDescColor = fileDescColor;
+ }
+
+ public String getFilePath() {
+ return this.filePath;
+ }
+
+ public String getFileName() {
+ Path path = Paths.get(filePath);
+ Path fileName = path.getFileName();
+ return fileName.toString();
+ }
+ public String getFileDesc() {
+ return this.fileDesc;
+ }
+ public Color getFileDescColor() {
+ return this.fileDescColor;
+ }
+}
diff --git a/PermissionManager/app/src/main/java/com/linux/permissionmanager/Utils/ScreenInfoUtils.java b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Utils/ScreenInfoUtils.java
new file mode 100644
index 00000000..5e50159e
--- /dev/null
+++ b/PermissionManager/app/src/main/java/com/linux/permissionmanager/Utils/ScreenInfoUtils.java
@@ -0,0 +1,187 @@
+package com.linux.permissionmanager.Utils;
+
+import android.app.Activity;
+import android.content.Context;
+import android.content.res.Resources;
+import android.util.DisplayMetrics;
+import android.util.Log;
+import android.util.TypedValue;
+import android.view.Display;
+import android.view.WindowManager;
+
+/**
+ * Get Screen Information Utils
+ *
+ * @author yh
+ * @date 2018/12/18.
+ */
+public class ScreenInfoUtils {
+
+ private static final String TAG = "ScreenInfoUtils";
+
+ /**
+ * Get Screen Width
+ */
+ public static int getScreenWidth(Context context) {
+ return getDisplayMetrics(context).widthPixels;
+ }
+
+ /**
+ * Get Screen Height
+ */
+ public static int getScreenHeight(Context context) {
+ return getDisplayMetrics(context).heightPixels;
+ }
+
+
+ /**
+ * Get Screen Real Height
+ *
+ * @param context Context
+ * @return Real Height
+ */
+ public static int getRealHeight(Context context) {
+ Display display = getDisplay(context);
+ if (display == null) {
+ return 0;
+ }
+ DisplayMetrics dm = new DisplayMetrics();
+ display.getRealMetrics(dm);
+ return dm.heightPixels;
+ }
+
+ /**
+ * Get Screen Real Width
+ *
+ * @param context Context
+ * @return Real Width
+ */
+ public static int getRealWidth(Context context) {
+ Display display = getDisplay(context);
+ if (display == null) {
+ return 0;
+ }
+ DisplayMetrics dm = new DisplayMetrics();
+ display.getRealMetrics(dm);
+ return dm.widthPixels;
+ }
+
+ /**
+ * Get StatusBar Height
+ */
+ public static int getStatusBarHeight(Context mContext) {
+ int resourceId = mContext.getResources().getIdentifier("status_bar_height", "dimen", "android");
+ if (resourceId > 0) {
+ return mContext.getResources().getDimensionPixelSize(resourceId);
+ }
+ return 0;
+ }
+
+ /**
+ * Get ActionBar Height
+ */
+ public static int getActionBarHeight(Context mContext) {
+ TypedValue tv = new TypedValue();
+ if (mContext.getTheme().resolveAttribute(android.R.attr.actionBarSize, tv, true)) {
+ return TypedValue.complexToDimensionPixelSize(tv.data, mContext.getResources().getDisplayMetrics());
+ }
+ return 0;
+ }
+
+ /**
+ * Get NavigationBar Height
+ */
+ public static int getNavigationBarHeight(Context mContext) {
+ Resources resources = mContext.getResources();
+ int resourceId = resources.getIdentifier("navigation_bar_height", "dimen", "android");
+ if (resourceId > 0) {
+ return resources.getDimensionPixelSize(resourceId);
+ }
+ return 0;
+ }
+
+ /**
+ * Get Density
+ */
+ private static float getDensity(Context context) {
+ return getDisplayMetrics(context).density;
+ }
+
+ /**
+ * Get Dpi
+ */
+ private static int getDpi(Context context) {
+ return getDisplayMetrics(context).densityDpi;
+ }
+
+ /**
+ * Get Display
+ *
+ * @param context Context for get WindowManager
+ * @return Display
+ */
+ private static Display getDisplay(Context context) {
+ WindowManager wm;
+ if (context instanceof Activity) {
+ Activity activity = (Activity) context;
+ wm = activity.getWindowManager();
+ } else {
+ wm = (WindowManager) context.getSystemService(Context.WINDOW_SERVICE);
+ }
+ if (wm != null) {
+ return wm.getDefaultDisplay();
+ }
+ return null;
+ }
+
+ /**
+ * Get DisplayMetrics
+ *
+ * @param context Context for get Resources
+ * @return DisplayMetrics
+ */
+ private static DisplayMetrics getDisplayMetrics(Context context) {
+ return context.getResources().getDisplayMetrics();
+ }
+
+
+ /**
+ * Get ScreenInfo
+ */
+ private static String getScreenInfo(Context context) {
+ return " \n" +
+ "--------ScreenInfo--------" + "\n" +
+ "Screen Width : " + getScreenWidth(context) + "px\n" +
+ "Screen RealWidth :" + getRealWidth(context) + "px\n" +
+ "Screen Height: " + getScreenHeight(context) + "px\n" +
+ "Screen RealHeight: " + getRealHeight(context) + "px\n" +
+ "Screen StatusBar Height: " + getStatusBarHeight(context)+ "px\n" +
+ "Screen ActionBar Height: " + getActionBarHeight(context)+ "px\n" +
+ "Screen NavigationBar Height: " + getNavigationBarHeight(context)+ "px\n" +
+ "Screen Dpi: " + getDpi(context) + "\n" +
+ "Screen Density: " + getDensity(context) + "\n" +
+ "--------------------------";
+ }
+
+
+ /**
+ * 根据手机的分辨率从 dp 的单位 转成为 px(像素)
+ */
+ public static int dip2px(Context context, float dpValue) {
+ final float scale = context.getResources().getDisplayMetrics().density;
+ return (int) (dpValue * scale);
+ }
+
+ /** * 根据手机的分辨率从 px(像素) 的单位 转成为 dp */
+ public static int px2dip(Context context, float pxValue) {
+ final float scale = context.getResources().getDisplayMetrics().density;
+ return (int) (pxValue / scale);
+ }
+
+ /**
+ * Print screenInfo to logcat
+ */
+ public static void printScreenInfo(Context context) {
+ Log.d(TAG, getScreenInfo(context));
+ }
+}
diff --git a/PermissionManager/app/src/main/res/drawable-v24/ic_launcher_foreground.xml b/PermissionManager/app/src/main/res/drawable-v24/ic_launcher_foreground.xml
new file mode 100644
index 00000000..2b068d11
--- /dev/null
+++ b/PermissionManager/app/src/main/res/drawable-v24/ic_launcher_foreground.xml
@@ -0,0 +1,30 @@
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/drawable/ic_launcher_background.xml b/PermissionManager/app/src/main/res/drawable/ic_launcher_background.xml
new file mode 100644
index 00000000..07d5da9c
--- /dev/null
+++ b/PermissionManager/app/src/main/res/drawable/ic_launcher_background.xml
@@ -0,0 +1,170 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/PermissionManager/app/src/main/res/drawable/line.xml b/PermissionManager/app/src/main/res/drawable/line.xml
new file mode 100644
index 00000000..597142f2
--- /dev/null
+++ b/PermissionManager/app/src/main/res/drawable/line.xml
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/drawable/line_drawable.xml b/PermissionManager/app/src/main/res/drawable/line_drawable.xml
new file mode 100644
index 00000000..4f79f470
--- /dev/null
+++ b/PermissionManager/app/src/main/res/drawable/line_drawable.xml
@@ -0,0 +1,9 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/drawable/ripple_grey.xml b/PermissionManager/app/src/main/res/drawable/ripple_grey.xml
new file mode 100644
index 00000000..ac736de4
--- /dev/null
+++ b/PermissionManager/app/src/main/res/drawable/ripple_grey.xml
@@ -0,0 +1,6 @@
+
+//点击时波纹的颜色
+ //未点击时控件的背景(可以是图片,可以是颜色,也可以是drawable里的xml背景(比如圆角))
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/drawable/shape_wnd_grey_corner.xml b/PermissionManager/app/src/main/res/drawable/shape_wnd_grey_corner.xml
new file mode 100644
index 00000000..6bc80841
--- /dev/null
+++ b/PermissionManager/app/src/main/res/drawable/shape_wnd_grey_corner.xml
@@ -0,0 +1,9 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/drawable/thumb.xml b/PermissionManager/app/src/main/res/drawable/thumb.xml
new file mode 100644
index 00000000..0646431b
--- /dev/null
+++ b/PermissionManager/app/src/main/res/drawable/thumb.xml
@@ -0,0 +1,11 @@
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/drawable/thumb_drawable.xml b/PermissionManager/app/src/main/res/drawable/thumb_drawable.xml
new file mode 100644
index 00000000..a93b8b83
--- /dev/null
+++ b/PermissionManager/app/src/main/res/drawable/thumb_drawable.xml
@@ -0,0 +1,9 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/layout/activity_main.xml b/PermissionManager/app/src/main/res/layout/activity_main.xml
new file mode 100644
index 00000000..0e89ddd8
--- /dev/null
+++ b/PermissionManager/app/src/main/res/layout/activity_main.xml
@@ -0,0 +1,175 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/layout/select_app_recycler_item.xml b/PermissionManager/app/src/main/res/layout/select_app_recycler_item.xml
new file mode 100644
index 00000000..a52cd2d8
--- /dev/null
+++ b/PermissionManager/app/src/main/res/layout/select_app_recycler_item.xml
@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/PermissionManager/app/src/main/res/layout/select_app_wnd.xml b/PermissionManager/app/src/main/res/layout/select_app_wnd.xml
new file mode 100644
index 00000000..7b75eda3
--- /dev/null
+++ b/PermissionManager/app/src/main/res/layout/select_app_wnd.xml
@@ -0,0 +1,124 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/PermissionManager/app/src/main/res/layout/select_file_recycler_item.xml b/PermissionManager/app/src/main/res/layout/select_file_recycler_item.xml
new file mode 100644
index 00000000..355ce92a
--- /dev/null
+++ b/PermissionManager/app/src/main/res/layout/select_file_recycler_item.xml
@@ -0,0 +1,39 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/PermissionManager/app/src/main/res/layout/select_file_wnd.xml b/PermissionManager/app/src/main/res/layout/select_file_wnd.xml
new file mode 100644
index 00000000..4ab4231e
--- /dev/null
+++ b/PermissionManager/app/src/main/res/layout/select_file_wnd.xml
@@ -0,0 +1,95 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/PermissionManager/app/src/main/res/mipmap-anydpi-v26/ic_launcher.xml b/PermissionManager/app/src/main/res/mipmap-anydpi-v26/ic_launcher.xml
new file mode 100644
index 00000000..eca70cfe
--- /dev/null
+++ b/PermissionManager/app/src/main/res/mipmap-anydpi-v26/ic_launcher.xml
@@ -0,0 +1,5 @@
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/mipmap-anydpi-v26/ic_launcher_round.xml b/PermissionManager/app/src/main/res/mipmap-anydpi-v26/ic_launcher_round.xml
new file mode 100644
index 00000000..eca70cfe
--- /dev/null
+++ b/PermissionManager/app/src/main/res/mipmap-anydpi-v26/ic_launcher_round.xml
@@ -0,0 +1,5 @@
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/mipmap-hdpi/ic_launcher.webp b/PermissionManager/app/src/main/res/mipmap-hdpi/ic_launcher.webp
new file mode 100644
index 00000000..c209e78e
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-hdpi/ic_launcher.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-hdpi/ic_launcher_round.webp b/PermissionManager/app/src/main/res/mipmap-hdpi/ic_launcher_round.webp
new file mode 100644
index 00000000..b2dfe3d1
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-hdpi/ic_launcher_round.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-mdpi/ic_launcher.webp b/PermissionManager/app/src/main/res/mipmap-mdpi/ic_launcher.webp
new file mode 100644
index 00000000..4f0f1d64
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-mdpi/ic_launcher.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-mdpi/ic_launcher_round.webp b/PermissionManager/app/src/main/res/mipmap-mdpi/ic_launcher_round.webp
new file mode 100644
index 00000000..62b611da
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-mdpi/ic_launcher_round.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-xhdpi/ic_launcher.webp b/PermissionManager/app/src/main/res/mipmap-xhdpi/ic_launcher.webp
new file mode 100644
index 00000000..948a3070
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-xhdpi/ic_launcher.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-xhdpi/ic_launcher_round.webp b/PermissionManager/app/src/main/res/mipmap-xhdpi/ic_launcher_round.webp
new file mode 100644
index 00000000..1b9a6956
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-xhdpi/ic_launcher_round.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-xxhdpi/ic_launcher.webp b/PermissionManager/app/src/main/res/mipmap-xxhdpi/ic_launcher.webp
new file mode 100644
index 00000000..28d4b77f
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-xxhdpi/ic_launcher.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-xxhdpi/ic_launcher_round.webp b/PermissionManager/app/src/main/res/mipmap-xxhdpi/ic_launcher_round.webp
new file mode 100644
index 00000000..9287f508
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-xxhdpi/ic_launcher_round.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-xxxhdpi/ic_launcher.webp b/PermissionManager/app/src/main/res/mipmap-xxxhdpi/ic_launcher.webp
new file mode 100644
index 00000000..aa7d6427
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-xxxhdpi/ic_launcher.webp differ
diff --git a/PermissionManager/app/src/main/res/mipmap-xxxhdpi/ic_launcher_round.webp b/PermissionManager/app/src/main/res/mipmap-xxxhdpi/ic_launcher_round.webp
new file mode 100644
index 00000000..9126ae37
Binary files /dev/null and b/PermissionManager/app/src/main/res/mipmap-xxxhdpi/ic_launcher_round.webp differ
diff --git a/PermissionManager/app/src/main/res/values-night/themes.xml b/PermissionManager/app/src/main/res/values-night/themes.xml
new file mode 100644
index 00000000..d5b6cfa7
--- /dev/null
+++ b/PermissionManager/app/src/main/res/values-night/themes.xml
@@ -0,0 +1,16 @@
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/values/colors.xml b/PermissionManager/app/src/main/res/values/colors.xml
new file mode 100644
index 00000000..bbb834e9
--- /dev/null
+++ b/PermissionManager/app/src/main/res/values/colors.xml
@@ -0,0 +1,13 @@
+
+
+ #FFBB86FC
+ #FF6200EE
+ #FF3700B3
+ #FF03DAC5
+ #FF018786
+ #FF000000
+ #FFFFFFFF
+ #424242
+ #FF767676
+ #00000000
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/values/strings.xml b/PermissionManager/app/src/main/res/values/strings.xml
new file mode 100644
index 00000000..3c17a54a
--- /dev/null
+++ b/PermissionManager/app/src/main/res/values/strings.xml
@@ -0,0 +1,3 @@
+
+ PermissionManager
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/main/res/values/themes.xml b/PermissionManager/app/src/main/res/values/themes.xml
new file mode 100644
index 00000000..3a6641c8
--- /dev/null
+++ b/PermissionManager/app/src/main/res/values/themes.xml
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/PermissionManager/app/src/test/java/com/linux/permissionmanager/ExampleUnitTest.java b/PermissionManager/app/src/test/java/com/linux/permissionmanager/ExampleUnitTest.java
new file mode 100644
index 00000000..bd51fc00
--- /dev/null
+++ b/PermissionManager/app/src/test/java/com/linux/permissionmanager/ExampleUnitTest.java
@@ -0,0 +1,17 @@
+package com.linux.permissionmanager;
+
+import org.junit.Test;
+
+import static org.junit.Assert.*;
+
+/**
+ * Example local unit test, which will execute on the development machine (host).
+ *
+ * @see Testing documentation
+ */
+public class ExampleUnitTest {
+ @Test
+ public void addition_isCorrect() {
+ assertEquals(4, 2 + 2);
+ }
+}
\ No newline at end of file
diff --git a/PermissionManager/build.gradle b/PermissionManager/build.gradle
new file mode 100644
index 00000000..f757f23e
--- /dev/null
+++ b/PermissionManager/build.gradle
@@ -0,0 +1,5 @@
+// Top-level build file where you can add configuration options common to all sub-projects/modules.
+
+task clean(type: Delete) {
+ delete rootProject.buildDir
+}
\ No newline at end of file
diff --git a/PermissionManager/gradle.properties b/PermissionManager/gradle.properties
new file mode 100644
index 00000000..9a4c7cc9
--- /dev/null
+++ b/PermissionManager/gradle.properties
@@ -0,0 +1,23 @@
+# Project-wide Gradle settings.
+# IDE (e.g. Android Studio) users:
+# Gradle settings configured through the IDE *will override*
+# any settings specified in this file.
+# For more details on how to configure your build environment visit
+# http://www.gradle.org/docs/current/userguide/build_environment.html
+# Specifies the JVM arguments used for the daemon process.
+# The setting is particularly useful for tweaking memory settings.
+org.gradle.jvmargs=-Xmx2048m -Dfile.encoding=UTF-8
+# When configured, Gradle will run in incubating parallel mode.
+# This option should only be used with decoupled projects. More details, visit
+# http://www.gradle.org/docs/current/userguide/multi_project_builds.html#sec:decoupled_projects
+# org.gradle.parallel=true
+# AndroidX package structure to make it clearer which packages are bundled with the
+# Android operating system, and which are packaged with your app"s APK
+# https://developer.android.com/topic/libraries/support-library/androidx-rn
+android.useAndroidX=true
+# Automatically convert third-party libraries to use AndroidX
+android.enableJetifier=true
+# Enables namespacing of each library's R class so that its R class includes only the
+# resources declared in the library itself and none from the library's dependencies,
+# thereby reducing the size of the R class for that library
+android.nonTransitiveRClass=true
\ No newline at end of file
diff --git a/PermissionManager/gradle/wrapper/gradle-wrapper.jar b/PermissionManager/gradle/wrapper/gradle-wrapper.jar
new file mode 100644
index 00000000..e708b1c0
Binary files /dev/null and b/PermissionManager/gradle/wrapper/gradle-wrapper.jar differ
diff --git a/PermissionManager/gradle/wrapper/gradle-wrapper.properties b/PermissionManager/gradle/wrapper/gradle-wrapper.properties
new file mode 100644
index 00000000..5ac2865d
--- /dev/null
+++ b/PermissionManager/gradle/wrapper/gradle-wrapper.properties
@@ -0,0 +1,6 @@
+#Sat Feb 19 21:34:04 CST 2022
+distributionBase=GRADLE_USER_HOME
+distributionUrl=https\://services.gradle.org/distributions/gradle-7.2-bin.zip
+distributionPath=wrapper/dists
+zipStorePath=wrapper/dists
+zipStoreBase=GRADLE_USER_HOME
diff --git a/PermissionManager/gradlew b/PermissionManager/gradlew
new file mode 100644
index 00000000..4f906e0c
--- /dev/null
+++ b/PermissionManager/gradlew
@@ -0,0 +1,185 @@
+#!/usr/bin/env sh
+
+#
+# Copyright 2015 the original author or authors.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+##############################################################################
+##
+## Gradle start up script for UN*X
+##
+##############################################################################
+
+# Attempt to set APP_HOME
+# Resolve links: $0 may be a link
+PRG="$0"
+# Need this for relative symlinks.
+while [ -h "$PRG" ] ; do
+ ls=`ls -ld "$PRG"`
+ link=`expr "$ls" : '.*-> \(.*\)$'`
+ if expr "$link" : '/.*' > /dev/null; then
+ PRG="$link"
+ else
+ PRG=`dirname "$PRG"`"/$link"
+ fi
+done
+SAVED="`pwd`"
+cd "`dirname \"$PRG\"`/" >/dev/null
+APP_HOME="`pwd -P`"
+cd "$SAVED" >/dev/null
+
+APP_NAME="Gradle"
+APP_BASE_NAME=`basename "$0"`
+
+# Add default JVM options here. You can also use JAVA_OPTS and GRADLE_OPTS to pass JVM options to this script.
+DEFAULT_JVM_OPTS='"-Xmx64m" "-Xms64m"'
+
+# Use the maximum available, or set MAX_FD != -1 to use that value.
+MAX_FD="maximum"
+
+warn () {
+ echo "$*"
+}
+
+die () {
+ echo
+ echo "$*"
+ echo
+ exit 1
+}
+
+# OS specific support (must be 'true' or 'false').
+cygwin=false
+msys=false
+darwin=false
+nonstop=false
+case "`uname`" in
+ CYGWIN* )
+ cygwin=true
+ ;;
+ Darwin* )
+ darwin=true
+ ;;
+ MINGW* )
+ msys=true
+ ;;
+ NONSTOP* )
+ nonstop=true
+ ;;
+esac
+
+CLASSPATH=$APP_HOME/gradle/wrapper/gradle-wrapper.jar
+
+
+# Determine the Java command to use to start the JVM.
+if [ -n "$JAVA_HOME" ] ; then
+ if [ -x "$JAVA_HOME/jre/sh/java" ] ; then
+ # IBM's JDK on AIX uses strange locations for the executables
+ JAVACMD="$JAVA_HOME/jre/sh/java"
+ else
+ JAVACMD="$JAVA_HOME/bin/java"
+ fi
+ if [ ! -x "$JAVACMD" ] ; then
+ die "ERROR: JAVA_HOME is set to an invalid directory: $JAVA_HOME
+
+Please set the JAVA_HOME variable in your environment to match the
+location of your Java installation."
+ fi
+else
+ JAVACMD="java"
+ which java >/dev/null 2>&1 || die "ERROR: JAVA_HOME is not set and no 'java' command could be found in your PATH.
+
+Please set the JAVA_HOME variable in your environment to match the
+location of your Java installation."
+fi
+
+# Increase the maximum file descriptors if we can.
+if [ "$cygwin" = "false" -a "$darwin" = "false" -a "$nonstop" = "false" ] ; then
+ MAX_FD_LIMIT=`ulimit -H -n`
+ if [ $? -eq 0 ] ; then
+ if [ "$MAX_FD" = "maximum" -o "$MAX_FD" = "max" ] ; then
+ MAX_FD="$MAX_FD_LIMIT"
+ fi
+ ulimit -n $MAX_FD
+ if [ $? -ne 0 ] ; then
+ warn "Could not set maximum file descriptor limit: $MAX_FD"
+ fi
+ else
+ warn "Could not query maximum file descriptor limit: $MAX_FD_LIMIT"
+ fi
+fi
+
+# For Darwin, add options to specify how the application appears in the dock
+if $darwin; then
+ GRADLE_OPTS="$GRADLE_OPTS \"-Xdock:name=$APP_NAME\" \"-Xdock:icon=$APP_HOME/media/gradle.icns\""
+fi
+
+# For Cygwin or MSYS, switch paths to Windows format before running java
+if [ "$cygwin" = "true" -o "$msys" = "true" ] ; then
+ APP_HOME=`cygpath --path --mixed "$APP_HOME"`
+ CLASSPATH=`cygpath --path --mixed "$CLASSPATH"`
+
+ JAVACMD=`cygpath --unix "$JAVACMD"`
+
+ # We build the pattern for arguments to be converted via cygpath
+ ROOTDIRSRAW=`find -L / -maxdepth 1 -mindepth 1 -type d 2>/dev/null`
+ SEP=""
+ for dir in $ROOTDIRSRAW ; do
+ ROOTDIRS="$ROOTDIRS$SEP$dir"
+ SEP="|"
+ done
+ OURCYGPATTERN="(^($ROOTDIRS))"
+ # Add a user-defined pattern to the cygpath arguments
+ if [ "$GRADLE_CYGPATTERN" != "" ] ; then
+ OURCYGPATTERN="$OURCYGPATTERN|($GRADLE_CYGPATTERN)"
+ fi
+ # Now convert the arguments - kludge to limit ourselves to /bin/sh
+ i=0
+ for arg in "$@" ; do
+ CHECK=`echo "$arg"|egrep -c "$OURCYGPATTERN" -`
+ CHECK2=`echo "$arg"|egrep -c "^-"` ### Determine if an option
+
+ if [ $CHECK -ne 0 ] && [ $CHECK2 -eq 0 ] ; then ### Added a condition
+ eval `echo args$i`=`cygpath --path --ignore --mixed "$arg"`
+ else
+ eval `echo args$i`="\"$arg\""
+ fi
+ i=`expr $i + 1`
+ done
+ case $i in
+ 0) set -- ;;
+ 1) set -- "$args0" ;;
+ 2) set -- "$args0" "$args1" ;;
+ 3) set -- "$args0" "$args1" "$args2" ;;
+ 4) set -- "$args0" "$args1" "$args2" "$args3" ;;
+ 5) set -- "$args0" "$args1" "$args2" "$args3" "$args4" ;;
+ 6) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" ;;
+ 7) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" ;;
+ 8) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" "$args7" ;;
+ 9) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" "$args7" "$args8" ;;
+ esac
+fi
+
+# Escape application args
+save () {
+ for i do printf %s\\n "$i" | sed "s/'/'\\\\''/g;1s/^/'/;\$s/\$/' \\\\/" ; done
+ echo " "
+}
+APP_ARGS=`save "$@"`
+
+# Collect all arguments for the java command, following the shell quoting and substitution rules
+eval set -- $DEFAULT_JVM_OPTS $JAVA_OPTS $GRADLE_OPTS "\"-Dorg.gradle.appname=$APP_BASE_NAME\"" -classpath "\"$CLASSPATH\"" org.gradle.wrapper.GradleWrapperMain "$APP_ARGS"
+
+exec "$JAVACMD" "$@"
diff --git a/PermissionManager/gradlew.bat b/PermissionManager/gradlew.bat
new file mode 100644
index 00000000..107acd32
--- /dev/null
+++ b/PermissionManager/gradlew.bat
@@ -0,0 +1,89 @@
+@rem
+@rem Copyright 2015 the original author or authors.
+@rem
+@rem Licensed under the Apache License, Version 2.0 (the "License");
+@rem you may not use this file except in compliance with the License.
+@rem You may obtain a copy of the License at
+@rem
+@rem https://www.apache.org/licenses/LICENSE-2.0
+@rem
+@rem Unless required by applicable law or agreed to in writing, software
+@rem distributed under the License is distributed on an "AS IS" BASIS,
+@rem WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@rem See the License for the specific language governing permissions and
+@rem limitations under the License.
+@rem
+
+@if "%DEBUG%" == "" @echo off
+@rem ##########################################################################
+@rem
+@rem Gradle startup script for Windows
+@rem
+@rem ##########################################################################
+
+@rem Set local scope for the variables with windows NT shell
+if "%OS%"=="Windows_NT" setlocal
+
+set DIRNAME=%~dp0
+if "%DIRNAME%" == "" set DIRNAME=.
+set APP_BASE_NAME=%~n0
+set APP_HOME=%DIRNAME%
+
+@rem Resolve any "." and ".." in APP_HOME to make it shorter.
+for %%i in ("%APP_HOME%") do set APP_HOME=%%~fi
+
+@rem Add default JVM options here. You can also use JAVA_OPTS and GRADLE_OPTS to pass JVM options to this script.
+set DEFAULT_JVM_OPTS="-Xmx64m" "-Xms64m"
+
+@rem Find java.exe
+if defined JAVA_HOME goto findJavaFromJavaHome
+
+set JAVA_EXE=java.exe
+%JAVA_EXE% -version >NUL 2>&1
+if "%ERRORLEVEL%" == "0" goto execute
+
+echo.
+echo ERROR: JAVA_HOME is not set and no 'java' command could be found in your PATH.
+echo.
+echo Please set the JAVA_HOME variable in your environment to match the
+echo location of your Java installation.
+
+goto fail
+
+:findJavaFromJavaHome
+set JAVA_HOME=%JAVA_HOME:"=%
+set JAVA_EXE=%JAVA_HOME%/bin/java.exe
+
+if exist "%JAVA_EXE%" goto execute
+
+echo.
+echo ERROR: JAVA_HOME is set to an invalid directory: %JAVA_HOME%
+echo.
+echo Please set the JAVA_HOME variable in your environment to match the
+echo location of your Java installation.
+
+goto fail
+
+:execute
+@rem Setup the command line
+
+set CLASSPATH=%APP_HOME%\gradle\wrapper\gradle-wrapper.jar
+
+
+@rem Execute Gradle
+"%JAVA_EXE%" %DEFAULT_JVM_OPTS% %JAVA_OPTS% %GRADLE_OPTS% "-Dorg.gradle.appname=%APP_BASE_NAME%" -classpath "%CLASSPATH%" org.gradle.wrapper.GradleWrapperMain %*
+
+:end
+@rem End local scope for the variables with windows NT shell
+if "%ERRORLEVEL%"=="0" goto mainEnd
+
+:fail
+rem Set variable GRADLE_EXIT_CONSOLE if you need the _script_ return code instead of
+rem the _cmd.exe /c_ return code!
+if not "" == "%GRADLE_EXIT_CONSOLE%" exit 1
+exit /b 1
+
+:mainEnd
+if "%OS%"=="Windows_NT" endlocal
+
+:omega
diff --git a/PermissionManager/settings.gradle b/PermissionManager/settings.gradle
new file mode 100644
index 00000000..1f40e56f
--- /dev/null
+++ b/PermissionManager/settings.gradle
@@ -0,0 +1,20 @@
+pluginManagement {
+ repositories {
+ gradlePluginPortal()
+ google()
+ mavenCentral()
+ }
+ plugins {
+ id 'com.android.application' version '7.1.0-alpha11'
+ id 'com.android.library' version '7.1.0-alpha11'
+ }
+}
+dependencyResolutionManagement {
+ repositoriesMode.set(RepositoriesMode.FAIL_ON_PROJECT_REPOS)
+ repositories {
+ google()
+ mavenCentral()
+ }
+}
+rootProject.name = "PermissionManager"
+include ':app'
diff --git a/README.md b/README.md
new file mode 100644
index 00000000..8271fb11
--- /dev/null
+++ b/README.md
@@ -0,0 +1,53 @@
+# SKRoot - SuperKernelRoot - Linux内核级完美隐藏ROOT演示
+新一代SKRoot,挑战全网root检测手段,跟面具完全不同思路,摆脱面具被检测的弱点,完美隐藏root功能,全程不需要暂停SELinux,实现真正的SELinux 0%触碰,通用性强,通杀所有内核,不需要内核源码,直接patch内核,兼容安卓APP直接JNI调用,稳定、流畅、不闪退。
+## 功能列表:
+#### 1.测试ROOT权限
+#### 2.执行ROOT命令
+#### 3.执行原生内核命令
+#### 4.安装部署su
+#### 5.注入su到指定进程
+#### 6.完全卸载清理su
+#### 7.寄生目标APP
+
+## 效果:
+* **实验设备包括:红米K20\K30\K40\K50\K60、小米8\9\10\11\12\13、小米平板5\6、红魔5\6\7、联想、三星、一加、ROG2\3等,支持型号非常多。测试结果显示,SKRoot能够在所支持设备上非常稳定的运行。**
+* **过市面上所有主流APP的ROOT检测,如农业XX、交X12XX3等...**
+* **无需理会谷歌GKI**
+* **让所有的ROOT检测手段都回归尘土吧,愿世界迎来一个美好的ROOT时代!**
+
+
+
+
+
+## 功能备注:
+1.APP应用程序拿到ROOT权限的唯一方法就是得到ROOT密匙,此密匙为48位的随机字符串,安全可靠。
+
+2.其中【**注入su到指定进程**】**只支持授权su到64位的APP**,老式32位APP不再进行支持,因市面上几乎所有APP都是64位,例如MT文件管理器、Root Explorer文件管理器等等。
+
+## 使用流程:
+1.将内核文件拖拽置`patch_kernel_root.exe`即可一键自动化流程补丁内核,同时会自动生成ROOT密匙。
+
+2.编译并启动`PermissionManager`或者`testRoot`,输入ROOT密匙值,开始享受舒爽的ROOT环境。
+
+## 更新日志:
+**2.0:**
+ * **1.新增seccomp补丁代码**
+ * **2.新增寄生目标功能**
+ * **3.新增一键自动化流程补丁内核功能**
+ * **4.修复Linux 3.X老内核兼容问题**
+ * **5.修复Linux 5.10、5.15无法开机问题**
+
+**2.1:**
+ * **1.新增永久授权su功能**
+ * **2.修复一些bug**
+
+## 问题排查:
+如发现第三方应用程序依然有侦测行为,请按照以下步骤进行排查:
+* **内核必须保证是基于官方原版进行修改,而非自行编译或使用第三方源码编译。**
+* **如果你曾经使用过Magisk,你应该先将手机完全刷机,因为Magisk可能会残留日志文件等信息。**
+* **不要安装需要ROOT权限的工具,或涉及系统环境检测的应用,如冰箱、黑洞、momo和密匙认证等。这些应用的存在可能会被用作证据,推断你的设备已获取ROOT权限。以冰箱为例,这款应用需要ROOT权限才能运行,如果你的设备上安装了冰箱,那就可能被用来佐证你的设备处于ROOT环境。实际测试中我们发现,"X租号"APP就会进行此类环境检测。因此,我们强烈建议不安装这些工具。若确需使用,请在使用结束后立即卸载,以降低异常环境判断风险。**
+* **Android APP应用可能会被检测其特征。这里我们仅提供APP调用的教学,在实际使用中,请尽量隐藏应用。可以考虑使用寄生功能,即将你的应用功能嵌入或附加到另一个无害或常见的应用内,这样可以有效地避免检测。如果这仍然不能满足隐藏的需求,你还可以考虑卸载应用,改用纯命令行方式调用的testRoot.cpp。**
+* **在老旧版本的Android系统中,应用程序无需任何权限即可访问/data/local/tmp目录。在这种情况下,你应该升级Android系统版本,或者卸载SU。**
+* **如果你的手机在解锁后会发出警报,你需要自行解决这个问题,因为它与SKRoot无关。**
+* **检查应用程序是否在检测Bootloader锁,而不是ROOT权限。如果是这样,你应该安装SKRoot的隐藏Bootloader锁模块。**
+* **请检查SELinux状态是否被恶意软件禁用。**
diff --git a/ScreenCap/1.png b/ScreenCap/1.png
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diff --git a/ScreenCap/3.png b/ScreenCap/3.png
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diff --git a/ScreenCap/4.png b/ScreenCap/4.png
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diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/CREDITS.TXT b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/CREDITS.TXT
new file mode 100644
index 00000000..f2581f34
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/CREDITS.TXT
@@ -0,0 +1,79 @@
+This file credits all the contributors of the Capstone engine project.
+
+Key developers
+==============
+1. Nguyen Anh Quynh
+ - Core engine
+ - Bindings: Python, Ruby, OCaml, Java, C#
+
+2. Tan Sheng Di
+ - Bindings: Ruby
+
+3. Ben Nagy
+ - Bindings: Ruby, Go
+
+4. Dang Hoang Vu
+ - Bindings: Java
+
+
+Beta testers (in random order)
+==============================
+Pancake
+Van Hauser
+FX of Phenoelit
+The Grugq, The Grugq <-- our hero for submitting the first ever patch!
+Isaac Dawson, Veracode Inc
+Patroklos Argyroudis, Census Inc. (http://census-labs.com)
+Attila Suszter
+Le Dinh Long
+Nicolas Ruff
+Gunther
+Alex Ionescu, Winsider Seminars & Solutions Inc.
+Snare
+Daniel Godas-Lopez
+Joshua J. Drake
+Edgar Barbosa
+Ralf-Philipp Weinmann
+Hugo Fortier
+Joxean Koret
+Bruce Dang
+Andrew Dunham
+
+
+Contributors (in no particular order)
+=====================================
+(Please let us know if you want to have your name here)
+
+Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
+Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
+Daniel Pistelli: Cmake support.
+Peter Hlavaty: integrate Capstone for Windows kernel drivers.
+Guillaume Jeanne: Ocaml binding.
+Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features.
+David Martínez Moreno & Hilko Bengen: Debian package.
+Félix Cloutier: Xcode project.
+Benoit Lecocq: OpenBSD package.
+Christophe Avoinne (Hlide): Improve memory management for better performance.
+Michael Cohen & Nguyen Tan Cong: Python module installer.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.
+Xipiter LLC: Capstone logo redesigned.
+Satoshi Tanda: Support Windows kernel driver.
+Tang Yuhang: cstool.
+Andrew Dutcher: better Python setup.
+Ruben Boonen: PowerShell binding.
+David Zimmer: VB6 binding.
+Philippe Antoine: Integration with oss-fuzz and various fixes.
+Bui Dinh Cuong: Explicit registers accessed for Arm64.
+Vincent Bénony: Explicit registers accessed for X86.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.
+Daniel Collin & Nicolas Planel: M68K architecture.
+Pranith Kumar: Explicit registers accessed for Arm64.
+Xipiter LLC: Capstone logo redesigned.
+Satoshi Tanda: Support Windows kernel driver.
+Koutheir Attouchi: Support for Windows CE.
+Fotis Loukos: TMS320C64x architecture.
+Wolfgang Schwotzer: M680X architecture.
+Philippe Antoine: Integration with oss-fuzz and various fixes.
+Stephen Eckels (stevemk14ebr): x86 encoding features
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/ChangeLog b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/ChangeLog
new file mode 100644
index 00000000..9336bc9a
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/ChangeLog
@@ -0,0 +1,772 @@
+This file details the changelog of Capstone.
+
+----------------------------
+Version 4.0.2: May 8th, 2020
+
+
+[ Core ]
+
+- Windows kernel-mode driver support
+- Fix installation path on FreeBSD and DragonFly
+
+
+[ cstool ]
+
+- Add armv8, ppc32 & thumbv8 modes
+- Print instruction ID
+
+
+[ X86 ]
+
+- Support CS_OPT_UNSIGNED for ATT syntax
+- Fix operand size for some instructions
+- Fix LOCK prefixes
+- Recognize xacquire/xrelease prefix
+- Fix call/jmp access mode of mem operand
+- Add ENDBR32, ENDBR64 to reduce mode
+- Other minor fixes
+
+
+[ ARM64 ]
+
+- Support CS_OPT_UNSIGNED
+- Fix register access flags for memory instructions
+- Fix UMOV vess
+
+
+[ ARM ]
+
+- Update writeback for STR_POST_REG
+
+
+[ M68K ]
+
+- Store correct register value in op.reg_pair
+
+
+[ PowerPC ]
+
+- BDZLA is absolute branch
+
+
+[ SystemZ ]
+
+- Fix truncated 64bit imm operand
+- Fix base/index printing
+
+
+[ Python ]
+
+- Fix skipdata struct being destroyed
+- Add __repr__ for capstone.CsInsn
+
+
+[ Java ]
+
+- Fix Java bindings to use pointers instead of longs
+
+
+[ Ocaml ]
+
+- Fix x86_op record
+
+
+---------------------------------
+Version 4.0.1: January 10th, 2019
+
+
+[ Core ]
+
+- Fix some issues for packaging (Debian, Gentoo).
+- Better support for building with Mingw.
+- cstool has new option -s to turn on skipdata mode.
+- cstool -v now report build settings of the core.
+- Add suite/capstone_get_setup.c so users can integrate with their own code
+ to retrieve Capstone settings at build time.
+
+
+[ Arm ]
+
+- Fix 4.0 regression: the `tbh [r0, r1, lsl #1]` instruction sets the operand.shift.value back again (see #1317)
+- Remove ARM_REG_PC group for BX instruction.
+
+
+[ X86 ]
+
+- Fix: endbr32 and endbr64 instructions are now properly decoded in both CS_MODE_32 and CS_MODE_64 (#1129)
+
+
+[ M680X ]
+
+- Fix some issues reported by clang-analyzer (#1329).
+
+
+[ Python ]
+
+- Fix skipdata setup.
+- Add getter/setter for skipdata_mnem, skipdata_callback.
+
+
+---------------------------------
+Version 4.0: December 18th, 2018
+
+
+[ Core ]
+
+- New APIs: cs_regs_access()
+- Add new options for cs_option(): CS_OPT_MNEMONIC & CS_OPT_UNSIGNED & CS_OPT_SYNTAX_MASM.
+- Various updates & bugfixes for all architectures.
+- Add 4 new architectures: EVM, M68K, M680X & TMS320C64x.
+- Add new group types: CS_GRP_PRIVILEGE & CS_GRP_BRANCH_RELATIVE.
+- Add new error types: CS_ERR_X86_MASM.
+
+
+[ X86 ]
+
+- Add XOP code condition type in x86_xop_cc.
+- Add some info on encoding to cs_x86 in cs_x86_encoding.
+- Add register flags update in cs_x86.{eflags, fpu_flags}
+- Change cs_x86.disp type from int32_t to int64_t.
+- Add new groups: X86_GRP_VM & X86_GRP_FPU.
+- Lots of new instructions (AVX)
+
+
+[ ARM64 ]
+
+- Add instruction ARM64_INS_NEGS & ARM64_INS_NGCS.
+
+
+[ Mips ]
+
+- Add mode CS_MODE_MIPS2.
+
+
+[ PPC ]
+
+- Change cs_ppc_op.imm type from int32_t to int64_t.
+- Add new groups: PPC_GRP_ICBT, PPC_GRP_P8ALTIVEC, PPC_GRP_P8VECTOR & PPC_GRP_QPX.
+- Lots of new instructions (QPX among them)
+
+
+[ Sparc ]
+
+- Change cs_sparc_op.imm type from int32_t to int64_t.
+
+
+[ Binding ]
+
+- New bindings: PowerShell & VB6
+
+
+---------------------------------
+Version 3.0.5: July 18th, 2018
+
+
+[ Core ]
+
+- Fix the include path for Android builds when building cstool.
+- Add posibility to disable universal build for Mac OS.
+- cstool: Separate instruction bytes by spaces.
+- Fix code path of pkg-config in Cmake.
+- Update XCode project for XCode 9.1.
+- Add Cortex-M support to cstool.
+- Cmake forces to be build using MT with MSVC.
+- Better support for Mac OS kernel.
+
+
+[ X86 ]
+
+- Fix some issues in handling EVEX & VEX3 instructions.
+- Fix immediate operand for AND instruction in ATT mode.
+- Fix ATT syntax when imm operand is 0.
+- Better handle XACQUIRE/XRELEASE.
+- Fix imm operand of RETF.
+
+
+[ ARM ]
+
+- Fix an integer overlow bug.
+
+
+[ ARM64 ]
+
+- Bug fix for incorrect operand type in certain load/store instructions.
+
+
+[ Mips ]
+
+- Mode CS_MODE_MIPS32R6 automatically sets CS_MODE_32
+
+
+[ PPC ]
+
+- Fix endian check.
+
+
+[ Sparc ]
+
+- Fix an integer overlow bug.
+
+
+[ SystemZ ]
+
+- Fix an integer overlow bug.
+
+
+[ Python binding ]
+
+- Raise error on accessing irrelevant data fields if skipdata & detail modes are enable.
+
+
+---------------------------------
+Version 3.0.5-rc3: July 31st, 2017
+
+
+[ Core ]
+
+- Fix compilation for MacOS kernel extension
+- cstool to support armbe and arm64be modes
+- Add nmake.bat for Windows build
+- Fix an integer overflow for Windows kernel driver
+- Support to embedded Capstone into MacOS kernel
+- cstool: fix mips64 mode
+- Fix a compiling error in MS Visual Studio 2015
+- Install pkgconfig file with CMake build
+- Fix SOVERSION property of CMake build
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+- Fix MingW build
+- Better handle CMake installation for Linux 64bit
+
+
+[ X86 ]
+
+- Support BND prefix of Intel MPX extension
+- Correct operand size for CALL/JMP in 64bit mode with prefix 0x66
+- LOCK NOP is a valid instruction
+- Fix ATT syntax for instruction with zero offset segment register
+- LES/LDS are invalid in 64bit mode
+- Fix number of operands for some MOV instructions
+
+
+[ ARM ]
+
+- Fix POP reg to update SP register
+- Update flags for UADD8 instruction
+
+
+[ ARM64 ]
+
+- Better performance with new lookup table
+- Handle system registers added in ARMv8.1/2
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ Visual Basic binding ]
+
+- New binding
+
+---------------------------------
+Version 3.0.5-rc2: March 2nd, 2017
+
+
+[ Core ]
+
+- Fix build for Visual Studio 2012
+- Fix X86_REL_ADDR macro
+- Add CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA
+- Better support for embedding Capstone into Windows kernel drivers
+- Support to embedded Capstone into MacOS kernel
+- Support MacOS 10.11 and up
+- Better support for Cygwin
+- Support build packages for FreeBSD & DragonflyBSD
+- Add a command-line tool "cstool"
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+
+
+[ X86 ]
+
+- Some random 16-bit code can be handled wrongly.
+- Remove abundant operand type X86_OP_FP
+- Fix instructions MOVQ, LOOP, LOOPE, LOOPNE, CALL/JMP rel16, REPNE LODSD, MOV *AX, MOFFS, FAR JMP/CALL
+- Add X86_REG_EFLAGS for STC and STD
+- Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT
+- Rename registers ST0-ST7 to be consistent with asm output
+
+
+[ ARM ]
+
+- Properly handle IT instruction
+- Fix LDRSB
+- Fix writeback for LDR
+- Fix Thumb BigEndian setup
+
+
+[ ARM64 ]
+
+- Fix arith extender
+- Fix writeback for LDR
+- Rename enum arm64_mrs_reg to arm64_sysreg
+
+
+[ PowerPC ]
+
+- Print 0 offset for memory operand
+
+
+[ Sparc ]
+
+- Fix POPC instruction
+
+
+[ Python binding ]
+
+- Better PyPy support
+- Add __version__
+- Better support for Python 3
+- Fix CS_SKIPDATA_CALLBACK prototype
+- Cast skipdata function inside binding to simplify the API
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ PowerShell ]
+
+- New binding
+
+---------------------------------
+Version 3.0.4: July 15th, 2015
+
+
+[ Library ]
+
+- Improve cross-compile for Android using Android NDK.
+- Support cross-compile for AArch64 Android (with Linux GCC).
+- Removed osxkernel_inttypes.h that is incompatible with BSD license.
+- Make it possible to compile with CC having a space inside (like "ccache gcc").
+
+
+[ X86 ]
+
+- Fix a null pointer dereference bug on handling code with special prefixes.
+- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
+- Print immediate operand in positive form in some algorithm instructions.
+- Properly decode some SSE instructions.
+
+
+[ PowerPC ]
+
+- Fixed a memory corruption bug.
+- Fixed a memory corruption bug for the engine built in DIET mode.
+
+
+[ Mips ]
+
+- Fixed instruction ID of SUBU instruction.
+- Fixed a memory corruption bug.
+
+
+[ Arm ]
+
+- Fixed a memory corruption bug on IT instruction.
+
+
+[ XCore ]
+
+- Fixed a memory corruption bug when instruction has a memory operand.
+
+
+[ Python ]
+
+- Support Virtualenv.
+- setup.py supports option --user if not in a virtualenv to allow for local usage.
+- Properly handle the destruction of Cs object in the case the shared library
+ was already unloaded.
+
+---------------------------------
+Version 3.0.3: May 08th, 2015
+
+
+[ Library ]
+
+- Support to embed into Mac OS X kernel extensions.
+- Now it is possible to compile Capstone with older C compilers, such as
+ GCC 4.8 on Ubuntu 12.04.
+- Add "test_iter" to MSVC project.
+
+
+[ X86 ]
+
+- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
+ $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
+ "rcll %edx").
+- CMPXCHG16B is a valid instruction with LOCK prefix.
+- Fixed a segfault on the input of 0xF3.
+
+
+[ Arm ]
+
+- BLX instruction modifies PC & LR registers.
+
+
+[ Sparc ]
+
+- Improved displacement decoding for sparc banching instructions.
+
+
+[ Python binding ]
+
+- Fix for Cython so it can properly initialize.
+- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
+- Properly support compile with Cygwin & install binding (setup.py).
+
+---------------------------------
+Version 3.0.2: March 11th, 2015
+
+
+[ Library ]
+
+- On *nix, only export symbols that are part of the API (instead of all
+ the internal symbols).
+
+
+[ X86 ]
+
+- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
+- Fix implicit registers read/written & instruction groups of some instructions.
+- More flexible on the order of prefixes, so better handle some tricky
+ instructions.
+- REPNE prefix can go with STOS & MOVS instructions.
+- Fix a compilation bug for X86_REDUCE mode.
+- Fix operand size of instructions with operand PTR []
+
+
+[ Arm ]
+
+- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
+- Fix a bug on handling the If-Then block.
+
+
+[ Mips ]
+
+- Sanity check for the input size for MIPS64 mode.
+
+
+[ MSVC ]
+
+- Compile capstone.dll with static runtime MSVCR built in.
+
+
+[ Python binding ]
+
+- Fix a compiling issue of Cython binding with gcc 4.9.
+
+---------------------------------
+Version 3.0.1: February 03rd, 2015
+
+[ X86 ]
+
+- Properly handle LOCK, REP, REPE & REPNE prefixes.
+- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
+- Print LJUMP/LCALL without * as prefix for Intel syntax.
+- Handle REX prefix properly for segment/MMX related instructions (x86_64).
+- Instruction with length > 15 is consider invalid.
+- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
+ FSTP, FSTPNCE, NOP.
+- Handle some tricky code for some X86_64 instructions with REX prefix.
+- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
+- MOV32ms & MOV32sm should reference word rather than dword.
+
+
+[ Arm64 ]
+
+- BL & BLR instructions do not read SP register.
+- Print absolute (rather than relative) address for instructions B, BL,
+ CBNZ, ADR.
+
+
+[ Arm ]
+
+- Instructions ADC & SBC do not update flags.
+- BL & BLX do not read SP, but PC register.
+- Alias LDR instruction with operands [sp], 4 to POP.
+- Print immediate operand of MVN instruction in positive hexadecimal form.
+
+
+[ PowerPC ]
+
+- Fix some compilation bugs when DIET mode is enable.
+- Populate SLWI/SRWI instruction details with SH operand.
+
+
+[ Python binding ]
+
+- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
+- Fixed a memory leak for Cython disasm functions when we immaturely quit
+ the enumeration of disassembled instructions.
+- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
+ at the same time.
+- Fix a memory leaking bug when when we stop enumeration over the disassembled
+ instructions prematurely.
+- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
+
+---------------------------------
+Version 3.0: November 19th, 2014
+
+[ API ]
+
+- New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials.
+- Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but
+ marked obsolete to be removed in future)
+- Support SKIPDATA mode, so Capstone can jump over unknown data and keep going
+ from the next legitimate instruction. See docs/README for tutorials.
+- More details provided in cs_detail struct for all architectures.
+- API version was bumped to 3.0.
+
+
+[ Bindings ]
+
+- Python binding supports Python3 (besides Python2).
+- Support Ocaml binding.
+- Java: add close() method to be used to deinitialize a Capstone object when
+ no longer use it.
+
+
+[ Architectures ]
+
+- New architectures: Sparc, SystemZ & XCore.
+- Important bugfixes for Arm, Arm64, Mips, PowerPC & X86.
+- Support more instructions for Arm, Arm64, Mips, PowerPC & X86.
+- Always expose absolute addresses rather than relative addresses (Arm, Arm64,
+ Mips, PPC, Sparc, X86).
+- Use common instruction operand types REG, IMM, MEM & FP across all
+ architectures (to enable cross-architecture analysis).
+- Use common instruction group types across all architectures (to enable
+ cross-architecture analysis).
+
+
+[ X86 ]
+
+- X86 engine is mature & handles all the malware tricks (that we are aware of).
+- Added a lot of new instructions (such as AVX512, 3DNow, etc).
+- Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE.
+- Print immediate in positive form & hexadecimal for AND/OR/XOR instructions.
+- More friendly disassembly for JMP16i (in the form segment:offset)
+
+
+[ Mips ]
+
+- Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) &
+ MipsGP64 (CS_MODE_MIPSGP64).
+- Removed the ABI-only mode CS_MODE_N64.
+- New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 &
+ CS_MODE_64).
+
+
+[ ARM ]
+
+- Support new mode CS_MODE_V8 for Armv8 A32 encodings.
+- Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions
+
+
+[ ARM64 ]
+
+- Print immediate in hexadecimal for AND/ORR/EOR/TST instructions.
+
+
+[ PowerPC ]
+
+- Do not print a dot in front of absolute address.
+
+
+[ Other features ]
+
+- Support for Microsoft Visual Studio (so enable Windows native compilation).
+- Support CMake compilation.
+- Cross-compile for Android.
+- Build libraries/tests using XCode project
+- Much faster, while consuming less memory for all architectures.
+
+---------------------------------
+Version 2.1.2: April 3rd, 2014
+
+This is a stable release to fix some bugs deep in the core. There is no update
+to any architectures or bindings, so bindings version 2.1 can be used with this
+version 2.1.2 just fine.
+
+[ Core changes]
+
+- Support cross-compilation for all iDevices (iPhone/iPad/iPod).
+- X86: do not print memory offset in negative form.
+- Fix a bug in X86 when Capstone cannot handle short instruction.
+- Print negative number above -9 without prefix 0x (arm64, mips, arm).
+- Correct the SONAME setup for library versioning (Linux, *BSD, Solaris).
+- Set library versioning for dylib of OSX.
+
+---------------------------------
+Version 2.1.1: March 13th, 2014
+
+This is a stable release to fix some bugs deep in the core. There is no update
+to any architectures or bindings, so bindings version 2.1 can be used with this
+version 2.1.1 just fine.
+
+[ Core changes]
+
+- Fix a buffer overflow bug in Thumb mode (ARM). Some special input can
+ trigger this flaw.
+- Fix a crash issue when embedding Capstone into OSX kernel. This should
+ also enable Capstone to be embedded into other systems with limited stack
+ memory size such as Linux kernel or some firmwares.
+- Use a proper SONAME for library versioning (Linux).
+
+---------------------------------
+Version 2.1: March 5th, 2014
+
+[ API changes ]
+
+- API version has been bumped to 2.1.
+- Change prototype of cs_close() to be able to invalidate closed handle.
+ See http://capstone-engine.org/version_2.1_API.html for more information.
+- Extend cs_support() to handle more query types, not only about supported
+ architectures. This change is backward compatible, however, so existent code
+ do not need to be modified to support this.
+- New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of
+ the engine.
+- New error code CS_ERR_DIET to report errors about newly added diet mode.
+- New error code CS_ERR_VERSION to report issue of incompatible versions between
+ bindings & core engine.
+
+
+[ Core changes ]
+
+- On memory usage, Capstone uses about 40% less memory, while still faster
+ than version 2.0.
+- All architectures are much smaller: binaries size reduce at least 30%.
+ Especially, X86-only binary reduces from 1.9MB to just 720KB.
+- Support "diet" mode, in which engine size is further reduced (by around 40%)
+ for embedding purpose. The price to pay is that we have to sacrifice some
+ non-critical data fields. See http://capstone-engine.org/diet.html for more
+ details.
+
+
+[ Architectures ]
+
+- Update all 5 architectures to fix bugs.
+- PowerPC:
+ - New instructions: FMR & MSYNC.
+- Mips:
+ - New instruction: DLSA
+- X86:
+ - Properly handle AVX-512 instructions.
+ - New instructions: PSETPM, SALC, INT1, GETSEC.
+ - Fix some memory leaking issues in case of prefixed instructions such
+ as LOCK, REP, REPNE.
+
+
+[ Python binding ]
+
+- Verify the core version at initialization time. Refuse to run if its version
+ is different from the core's version.
+- New API disasm_lite() added to Cs class. This light API only returns tuples of
+ (address, size, mnemonic, op_str), rather than list of CsInsn objects. This
+ improves performance by around 30% in some benchmarks.
+- New API version_bind() returns binding's version, which might differ from
+ the core's API version if the binding is out-of-date.
+- New API debug() returns information on Cython support, diet status & archs
+ compiled in.
+- Fixed some memory leaking bugs for Cython binding.
+- Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups.
+- Support diet mode.
+
+
+[ Java binding ]
+
+- Fix some memory leaking bugs.
+- New API version() returns combined version.
+- Support diet mode.
+- Better support for detail option.
+
+
+[ Miscellaneous ]
+
+- make.sh now can uninstall the core engine. This is done with:
+
+ $ sudo ./make.sh uninstall
+
+----------------------------------
+Version 2.0: January 22nd, 2014
+
+Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
+
+[ API changes ]
+
+- API version has been bumped to 2.0 (see cs_version() API)
+- New API cs_strerror(errno) returns a string describing error code given
+ in its only argument.
+- cs_version() now returns combined version encoding both major & minor versions.
+- New option CS_OPT_MODE allows to change engine’s mode at run-time with
+ cs_option().
+- New option CS_OPT_MEM allows to specify user-defined functions for dynamically
+ memory management used internally by Capstone. This is useful to embed Capstone
+ into special environments such as kernel or firware.
+- New API cs_support() can be used to check if this lib supports a particular
+ architecture (this is necessary since we now allow to choose which architectures
+ to compile in).
+- The detail option is OFF by default now. To get detail information, it should be
+ explicitly turned ON. The details then can be accessed using cs_insn.detail
+ pointer (to newly added structure cs_detail)
+
+
+[ Core changes ]
+
+- On memory usage, Capstone uses much less memory, but a lot faster now.
+- User now can choose which architectures to be supported by modifying config.mk
+ before compiling/installing.
+
+
+[ Architectures ]
+
+- Arm
+ - Support Big-Endian mode (besides Little-Endian mode).
+ - Support friendly register, so instead of output sub "r12,r11,0x14",
+ we have "sub ip,fp,0x14".
+- Arm64: support Big-Endian mode (besides Little-Endian mode).
+- PowerPC: newly added.
+- Mips: support friendly register, so instead of output "srl $2,$1,0x1f",
+ we have "srl $v0,$at,0x1f".
+- X86: bug fixes.
+
+
+[ Python binding ]
+
+- Python binding is vastly improved in performance: around 3 ~ 4 times faster
+ than in 1.0.
+- Cython support has been added, which can further speed up over the default
+ pure Python binding (up to 30% in some cases)
+- Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list)
+ to return succesfully disassembled instructions. This improves the performance
+ and reduces memory usage.
+
+
+[ Java binding ]
+
+- Better performance & bug fixes.
+
+
+[ Miscellaneous ]
+
+- Fixed some installation issues with Gentoo Linux.
+- Capstone now can easily compile/install on all *nix, including Linux, OSX,
+ {Net, Free, Open}BSD & Solaris.
+
+----------------------------------
+[Version 1.0]: December 18th, 2013
+
+- Initial public release.
+
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/LICENSE.TXT b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/LICENSE.TXT
new file mode 100644
index 00000000..0dabdc74
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/LICENSE.TXT
@@ -0,0 +1,31 @@
+This is the software license for Capstone disassembly framework.
+Capstone has been designed & implemented by Nguyen Anh Quynh
+
+See http://www.capstone-engine.org for further information.
+
+Copyright (c) 2013, COSEINC.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+* Neither the name of the developer(s) nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/LICENSE_LLVM.TXT b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/LICENSE_LLVM.TXT
new file mode 100644
index 00000000..66d6647f
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/LICENSE_LLVM.TXT
@@ -0,0 +1,71 @@
+==============================================================================
+LLVM Release License
+==============================================================================
+University of Illinois/NCSA
+Open Source License
+
+Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign.
+All rights reserved.
+
+Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+==============================================================================
+Copyrights and Licenses for Third Party Software Distributed with LLVM:
+==============================================================================
+The LLVM software contains code written by third parties. Such software will
+have its own individual LICENSE.TXT file in the directory in which it appears.
+This file will describe the copyrights, license, and restrictions which apply
+to that code.
+
+The disclaimer of warranty in the University of Illinois Open Source License
+applies to all code in the LLVM Distribution, and nothing in any of the
+other licenses gives permission to use the names of the LLVM Team or the
+University of Illinois to endorse or promote products derived from this
+Software.
+
+The following pieces of software have additional or alternate copyrights,
+licenses, and/or restrictions:
+
+Program Directory
+------- ---------
+Autoconf llvm/autoconf
+ llvm/projects/ModuleMaker/autoconf
+ llvm/projects/sample/autoconf
+Google Test llvm/utils/unittest/googletest
+OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex}
+pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT}
+ARM contributions llvm/lib/Target/ARM/LICENSE.TXT
+md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/README.md b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/README.md
new file mode 100644
index 00000000..ebbcd934
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/README.md
@@ -0,0 +1,65 @@
+Capstone Engine
+===============
+
+[](https://travis-ci.org/aquynh/capstone)
+[](https://ci.appveyor.com/project/aquynh/capstone/branch/v4)
+
+Capstone is a disassembly framework with the target of becoming the ultimate
+disasm engine for binary analysis and reversing in the security community.
+
+Created by Nguyen Anh Quynh, then developed and maintained by a small community,
+Capstone offers some unparalleled features:
+
+- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Ethereum VM, M68K,
+ Mips, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore and X86 (including X86_64).
+
+- Having clean/simple/lightweight/intuitive architecture-neutral API.
+
+- Provide details on disassembled instruction (called “decomposer” by others).
+
+- Provide semantics of the disassembled instruction, such as list of implicit
+ registers read & written.
+
+- Implemented in pure C language, with lightweight bindings for D, Clojure, F#,
+ Common Lisp, Visual Basic, PHP, PowerShell, Emacs, Haskell, Perl, Python,
+ Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala
+ (ready either in main code, or provided externally by the community).
+
+- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
+ Linux, \*BSD, Solaris, etc.
+
+- Thread-safe by design.
+
+- Special support for embedding into firmware or OS kernel.
+
+- High performance & suitable for malware analysis (capable of handling various
+ X86 malware tricks).
+
+- Distributed under the open source BSD license.
+
+Further information is available at http://www.capstone-engine.org
+
+
+Compile
+-------
+
+See COMPILE.TXT file for how to compile and install Capstone.
+
+
+Documentation
+-------------
+
+See docs/README for how to customize & program your own tools with Capstone.
+
+
+Hack
+----
+
+See HACK.TXT file for the structure of the source code.
+
+
+License
+-------
+
+This project is released under the BSD license. If you redistribute the binary
+or source code of Capstone, please attach file LICENSE.TXT with your products.
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/RELEASE_NOTES b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/RELEASE_NOTES
new file mode 100644
index 00000000..f0102506
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/RELEASE_NOTES
@@ -0,0 +1,4 @@
+This release 4.0.2 is dedicated to my dad!
+
+Without him, I would not work in computing field, let alone writing any code
+or making contribution to the cyber security community.
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/SPONSORS.TXT b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/SPONSORS.TXT
new file mode 100644
index 00000000..970384c2
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/SPONSORS.TXT
@@ -0,0 +1,29 @@
+* Version 4.0.2 - May 08th, 2020
+
+Release 4.0.2 was sponsored by the following companies (in no particular order).
+
+- Senrio: https://senr.io
+- Catena Cyber: https://catenacyber.fr
+
+------------------------------------
+
+* Version 4.0.1 - January 10th, 2019
+
+Release 4.0.1 was sponsored by the following companies (in no particular order).
+
+- NowSecure: https://www.nowsecure.com
+- Verichains: https://verichains.io
+- Vsec: https://vsec.com.vn
+
+-----------------------------------
+* Version 4.0 - December 18th, 2018
+
+Capstone 4.0 version marks 5 years of the project!
+This release was sponsored by the following companies (in no particular order).
+
+- Thinkst Canary: https://canary.tools
+- NowSecure: https://www.nowsecure.com
+- ECQ: https://e-cq.net
+- Senrio: https://senr.io
+- GracefulBits: https://gracefulbits.com
+- Catena Cyber: https://catenacyber.fr
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone.dll b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone.dll
new file mode 100644
index 00000000..4eb46278
Binary files /dev/null and b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone.dll differ
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone.lib b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone.lib
new file mode 100644
index 00000000..01bfddee
Binary files /dev/null and b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone.lib differ
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone_dll.lib b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone_dll.lib
new file mode 100644
index 00000000..f49c9d8c
Binary files /dev/null and b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/capstone_dll.lib differ
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/cstool.exe b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/cstool.exe
new file mode 100644
index 00000000..99b1a260
Binary files /dev/null and b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/cstool.exe differ
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/arm.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/arm.h
new file mode 100644
index 00000000..21ba5be5
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/arm.h
@@ -0,0 +1,937 @@
+#ifndef CAPSTONE_ARM_H
+#define CAPSTONE_ARM_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2013-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// ARM shift type
+typedef enum arm_shifter {
+ ARM_SFT_INVALID = 0,
+ ARM_SFT_ASR, ///< shift with immediate const
+ ARM_SFT_LSL, ///< shift with immediate const
+ ARM_SFT_LSR, ///< shift with immediate const
+ ARM_SFT_ROR, ///< shift with immediate const
+ ARM_SFT_RRX, ///< shift with immediate const
+ ARM_SFT_ASR_REG, ///< shift with register
+ ARM_SFT_LSL_REG, ///< shift with register
+ ARM_SFT_LSR_REG, ///< shift with register
+ ARM_SFT_ROR_REG, ///< shift with register
+ ARM_SFT_RRX_REG, ///< shift with register
+} arm_shifter;
+
+/// ARM condition code
+typedef enum arm_cc {
+ ARM_CC_INVALID = 0,
+ ARM_CC_EQ, ///< Equal Equal
+ ARM_CC_NE, ///< Not equal Not equal, or unordered
+ ARM_CC_HS, ///< Carry set >, ==, or unordered
+ ARM_CC_LO, ///< Carry clear Less than
+ ARM_CC_MI, ///< Minus, negative Less than
+ ARM_CC_PL, ///< Plus, positive or zero >, ==, or unordered
+ ARM_CC_VS, ///< Overflow Unordered
+ ARM_CC_VC, ///< No overflow Not unordered
+ ARM_CC_HI, ///< Unsigned higher Greater than, or unordered
+ ARM_CC_LS, ///< Unsigned lower or same Less than or equal
+ ARM_CC_GE, ///< Greater than or equal Greater than or equal
+ ARM_CC_LT, ///< Less than Less than, or unordered
+ ARM_CC_GT, ///< Greater than Greater than
+ ARM_CC_LE, ///< Less than or equal <, ==, or unordered
+ ARM_CC_AL ///< Always (unconditional) Always (unconditional)
+} arm_cc;
+
+typedef enum arm_sysreg {
+ /// Special registers for MSR
+ ARM_SYSREG_INVALID = 0,
+
+ // SPSR* registers can be OR combined
+ ARM_SYSREG_SPSR_C = 1,
+ ARM_SYSREG_SPSR_X = 2,
+ ARM_SYSREG_SPSR_S = 4,
+ ARM_SYSREG_SPSR_F = 8,
+
+ // CPSR* registers can be OR combined
+ ARM_SYSREG_CPSR_C = 16,
+ ARM_SYSREG_CPSR_X = 32,
+ ARM_SYSREG_CPSR_S = 64,
+ ARM_SYSREG_CPSR_F = 128,
+
+ // independent registers
+ ARM_SYSREG_APSR = 256,
+ ARM_SYSREG_APSR_G,
+ ARM_SYSREG_APSR_NZCVQ,
+ ARM_SYSREG_APSR_NZCVQG,
+
+ ARM_SYSREG_IAPSR,
+ ARM_SYSREG_IAPSR_G,
+ ARM_SYSREG_IAPSR_NZCVQG,
+ ARM_SYSREG_IAPSR_NZCVQ,
+
+ ARM_SYSREG_EAPSR,
+ ARM_SYSREG_EAPSR_G,
+ ARM_SYSREG_EAPSR_NZCVQG,
+ ARM_SYSREG_EAPSR_NZCVQ,
+
+ ARM_SYSREG_XPSR,
+ ARM_SYSREG_XPSR_G,
+ ARM_SYSREG_XPSR_NZCVQG,
+ ARM_SYSREG_XPSR_NZCVQ,
+
+ ARM_SYSREG_IPSR,
+ ARM_SYSREG_EPSR,
+ ARM_SYSREG_IEPSR,
+
+ ARM_SYSREG_MSP,
+ ARM_SYSREG_PSP,
+ ARM_SYSREG_PRIMASK,
+ ARM_SYSREG_BASEPRI,
+ ARM_SYSREG_BASEPRI_MAX,
+ ARM_SYSREG_FAULTMASK,
+ ARM_SYSREG_CONTROL,
+
+ // Banked Registers
+ ARM_SYSREG_R8_USR,
+ ARM_SYSREG_R9_USR,
+ ARM_SYSREG_R10_USR,
+ ARM_SYSREG_R11_USR,
+ ARM_SYSREG_R12_USR,
+ ARM_SYSREG_SP_USR,
+ ARM_SYSREG_LR_USR,
+ ARM_SYSREG_R8_FIQ,
+ ARM_SYSREG_R9_FIQ,
+ ARM_SYSREG_R10_FIQ,
+ ARM_SYSREG_R11_FIQ,
+ ARM_SYSREG_R12_FIQ,
+ ARM_SYSREG_SP_FIQ,
+ ARM_SYSREG_LR_FIQ,
+ ARM_SYSREG_LR_IRQ,
+ ARM_SYSREG_SP_IRQ,
+ ARM_SYSREG_LR_SVC,
+ ARM_SYSREG_SP_SVC,
+ ARM_SYSREG_LR_ABT,
+ ARM_SYSREG_SP_ABT,
+ ARM_SYSREG_LR_UND,
+ ARM_SYSREG_SP_UND,
+ ARM_SYSREG_LR_MON,
+ ARM_SYSREG_SP_MON,
+ ARM_SYSREG_ELR_HYP,
+ ARM_SYSREG_SP_HYP,
+
+ ARM_SYSREG_SPSR_FIQ,
+ ARM_SYSREG_SPSR_IRQ,
+ ARM_SYSREG_SPSR_SVC,
+ ARM_SYSREG_SPSR_ABT,
+ ARM_SYSREG_SPSR_UND,
+ ARM_SYSREG_SPSR_MON,
+ ARM_SYSREG_SPSR_HYP,
+} arm_sysreg;
+
+/// The memory barrier constants map directly to the 4-bit encoding of
+/// the option field for Memory Barrier operations.
+typedef enum arm_mem_barrier {
+ ARM_MB_INVALID = 0,
+ ARM_MB_RESERVED_0,
+ ARM_MB_OSHLD,
+ ARM_MB_OSHST,
+ ARM_MB_OSH,
+ ARM_MB_RESERVED_4,
+ ARM_MB_NSHLD,
+ ARM_MB_NSHST,
+ ARM_MB_NSH,
+ ARM_MB_RESERVED_8,
+ ARM_MB_ISHLD,
+ ARM_MB_ISHST,
+ ARM_MB_ISH,
+ ARM_MB_RESERVED_12,
+ ARM_MB_LD,
+ ARM_MB_ST,
+ ARM_MB_SY,
+} arm_mem_barrier;
+
+/// Operand type for instruction's operands
+typedef enum arm_op_type {
+ ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ ARM_OP_REG, ///< = CS_OP_REG (Register operand).
+ ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+ ARM_OP_FP, ///< = CS_OP_FP (Floating-Point operand).
+ ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers)
+ ARM_OP_PIMM, ///< P-Immediate (coprocessor registers)
+ ARM_OP_SETEND, ///< operand for SETEND instruction
+ ARM_OP_SYSREG, ///< MSR/MRS special register operand
+} arm_op_type;
+
+/// Operand type for SETEND instruction
+typedef enum arm_setend_type {
+ ARM_SETEND_INVALID = 0, ///< Uninitialized.
+ ARM_SETEND_BE, ///< BE operand.
+ ARM_SETEND_LE, ///< LE operand
+} arm_setend_type;
+
+typedef enum arm_cpsmode_type {
+ ARM_CPSMODE_INVALID = 0,
+ ARM_CPSMODE_IE = 2,
+ ARM_CPSMODE_ID = 3
+} arm_cpsmode_type;
+
+/// Operand type for SETEND instruction
+typedef enum arm_cpsflag_type {
+ ARM_CPSFLAG_INVALID = 0,
+ ARM_CPSFLAG_F = 1,
+ ARM_CPSFLAG_I = 2,
+ ARM_CPSFLAG_A = 4,
+ ARM_CPSFLAG_NONE = 16, ///< no flag
+} arm_cpsflag_type;
+
+/// Data type for elements of vector instructions.
+typedef enum arm_vectordata_type {
+ ARM_VECTORDATA_INVALID = 0,
+
+ // Integer type
+ ARM_VECTORDATA_I8,
+ ARM_VECTORDATA_I16,
+ ARM_VECTORDATA_I32,
+ ARM_VECTORDATA_I64,
+
+ // Signed integer type
+ ARM_VECTORDATA_S8,
+ ARM_VECTORDATA_S16,
+ ARM_VECTORDATA_S32,
+ ARM_VECTORDATA_S64,
+
+ // Unsigned integer type
+ ARM_VECTORDATA_U8,
+ ARM_VECTORDATA_U16,
+ ARM_VECTORDATA_U32,
+ ARM_VECTORDATA_U64,
+
+ // Data type for VMUL/VMULL
+ ARM_VECTORDATA_P8,
+
+ // Floating type
+ ARM_VECTORDATA_F32,
+ ARM_VECTORDATA_F64,
+
+ // Convert float <-> float
+ ARM_VECTORDATA_F16F64, // f16.f64
+ ARM_VECTORDATA_F64F16, // f64.f16
+ ARM_VECTORDATA_F32F16, // f32.f16
+ ARM_VECTORDATA_F16F32, // f32.f16
+ ARM_VECTORDATA_F64F32, // f64.f32
+ ARM_VECTORDATA_F32F64, // f32.f64
+
+ // Convert integer <-> float
+ ARM_VECTORDATA_S32F32, // s32.f32
+ ARM_VECTORDATA_U32F32, // u32.f32
+ ARM_VECTORDATA_F32S32, // f32.s32
+ ARM_VECTORDATA_F32U32, // f32.u32
+ ARM_VECTORDATA_F64S16, // f64.s16
+ ARM_VECTORDATA_F32S16, // f32.s16
+ ARM_VECTORDATA_F64S32, // f64.s32
+ ARM_VECTORDATA_S16F64, // s16.f64
+ ARM_VECTORDATA_S16F32, // s16.f64
+ ARM_VECTORDATA_S32F64, // s32.f64
+ ARM_VECTORDATA_U16F64, // u16.f64
+ ARM_VECTORDATA_U16F32, // u16.f32
+ ARM_VECTORDATA_U32F64, // u32.f64
+ ARM_VECTORDATA_F64U16, // f64.u16
+ ARM_VECTORDATA_F32U16, // f32.u16
+ ARM_VECTORDATA_F64U32, // f64.u32
+} arm_vectordata_type;
+
+/// ARM registers
+typedef enum arm_reg {
+ ARM_REG_INVALID = 0,
+ ARM_REG_APSR,
+ ARM_REG_APSR_NZCV,
+ ARM_REG_CPSR,
+ ARM_REG_FPEXC,
+ ARM_REG_FPINST,
+ ARM_REG_FPSCR,
+ ARM_REG_FPSCR_NZCV,
+ ARM_REG_FPSID,
+ ARM_REG_ITSTATE,
+ ARM_REG_LR,
+ ARM_REG_PC,
+ ARM_REG_SP,
+ ARM_REG_SPSR,
+ ARM_REG_D0,
+ ARM_REG_D1,
+ ARM_REG_D2,
+ ARM_REG_D3,
+ ARM_REG_D4,
+ ARM_REG_D5,
+ ARM_REG_D6,
+ ARM_REG_D7,
+ ARM_REG_D8,
+ ARM_REG_D9,
+ ARM_REG_D10,
+ ARM_REG_D11,
+ ARM_REG_D12,
+ ARM_REG_D13,
+ ARM_REG_D14,
+ ARM_REG_D15,
+ ARM_REG_D16,
+ ARM_REG_D17,
+ ARM_REG_D18,
+ ARM_REG_D19,
+ ARM_REG_D20,
+ ARM_REG_D21,
+ ARM_REG_D22,
+ ARM_REG_D23,
+ ARM_REG_D24,
+ ARM_REG_D25,
+ ARM_REG_D26,
+ ARM_REG_D27,
+ ARM_REG_D28,
+ ARM_REG_D29,
+ ARM_REG_D30,
+ ARM_REG_D31,
+ ARM_REG_FPINST2,
+ ARM_REG_MVFR0,
+ ARM_REG_MVFR1,
+ ARM_REG_MVFR2,
+ ARM_REG_Q0,
+ ARM_REG_Q1,
+ ARM_REG_Q2,
+ ARM_REG_Q3,
+ ARM_REG_Q4,
+ ARM_REG_Q5,
+ ARM_REG_Q6,
+ ARM_REG_Q7,
+ ARM_REG_Q8,
+ ARM_REG_Q9,
+ ARM_REG_Q10,
+ ARM_REG_Q11,
+ ARM_REG_Q12,
+ ARM_REG_Q13,
+ ARM_REG_Q14,
+ ARM_REG_Q15,
+ ARM_REG_R0,
+ ARM_REG_R1,
+ ARM_REG_R2,
+ ARM_REG_R3,
+ ARM_REG_R4,
+ ARM_REG_R5,
+ ARM_REG_R6,
+ ARM_REG_R7,
+ ARM_REG_R8,
+ ARM_REG_R9,
+ ARM_REG_R10,
+ ARM_REG_R11,
+ ARM_REG_R12,
+ ARM_REG_S0,
+ ARM_REG_S1,
+ ARM_REG_S2,
+ ARM_REG_S3,
+ ARM_REG_S4,
+ ARM_REG_S5,
+ ARM_REG_S6,
+ ARM_REG_S7,
+ ARM_REG_S8,
+ ARM_REG_S9,
+ ARM_REG_S10,
+ ARM_REG_S11,
+ ARM_REG_S12,
+ ARM_REG_S13,
+ ARM_REG_S14,
+ ARM_REG_S15,
+ ARM_REG_S16,
+ ARM_REG_S17,
+ ARM_REG_S18,
+ ARM_REG_S19,
+ ARM_REG_S20,
+ ARM_REG_S21,
+ ARM_REG_S22,
+ ARM_REG_S23,
+ ARM_REG_S24,
+ ARM_REG_S25,
+ ARM_REG_S26,
+ ARM_REG_S27,
+ ARM_REG_S28,
+ ARM_REG_S29,
+ ARM_REG_S30,
+ ARM_REG_S31,
+
+ ARM_REG_ENDING, // <-- mark the end of the list or registers
+
+ // alias registers
+ ARM_REG_R13 = ARM_REG_SP,
+ ARM_REG_R14 = ARM_REG_LR,
+ ARM_REG_R15 = ARM_REG_PC,
+
+ ARM_REG_SB = ARM_REG_R9,
+ ARM_REG_SL = ARM_REG_R10,
+ ARM_REG_FP = ARM_REG_R11,
+ ARM_REG_IP = ARM_REG_R12,
+} arm_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with ARM_OP_MEM operand type above
+typedef struct arm_op_mem {
+ arm_reg base; ///< base register
+ arm_reg index; ///< index register
+ int scale; ///< scale for index register (can be 1, or -1)
+ int disp; ///< displacement/offset value
+ /// left-shift on index register, or 0 if irrelevant
+ /// NOTE: this value can also be fetched via operand.shift.value
+ int lshift;
+} arm_op_mem;
+
+/// Instruction operand
+typedef struct cs_arm_op {
+ int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant)
+
+ struct {
+ arm_shifter type;
+ unsigned int value;
+ } shift;
+
+ arm_op_type type; ///< operand type
+
+ union {
+ int reg; ///< register value for REG/SYSREG operand
+ int32_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand
+ double fp; ///< floating point value for FP operand
+ arm_op_mem mem; ///< base/index/scale/disp value for MEM operand
+ arm_setend_type setend; ///< SETEND instruction's operand type
+ };
+
+ /// in some instructions, an operand can be subtracted or added to
+ /// the base register,
+ /// if TRUE, this operand is subtracted. otherwise, it is added.
+ bool subtracted;
+
+ /// How is this operand accessed? (READ, WRITE or READ|WRITE)
+ /// This field is combined of cs_ac_type.
+ /// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+ uint8_t access;
+
+ /// Neon lane index for NEON instructions (or -1 if irrelevant)
+ int8_t neon_lane;
+} cs_arm_op;
+
+/// Instruction structure
+typedef struct cs_arm {
+ bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions)
+ int vector_size; ///< Scalar size for vector instructions
+ arm_vectordata_type vector_data; ///< Data type for elements of vector instructions
+ arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction
+ arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction
+ arm_cc cc; ///< conditional code for this insn
+ bool update_flags; ///< does this insn update flags?
+ bool writeback; ///< does this insn write-back?
+ arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions
+
+ /// Number of operands of this instruction,
+ /// or 0 when instruction has no operand.
+ uint8_t op_count;
+
+ cs_arm_op operands[36]; ///< operands for this instruction.
+} cs_arm;
+
+/// ARM instruction
+typedef enum arm_insn {
+ ARM_INS_INVALID = 0,
+
+ ARM_INS_ADC,
+ ARM_INS_ADD,
+ ARM_INS_ADR,
+ ARM_INS_AESD,
+ ARM_INS_AESE,
+ ARM_INS_AESIMC,
+ ARM_INS_AESMC,
+ ARM_INS_AND,
+ ARM_INS_BFC,
+ ARM_INS_BFI,
+ ARM_INS_BIC,
+ ARM_INS_BKPT,
+ ARM_INS_BL,
+ ARM_INS_BLX,
+ ARM_INS_BX,
+ ARM_INS_BXJ,
+ ARM_INS_B,
+ ARM_INS_CDP,
+ ARM_INS_CDP2,
+ ARM_INS_CLREX,
+ ARM_INS_CLZ,
+ ARM_INS_CMN,
+ ARM_INS_CMP,
+ ARM_INS_CPS,
+ ARM_INS_CRC32B,
+ ARM_INS_CRC32CB,
+ ARM_INS_CRC32CH,
+ ARM_INS_CRC32CW,
+ ARM_INS_CRC32H,
+ ARM_INS_CRC32W,
+ ARM_INS_DBG,
+ ARM_INS_DMB,
+ ARM_INS_DSB,
+ ARM_INS_EOR,
+ ARM_INS_ERET,
+ ARM_INS_VMOV,
+ ARM_INS_FLDMDBX,
+ ARM_INS_FLDMIAX,
+ ARM_INS_VMRS,
+ ARM_INS_FSTMDBX,
+ ARM_INS_FSTMIAX,
+ ARM_INS_HINT,
+ ARM_INS_HLT,
+ ARM_INS_HVC,
+ ARM_INS_ISB,
+ ARM_INS_LDA,
+ ARM_INS_LDAB,
+ ARM_INS_LDAEX,
+ ARM_INS_LDAEXB,
+ ARM_INS_LDAEXD,
+ ARM_INS_LDAEXH,
+ ARM_INS_LDAH,
+ ARM_INS_LDC2L,
+ ARM_INS_LDC2,
+ ARM_INS_LDCL,
+ ARM_INS_LDC,
+ ARM_INS_LDMDA,
+ ARM_INS_LDMDB,
+ ARM_INS_LDM,
+ ARM_INS_LDMIB,
+ ARM_INS_LDRBT,
+ ARM_INS_LDRB,
+ ARM_INS_LDRD,
+ ARM_INS_LDREX,
+ ARM_INS_LDREXB,
+ ARM_INS_LDREXD,
+ ARM_INS_LDREXH,
+ ARM_INS_LDRH,
+ ARM_INS_LDRHT,
+ ARM_INS_LDRSB,
+ ARM_INS_LDRSBT,
+ ARM_INS_LDRSH,
+ ARM_INS_LDRSHT,
+ ARM_INS_LDRT,
+ ARM_INS_LDR,
+ ARM_INS_MCR,
+ ARM_INS_MCR2,
+ ARM_INS_MCRR,
+ ARM_INS_MCRR2,
+ ARM_INS_MLA,
+ ARM_INS_MLS,
+ ARM_INS_MOV,
+ ARM_INS_MOVT,
+ ARM_INS_MOVW,
+ ARM_INS_MRC,
+ ARM_INS_MRC2,
+ ARM_INS_MRRC,
+ ARM_INS_MRRC2,
+ ARM_INS_MRS,
+ ARM_INS_MSR,
+ ARM_INS_MUL,
+ ARM_INS_MVN,
+ ARM_INS_ORR,
+ ARM_INS_PKHBT,
+ ARM_INS_PKHTB,
+ ARM_INS_PLDW,
+ ARM_INS_PLD,
+ ARM_INS_PLI,
+ ARM_INS_QADD,
+ ARM_INS_QADD16,
+ ARM_INS_QADD8,
+ ARM_INS_QASX,
+ ARM_INS_QDADD,
+ ARM_INS_QDSUB,
+ ARM_INS_QSAX,
+ ARM_INS_QSUB,
+ ARM_INS_QSUB16,
+ ARM_INS_QSUB8,
+ ARM_INS_RBIT,
+ ARM_INS_REV,
+ ARM_INS_REV16,
+ ARM_INS_REVSH,
+ ARM_INS_RFEDA,
+ ARM_INS_RFEDB,
+ ARM_INS_RFEIA,
+ ARM_INS_RFEIB,
+ ARM_INS_RSB,
+ ARM_INS_RSC,
+ ARM_INS_SADD16,
+ ARM_INS_SADD8,
+ ARM_INS_SASX,
+ ARM_INS_SBC,
+ ARM_INS_SBFX,
+ ARM_INS_SDIV,
+ ARM_INS_SEL,
+ ARM_INS_SETEND,
+ ARM_INS_SHA1C,
+ ARM_INS_SHA1H,
+ ARM_INS_SHA1M,
+ ARM_INS_SHA1P,
+ ARM_INS_SHA1SU0,
+ ARM_INS_SHA1SU1,
+ ARM_INS_SHA256H,
+ ARM_INS_SHA256H2,
+ ARM_INS_SHA256SU0,
+ ARM_INS_SHA256SU1,
+ ARM_INS_SHADD16,
+ ARM_INS_SHADD8,
+ ARM_INS_SHASX,
+ ARM_INS_SHSAX,
+ ARM_INS_SHSUB16,
+ ARM_INS_SHSUB8,
+ ARM_INS_SMC,
+ ARM_INS_SMLABB,
+ ARM_INS_SMLABT,
+ ARM_INS_SMLAD,
+ ARM_INS_SMLADX,
+ ARM_INS_SMLAL,
+ ARM_INS_SMLALBB,
+ ARM_INS_SMLALBT,
+ ARM_INS_SMLALD,
+ ARM_INS_SMLALDX,
+ ARM_INS_SMLALTB,
+ ARM_INS_SMLALTT,
+ ARM_INS_SMLATB,
+ ARM_INS_SMLATT,
+ ARM_INS_SMLAWB,
+ ARM_INS_SMLAWT,
+ ARM_INS_SMLSD,
+ ARM_INS_SMLSDX,
+ ARM_INS_SMLSLD,
+ ARM_INS_SMLSLDX,
+ ARM_INS_SMMLA,
+ ARM_INS_SMMLAR,
+ ARM_INS_SMMLS,
+ ARM_INS_SMMLSR,
+ ARM_INS_SMMUL,
+ ARM_INS_SMMULR,
+ ARM_INS_SMUAD,
+ ARM_INS_SMUADX,
+ ARM_INS_SMULBB,
+ ARM_INS_SMULBT,
+ ARM_INS_SMULL,
+ ARM_INS_SMULTB,
+ ARM_INS_SMULTT,
+ ARM_INS_SMULWB,
+ ARM_INS_SMULWT,
+ ARM_INS_SMUSD,
+ ARM_INS_SMUSDX,
+ ARM_INS_SRSDA,
+ ARM_INS_SRSDB,
+ ARM_INS_SRSIA,
+ ARM_INS_SRSIB,
+ ARM_INS_SSAT,
+ ARM_INS_SSAT16,
+ ARM_INS_SSAX,
+ ARM_INS_SSUB16,
+ ARM_INS_SSUB8,
+ ARM_INS_STC2L,
+ ARM_INS_STC2,
+ ARM_INS_STCL,
+ ARM_INS_STC,
+ ARM_INS_STL,
+ ARM_INS_STLB,
+ ARM_INS_STLEX,
+ ARM_INS_STLEXB,
+ ARM_INS_STLEXD,
+ ARM_INS_STLEXH,
+ ARM_INS_STLH,
+ ARM_INS_STMDA,
+ ARM_INS_STMDB,
+ ARM_INS_STM,
+ ARM_INS_STMIB,
+ ARM_INS_STRBT,
+ ARM_INS_STRB,
+ ARM_INS_STRD,
+ ARM_INS_STREX,
+ ARM_INS_STREXB,
+ ARM_INS_STREXD,
+ ARM_INS_STREXH,
+ ARM_INS_STRH,
+ ARM_INS_STRHT,
+ ARM_INS_STRT,
+ ARM_INS_STR,
+ ARM_INS_SUB,
+ ARM_INS_SVC,
+ ARM_INS_SWP,
+ ARM_INS_SWPB,
+ ARM_INS_SXTAB,
+ ARM_INS_SXTAB16,
+ ARM_INS_SXTAH,
+ ARM_INS_SXTB,
+ ARM_INS_SXTB16,
+ ARM_INS_SXTH,
+ ARM_INS_TEQ,
+ ARM_INS_TRAP,
+ ARM_INS_TST,
+ ARM_INS_UADD16,
+ ARM_INS_UADD8,
+ ARM_INS_UASX,
+ ARM_INS_UBFX,
+ ARM_INS_UDF,
+ ARM_INS_UDIV,
+ ARM_INS_UHADD16,
+ ARM_INS_UHADD8,
+ ARM_INS_UHASX,
+ ARM_INS_UHSAX,
+ ARM_INS_UHSUB16,
+ ARM_INS_UHSUB8,
+ ARM_INS_UMAAL,
+ ARM_INS_UMLAL,
+ ARM_INS_UMULL,
+ ARM_INS_UQADD16,
+ ARM_INS_UQADD8,
+ ARM_INS_UQASX,
+ ARM_INS_UQSAX,
+ ARM_INS_UQSUB16,
+ ARM_INS_UQSUB8,
+ ARM_INS_USAD8,
+ ARM_INS_USADA8,
+ ARM_INS_USAT,
+ ARM_INS_USAT16,
+ ARM_INS_USAX,
+ ARM_INS_USUB16,
+ ARM_INS_USUB8,
+ ARM_INS_UXTAB,
+ ARM_INS_UXTAB16,
+ ARM_INS_UXTAH,
+ ARM_INS_UXTB,
+ ARM_INS_UXTB16,
+ ARM_INS_UXTH,
+ ARM_INS_VABAL,
+ ARM_INS_VABA,
+ ARM_INS_VABDL,
+ ARM_INS_VABD,
+ ARM_INS_VABS,
+ ARM_INS_VACGE,
+ ARM_INS_VACGT,
+ ARM_INS_VADD,
+ ARM_INS_VADDHN,
+ ARM_INS_VADDL,
+ ARM_INS_VADDW,
+ ARM_INS_VAND,
+ ARM_INS_VBIC,
+ ARM_INS_VBIF,
+ ARM_INS_VBIT,
+ ARM_INS_VBSL,
+ ARM_INS_VCEQ,
+ ARM_INS_VCGE,
+ ARM_INS_VCGT,
+ ARM_INS_VCLE,
+ ARM_INS_VCLS,
+ ARM_INS_VCLT,
+ ARM_INS_VCLZ,
+ ARM_INS_VCMP,
+ ARM_INS_VCMPE,
+ ARM_INS_VCNT,
+ ARM_INS_VCVTA,
+ ARM_INS_VCVTB,
+ ARM_INS_VCVT,
+ ARM_INS_VCVTM,
+ ARM_INS_VCVTN,
+ ARM_INS_VCVTP,
+ ARM_INS_VCVTT,
+ ARM_INS_VDIV,
+ ARM_INS_VDUP,
+ ARM_INS_VEOR,
+ ARM_INS_VEXT,
+ ARM_INS_VFMA,
+ ARM_INS_VFMS,
+ ARM_INS_VFNMA,
+ ARM_INS_VFNMS,
+ ARM_INS_VHADD,
+ ARM_INS_VHSUB,
+ ARM_INS_VLD1,
+ ARM_INS_VLD2,
+ ARM_INS_VLD3,
+ ARM_INS_VLD4,
+ ARM_INS_VLDMDB,
+ ARM_INS_VLDMIA,
+ ARM_INS_VLDR,
+ ARM_INS_VMAXNM,
+ ARM_INS_VMAX,
+ ARM_INS_VMINNM,
+ ARM_INS_VMIN,
+ ARM_INS_VMLA,
+ ARM_INS_VMLAL,
+ ARM_INS_VMLS,
+ ARM_INS_VMLSL,
+ ARM_INS_VMOVL,
+ ARM_INS_VMOVN,
+ ARM_INS_VMSR,
+ ARM_INS_VMUL,
+ ARM_INS_VMULL,
+ ARM_INS_VMVN,
+ ARM_INS_VNEG,
+ ARM_INS_VNMLA,
+ ARM_INS_VNMLS,
+ ARM_INS_VNMUL,
+ ARM_INS_VORN,
+ ARM_INS_VORR,
+ ARM_INS_VPADAL,
+ ARM_INS_VPADDL,
+ ARM_INS_VPADD,
+ ARM_INS_VPMAX,
+ ARM_INS_VPMIN,
+ ARM_INS_VQABS,
+ ARM_INS_VQADD,
+ ARM_INS_VQDMLAL,
+ ARM_INS_VQDMLSL,
+ ARM_INS_VQDMULH,
+ ARM_INS_VQDMULL,
+ ARM_INS_VQMOVUN,
+ ARM_INS_VQMOVN,
+ ARM_INS_VQNEG,
+ ARM_INS_VQRDMULH,
+ ARM_INS_VQRSHL,
+ ARM_INS_VQRSHRN,
+ ARM_INS_VQRSHRUN,
+ ARM_INS_VQSHL,
+ ARM_INS_VQSHLU,
+ ARM_INS_VQSHRN,
+ ARM_INS_VQSHRUN,
+ ARM_INS_VQSUB,
+ ARM_INS_VRADDHN,
+ ARM_INS_VRECPE,
+ ARM_INS_VRECPS,
+ ARM_INS_VREV16,
+ ARM_INS_VREV32,
+ ARM_INS_VREV64,
+ ARM_INS_VRHADD,
+ ARM_INS_VRINTA,
+ ARM_INS_VRINTM,
+ ARM_INS_VRINTN,
+ ARM_INS_VRINTP,
+ ARM_INS_VRINTR,
+ ARM_INS_VRINTX,
+ ARM_INS_VRINTZ,
+ ARM_INS_VRSHL,
+ ARM_INS_VRSHRN,
+ ARM_INS_VRSHR,
+ ARM_INS_VRSQRTE,
+ ARM_INS_VRSQRTS,
+ ARM_INS_VRSRA,
+ ARM_INS_VRSUBHN,
+ ARM_INS_VSELEQ,
+ ARM_INS_VSELGE,
+ ARM_INS_VSELGT,
+ ARM_INS_VSELVS,
+ ARM_INS_VSHLL,
+ ARM_INS_VSHL,
+ ARM_INS_VSHRN,
+ ARM_INS_VSHR,
+ ARM_INS_VSLI,
+ ARM_INS_VSQRT,
+ ARM_INS_VSRA,
+ ARM_INS_VSRI,
+ ARM_INS_VST1,
+ ARM_INS_VST2,
+ ARM_INS_VST3,
+ ARM_INS_VST4,
+ ARM_INS_VSTMDB,
+ ARM_INS_VSTMIA,
+ ARM_INS_VSTR,
+ ARM_INS_VSUB,
+ ARM_INS_VSUBHN,
+ ARM_INS_VSUBL,
+ ARM_INS_VSUBW,
+ ARM_INS_VSWP,
+ ARM_INS_VTBL,
+ ARM_INS_VTBX,
+ ARM_INS_VCVTR,
+ ARM_INS_VTRN,
+ ARM_INS_VTST,
+ ARM_INS_VUZP,
+ ARM_INS_VZIP,
+ ARM_INS_ADDW,
+ ARM_INS_ASR,
+ ARM_INS_DCPS1,
+ ARM_INS_DCPS2,
+ ARM_INS_DCPS3,
+ ARM_INS_IT,
+ ARM_INS_LSL,
+ ARM_INS_LSR,
+ ARM_INS_ORN,
+ ARM_INS_ROR,
+ ARM_INS_RRX,
+ ARM_INS_SUBW,
+ ARM_INS_TBB,
+ ARM_INS_TBH,
+ ARM_INS_CBNZ,
+ ARM_INS_CBZ,
+ ARM_INS_POP,
+ ARM_INS_PUSH,
+
+ // special instructions
+ ARM_INS_NOP,
+ ARM_INS_YIELD,
+ ARM_INS_WFE,
+ ARM_INS_WFI,
+ ARM_INS_SEV,
+ ARM_INS_SEVL,
+ ARM_INS_VPUSH,
+ ARM_INS_VPOP,
+
+ ARM_INS_ENDING, // <-- mark the end of the list of instructions
+} arm_insn;
+
+/// Group of ARM instructions
+typedef enum arm_insn_group {
+ ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ ARM_GRP_JUMP, ///< = CS_GRP_JUMP
+ ARM_GRP_CALL, ///< = CS_GRP_CALL
+ ARM_GRP_INT = 4, ///< = CS_GRP_INT
+ ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE
+ ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+ // Architecture-specific groups
+ ARM_GRP_CRYPTO = 128,
+ ARM_GRP_DATABARRIER,
+ ARM_GRP_DIVIDE,
+ ARM_GRP_FPARMV8,
+ ARM_GRP_MULTPRO,
+ ARM_GRP_NEON,
+ ARM_GRP_T2EXTRACTPACK,
+ ARM_GRP_THUMB2DSP,
+ ARM_GRP_TRUSTZONE,
+ ARM_GRP_V4T,
+ ARM_GRP_V5T,
+ ARM_GRP_V5TE,
+ ARM_GRP_V6,
+ ARM_GRP_V6T2,
+ ARM_GRP_V7,
+ ARM_GRP_V8,
+ ARM_GRP_VFP2,
+ ARM_GRP_VFP3,
+ ARM_GRP_VFP4,
+ ARM_GRP_ARM,
+ ARM_GRP_MCLASS,
+ ARM_GRP_NOTMCLASS,
+ ARM_GRP_THUMB,
+ ARM_GRP_THUMB1ONLY,
+ ARM_GRP_THUMB2,
+ ARM_GRP_PREV8,
+ ARM_GRP_FPVMLX,
+ ARM_GRP_MULOPS,
+ ARM_GRP_CRC,
+ ARM_GRP_DPVFP,
+ ARM_GRP_V6M,
+ ARM_GRP_VIRTUALIZATION,
+
+ ARM_GRP_ENDING,
+} arm_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/arm64.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/arm64.h
new file mode 100644
index 00000000..0309f309
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/arm64.h
@@ -0,0 +1,1164 @@
+#ifndef CAPSTONE_ARM64_H
+#define CAPSTONE_ARM64_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2013-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// ARM64 shift type
+typedef enum arm64_shifter {
+ ARM64_SFT_INVALID = 0,
+ ARM64_SFT_LSL = 1,
+ ARM64_SFT_MSL = 2,
+ ARM64_SFT_LSR = 3,
+ ARM64_SFT_ASR = 4,
+ ARM64_SFT_ROR = 5,
+} arm64_shifter;
+
+/// ARM64 extender type
+typedef enum arm64_extender {
+ ARM64_EXT_INVALID = 0,
+ ARM64_EXT_UXTB = 1,
+ ARM64_EXT_UXTH = 2,
+ ARM64_EXT_UXTW = 3,
+ ARM64_EXT_UXTX = 4,
+ ARM64_EXT_SXTB = 5,
+ ARM64_EXT_SXTH = 6,
+ ARM64_EXT_SXTW = 7,
+ ARM64_EXT_SXTX = 8,
+} arm64_extender;
+
+/// ARM64 condition code
+typedef enum arm64_cc {
+ ARM64_CC_INVALID = 0,
+ ARM64_CC_EQ = 1, ///< Equal
+ ARM64_CC_NE = 2, ///< Not equal: Not equal, or unordered
+ ARM64_CC_HS = 3, ///< Unsigned higher or same: >, ==, or unordered
+ ARM64_CC_LO = 4, ///< Unsigned lower or same: Less than
+ ARM64_CC_MI = 5, ///< Minus, negative: Less than
+ ARM64_CC_PL = 6, ///< Plus, positive or zero: >, ==, or unordered
+ ARM64_CC_VS = 7, ///< Overflow: Unordered
+ ARM64_CC_VC = 8, ///< No overflow: Ordered
+ ARM64_CC_HI = 9, ///< Unsigned higher: Greater than, or unordered
+ ARM64_CC_LS = 10, ///< Unsigned lower or same: Less than or equal
+ ARM64_CC_GE = 11, ///< Greater than or equal: Greater than or equal
+ ARM64_CC_LT = 12, ///< Less than: Less than, or unordered
+ ARM64_CC_GT = 13, ///< Signed greater than: Greater than
+ ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered
+ ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional)
+ ARM64_CC_NV = 16, ///< Always (unconditional): Always (unconditional)
+ //< Note the NV exists purely to disassemble 0b1111. Execution
+ //< is "always".
+} arm64_cc;
+
+/// System registers
+typedef enum arm64_sysreg {
+ // System registers for MRS
+ ARM64_SYSREG_INVALID = 0,
+ ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
+ ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
+ ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
+ ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
+ ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
+ ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
+ ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
+ ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
+ ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
+ ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
+ ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001
+ ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
+ ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
+ ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
+ ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
+ ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
+ ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
+ ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
+ ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
+ ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
+ ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
+ ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
+ ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
+ ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
+ ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
+ ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
+ ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
+ ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
+ ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
+ ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
+ ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
+ ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
+ ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
+ ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
+ ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
+ ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
+ ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
+ ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
+ ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
+ ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
+ ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
+ ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
+ ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
+ ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
+ ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
+ ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000
+ ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
+ ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
+
+ // Trace registers
+ ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000
+ ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110
+ ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110
+ ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110
+ ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110
+ ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110
+ ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110
+ ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111
+ ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111
+ ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111
+ ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111
+ ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111
+ ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111
+ ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111
+ ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111
+ ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100
+ ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100
+ ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
+ ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
+ ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110
+ ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
+ ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
+ ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111
+ ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
+ ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
+ ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
+ ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
+ ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
+ ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
+ ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
+ ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
+ ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
+ ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
+ ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
+ ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
+ ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
+
+ // GICv3 registers
+ ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
+ ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
+ ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
+ ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
+ ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
+ ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
+ ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
+ ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101
+} arm64_sysreg;
+
+typedef enum arm64_msr_reg {
+ // System registers for MSR
+ ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
+ ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
+ ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
+
+ // Trace Registers
+ ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100
+ ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110
+
+ // GICv3 registers
+ ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
+ ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
+ ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
+ ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
+ ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
+ ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f, // 11 000 1100 1011 111
+} arm64_msr_reg;
+
+/// System PState Field (MSR instruction)
+typedef enum arm64_pstate {
+ ARM64_PSTATE_INVALID = 0,
+ ARM64_PSTATE_SPSEL = 0x05,
+ ARM64_PSTATE_DAIFSET = 0x1e,
+ ARM64_PSTATE_DAIFCLR = 0x1f
+} arm64_pstate;
+
+/// Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)
+typedef enum arm64_vas {
+ ARM64_VAS_INVALID = 0,
+ ARM64_VAS_8B,
+ ARM64_VAS_16B,
+ ARM64_VAS_4H,
+ ARM64_VAS_8H,
+ ARM64_VAS_2S,
+ ARM64_VAS_4S,
+ ARM64_VAS_1D,
+ ARM64_VAS_2D,
+ ARM64_VAS_1Q,
+} arm64_vas;
+
+/// Vector element size specifier
+typedef enum arm64_vess {
+ ARM64_VESS_INVALID = 0,
+ ARM64_VESS_B,
+ ARM64_VESS_H,
+ ARM64_VESS_S,
+ ARM64_VESS_D,
+} arm64_vess;
+
+/// Memory barrier operands
+typedef enum arm64_barrier_op {
+ ARM64_BARRIER_INVALID = 0,
+ ARM64_BARRIER_OSHLD = 0x1,
+ ARM64_BARRIER_OSHST = 0x2,
+ ARM64_BARRIER_OSH = 0x3,
+ ARM64_BARRIER_NSHLD = 0x5,
+ ARM64_BARRIER_NSHST = 0x6,
+ ARM64_BARRIER_NSH = 0x7,
+ ARM64_BARRIER_ISHLD = 0x9,
+ ARM64_BARRIER_ISHST = 0xa,
+ ARM64_BARRIER_ISH = 0xb,
+ ARM64_BARRIER_LD = 0xd,
+ ARM64_BARRIER_ST = 0xe,
+ ARM64_BARRIER_SY = 0xf
+} arm64_barrier_op;
+
+/// Operand type for instruction's operands
+typedef enum arm64_op_type {
+ ARM64_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ ARM64_OP_REG, ///< = CS_OP_REG (Register operand).
+ ARM64_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ ARM64_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+ ARM64_OP_FP, ///< = CS_OP_FP (Floating-Point operand).
+ ARM64_OP_CIMM = 64, ///< C-Immediate
+ ARM64_OP_REG_MRS, ///< MRS register operand.
+ ARM64_OP_REG_MSR, ///< MSR register operand.
+ ARM64_OP_PSTATE, ///< PState operand.
+ ARM64_OP_SYS, ///< SYS operand for IC/DC/AT/TLBI instructions.
+ ARM64_OP_PREFETCH, ///< Prefetch operand (PRFM).
+ ARM64_OP_BARRIER, ///< Memory barrier operand (ISB/DMB/DSB instructions).
+} arm64_op_type;
+
+/// TLBI operations
+typedef enum arm64_tlbi_op {
+ ARM64_TLBI_INVALID = 0,
+ ARM64_TLBI_VMALLE1IS,
+ ARM64_TLBI_VAE1IS,
+ ARM64_TLBI_ASIDE1IS,
+ ARM64_TLBI_VAAE1IS,
+ ARM64_TLBI_VALE1IS,
+ ARM64_TLBI_VAALE1IS,
+ ARM64_TLBI_ALLE2IS,
+ ARM64_TLBI_VAE2IS,
+ ARM64_TLBI_ALLE1IS,
+ ARM64_TLBI_VALE2IS,
+ ARM64_TLBI_VMALLS12E1IS,
+ ARM64_TLBI_ALLE3IS,
+ ARM64_TLBI_VAE3IS,
+ ARM64_TLBI_VALE3IS,
+ ARM64_TLBI_IPAS2E1IS,
+ ARM64_TLBI_IPAS2LE1IS,
+ ARM64_TLBI_IPAS2E1,
+ ARM64_TLBI_IPAS2LE1,
+ ARM64_TLBI_VMALLE1,
+ ARM64_TLBI_VAE1,
+ ARM64_TLBI_ASIDE1,
+ ARM64_TLBI_VAAE1,
+ ARM64_TLBI_VALE1,
+ ARM64_TLBI_VAALE1,
+ ARM64_TLBI_ALLE2,
+ ARM64_TLBI_VAE2,
+ ARM64_TLBI_ALLE1,
+ ARM64_TLBI_VALE2,
+ ARM64_TLBI_VMALLS12E1,
+ ARM64_TLBI_ALLE3,
+ ARM64_TLBI_VAE3,
+ ARM64_TLBI_VALE3,
+} arm64_tlbi_op;
+
+/// AT operations
+typedef enum arm64_at_op {
+ ARM64_AT_S1E1R,
+ ARM64_AT_S1E1W,
+ ARM64_AT_S1E0R,
+ ARM64_AT_S1E0W,
+ ARM64_AT_S1E2R,
+ ARM64_AT_S1E2W,
+ ARM64_AT_S12E1R,
+ ARM64_AT_S12E1W,
+ ARM64_AT_S12E0R,
+ ARM64_AT_S12E0W,
+ ARM64_AT_S1E3R,
+ ARM64_AT_S1E3W,
+} arm64_at_op;
+
+/// DC operations
+typedef enum arm64_dc_op {
+ ARM64_DC_INVALID = 0,
+ ARM64_DC_ZVA,
+ ARM64_DC_IVAC,
+ ARM64_DC_ISW,
+ ARM64_DC_CVAC,
+ ARM64_DC_CSW,
+ ARM64_DC_CVAU,
+ ARM64_DC_CIVAC,
+ ARM64_DC_CISW,
+} arm64_dc_op;
+
+/// IC operations
+typedef enum arm64_ic_op {
+ ARM64_IC_INVALID = 0,
+ ARM64_IC_IALLUIS,
+ ARM64_IC_IALLU,
+ ARM64_IC_IVAU,
+} arm64_ic_op;
+
+/// Prefetch operations (PRFM)
+typedef enum arm64_prefetch_op {
+ ARM64_PRFM_INVALID = 0,
+ ARM64_PRFM_PLDL1KEEP = 0x00 + 1,
+ ARM64_PRFM_PLDL1STRM = 0x01 + 1,
+ ARM64_PRFM_PLDL2KEEP = 0x02 + 1,
+ ARM64_PRFM_PLDL2STRM = 0x03 + 1,
+ ARM64_PRFM_PLDL3KEEP = 0x04 + 1,
+ ARM64_PRFM_PLDL3STRM = 0x05 + 1,
+ ARM64_PRFM_PLIL1KEEP = 0x08 + 1,
+ ARM64_PRFM_PLIL1STRM = 0x09 + 1,
+ ARM64_PRFM_PLIL2KEEP = 0x0a + 1,
+ ARM64_PRFM_PLIL2STRM = 0x0b + 1,
+ ARM64_PRFM_PLIL3KEEP = 0x0c + 1,
+ ARM64_PRFM_PLIL3STRM = 0x0d + 1,
+ ARM64_PRFM_PSTL1KEEP = 0x10 + 1,
+ ARM64_PRFM_PSTL1STRM = 0x11 + 1,
+ ARM64_PRFM_PSTL2KEEP = 0x12 + 1,
+ ARM64_PRFM_PSTL2STRM = 0x13 + 1,
+ ARM64_PRFM_PSTL3KEEP = 0x14 + 1,
+ ARM64_PRFM_PSTL3STRM = 0x15 + 1,
+} arm64_prefetch_op;
+
+
+/// ARM64 registers
+typedef enum arm64_reg {
+ ARM64_REG_INVALID = 0,
+
+ ARM64_REG_X29,
+ ARM64_REG_X30,
+ ARM64_REG_NZCV,
+ ARM64_REG_SP,
+ ARM64_REG_WSP,
+ ARM64_REG_WZR,
+ ARM64_REG_XZR,
+ ARM64_REG_B0,
+ ARM64_REG_B1,
+ ARM64_REG_B2,
+ ARM64_REG_B3,
+ ARM64_REG_B4,
+ ARM64_REG_B5,
+ ARM64_REG_B6,
+ ARM64_REG_B7,
+ ARM64_REG_B8,
+ ARM64_REG_B9,
+ ARM64_REG_B10,
+ ARM64_REG_B11,
+ ARM64_REG_B12,
+ ARM64_REG_B13,
+ ARM64_REG_B14,
+ ARM64_REG_B15,
+ ARM64_REG_B16,
+ ARM64_REG_B17,
+ ARM64_REG_B18,
+ ARM64_REG_B19,
+ ARM64_REG_B20,
+ ARM64_REG_B21,
+ ARM64_REG_B22,
+ ARM64_REG_B23,
+ ARM64_REG_B24,
+ ARM64_REG_B25,
+ ARM64_REG_B26,
+ ARM64_REG_B27,
+ ARM64_REG_B28,
+ ARM64_REG_B29,
+ ARM64_REG_B30,
+ ARM64_REG_B31,
+ ARM64_REG_D0,
+ ARM64_REG_D1,
+ ARM64_REG_D2,
+ ARM64_REG_D3,
+ ARM64_REG_D4,
+ ARM64_REG_D5,
+ ARM64_REG_D6,
+ ARM64_REG_D7,
+ ARM64_REG_D8,
+ ARM64_REG_D9,
+ ARM64_REG_D10,
+ ARM64_REG_D11,
+ ARM64_REG_D12,
+ ARM64_REG_D13,
+ ARM64_REG_D14,
+ ARM64_REG_D15,
+ ARM64_REG_D16,
+ ARM64_REG_D17,
+ ARM64_REG_D18,
+ ARM64_REG_D19,
+ ARM64_REG_D20,
+ ARM64_REG_D21,
+ ARM64_REG_D22,
+ ARM64_REG_D23,
+ ARM64_REG_D24,
+ ARM64_REG_D25,
+ ARM64_REG_D26,
+ ARM64_REG_D27,
+ ARM64_REG_D28,
+ ARM64_REG_D29,
+ ARM64_REG_D30,
+ ARM64_REG_D31,
+ ARM64_REG_H0,
+ ARM64_REG_H1,
+ ARM64_REG_H2,
+ ARM64_REG_H3,
+ ARM64_REG_H4,
+ ARM64_REG_H5,
+ ARM64_REG_H6,
+ ARM64_REG_H7,
+ ARM64_REG_H8,
+ ARM64_REG_H9,
+ ARM64_REG_H10,
+ ARM64_REG_H11,
+ ARM64_REG_H12,
+ ARM64_REG_H13,
+ ARM64_REG_H14,
+ ARM64_REG_H15,
+ ARM64_REG_H16,
+ ARM64_REG_H17,
+ ARM64_REG_H18,
+ ARM64_REG_H19,
+ ARM64_REG_H20,
+ ARM64_REG_H21,
+ ARM64_REG_H22,
+ ARM64_REG_H23,
+ ARM64_REG_H24,
+ ARM64_REG_H25,
+ ARM64_REG_H26,
+ ARM64_REG_H27,
+ ARM64_REG_H28,
+ ARM64_REG_H29,
+ ARM64_REG_H30,
+ ARM64_REG_H31,
+ ARM64_REG_Q0,
+ ARM64_REG_Q1,
+ ARM64_REG_Q2,
+ ARM64_REG_Q3,
+ ARM64_REG_Q4,
+ ARM64_REG_Q5,
+ ARM64_REG_Q6,
+ ARM64_REG_Q7,
+ ARM64_REG_Q8,
+ ARM64_REG_Q9,
+ ARM64_REG_Q10,
+ ARM64_REG_Q11,
+ ARM64_REG_Q12,
+ ARM64_REG_Q13,
+ ARM64_REG_Q14,
+ ARM64_REG_Q15,
+ ARM64_REG_Q16,
+ ARM64_REG_Q17,
+ ARM64_REG_Q18,
+ ARM64_REG_Q19,
+ ARM64_REG_Q20,
+ ARM64_REG_Q21,
+ ARM64_REG_Q22,
+ ARM64_REG_Q23,
+ ARM64_REG_Q24,
+ ARM64_REG_Q25,
+ ARM64_REG_Q26,
+ ARM64_REG_Q27,
+ ARM64_REG_Q28,
+ ARM64_REG_Q29,
+ ARM64_REG_Q30,
+ ARM64_REG_Q31,
+ ARM64_REG_S0,
+ ARM64_REG_S1,
+ ARM64_REG_S2,
+ ARM64_REG_S3,
+ ARM64_REG_S4,
+ ARM64_REG_S5,
+ ARM64_REG_S6,
+ ARM64_REG_S7,
+ ARM64_REG_S8,
+ ARM64_REG_S9,
+ ARM64_REG_S10,
+ ARM64_REG_S11,
+ ARM64_REG_S12,
+ ARM64_REG_S13,
+ ARM64_REG_S14,
+ ARM64_REG_S15,
+ ARM64_REG_S16,
+ ARM64_REG_S17,
+ ARM64_REG_S18,
+ ARM64_REG_S19,
+ ARM64_REG_S20,
+ ARM64_REG_S21,
+ ARM64_REG_S22,
+ ARM64_REG_S23,
+ ARM64_REG_S24,
+ ARM64_REG_S25,
+ ARM64_REG_S26,
+ ARM64_REG_S27,
+ ARM64_REG_S28,
+ ARM64_REG_S29,
+ ARM64_REG_S30,
+ ARM64_REG_S31,
+ ARM64_REG_W0,
+ ARM64_REG_W1,
+ ARM64_REG_W2,
+ ARM64_REG_W3,
+ ARM64_REG_W4,
+ ARM64_REG_W5,
+ ARM64_REG_W6,
+ ARM64_REG_W7,
+ ARM64_REG_W8,
+ ARM64_REG_W9,
+ ARM64_REG_W10,
+ ARM64_REG_W11,
+ ARM64_REG_W12,
+ ARM64_REG_W13,
+ ARM64_REG_W14,
+ ARM64_REG_W15,
+ ARM64_REG_W16,
+ ARM64_REG_W17,
+ ARM64_REG_W18,
+ ARM64_REG_W19,
+ ARM64_REG_W20,
+ ARM64_REG_W21,
+ ARM64_REG_W22,
+ ARM64_REG_W23,
+ ARM64_REG_W24,
+ ARM64_REG_W25,
+ ARM64_REG_W26,
+ ARM64_REG_W27,
+ ARM64_REG_W28,
+ ARM64_REG_W29,
+ ARM64_REG_W30,
+ ARM64_REG_X0,
+ ARM64_REG_X1,
+ ARM64_REG_X2,
+ ARM64_REG_X3,
+ ARM64_REG_X4,
+ ARM64_REG_X5,
+ ARM64_REG_X6,
+ ARM64_REG_X7,
+ ARM64_REG_X8,
+ ARM64_REG_X9,
+ ARM64_REG_X10,
+ ARM64_REG_X11,
+ ARM64_REG_X12,
+ ARM64_REG_X13,
+ ARM64_REG_X14,
+ ARM64_REG_X15,
+ ARM64_REG_X16,
+ ARM64_REG_X17,
+ ARM64_REG_X18,
+ ARM64_REG_X19,
+ ARM64_REG_X20,
+ ARM64_REG_X21,
+ ARM64_REG_X22,
+ ARM64_REG_X23,
+ ARM64_REG_X24,
+ ARM64_REG_X25,
+ ARM64_REG_X26,
+ ARM64_REG_X27,
+ ARM64_REG_X28,
+
+ ARM64_REG_V0,
+ ARM64_REG_V1,
+ ARM64_REG_V2,
+ ARM64_REG_V3,
+ ARM64_REG_V4,
+ ARM64_REG_V5,
+ ARM64_REG_V6,
+ ARM64_REG_V7,
+ ARM64_REG_V8,
+ ARM64_REG_V9,
+ ARM64_REG_V10,
+ ARM64_REG_V11,
+ ARM64_REG_V12,
+ ARM64_REG_V13,
+ ARM64_REG_V14,
+ ARM64_REG_V15,
+ ARM64_REG_V16,
+ ARM64_REG_V17,
+ ARM64_REG_V18,
+ ARM64_REG_V19,
+ ARM64_REG_V20,
+ ARM64_REG_V21,
+ ARM64_REG_V22,
+ ARM64_REG_V23,
+ ARM64_REG_V24,
+ ARM64_REG_V25,
+ ARM64_REG_V26,
+ ARM64_REG_V27,
+ ARM64_REG_V28,
+ ARM64_REG_V29,
+ ARM64_REG_V30,
+ ARM64_REG_V31,
+
+ ARM64_REG_ENDING, // <-- mark the end of the list of registers
+
+ // alias registers
+
+ ARM64_REG_IP0 = ARM64_REG_X16,
+ ARM64_REG_IP1 = ARM64_REG_X17,
+ ARM64_REG_FP = ARM64_REG_X29,
+ ARM64_REG_LR = ARM64_REG_X30,
+} arm64_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with ARM64_OP_MEM operand type above
+typedef struct arm64_op_mem {
+ arm64_reg base; ///< base register
+ arm64_reg index; ///< index register
+ int32_t disp; ///< displacement/offset value
+} arm64_op_mem;
+
+/// Instruction operand
+typedef struct cs_arm64_op {
+ int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant)
+ arm64_vas vas; ///< Vector Arrangement Specifier
+ arm64_vess vess; ///< Vector Element Size Specifier
+ struct {
+ arm64_shifter type; ///< shifter type of this operand
+ unsigned int value; ///< shifter value of this operand
+ } shift;
+ arm64_extender ext; ///< extender type of this operand
+ arm64_op_type type; ///< operand type
+ union {
+ arm64_reg reg; ///< register value for REG operand
+ int64_t imm; ///< immediate value, or index for C-IMM or IMM operand
+ double fp; ///< floating point value for FP operand
+ arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand
+ arm64_pstate pstate; ///< PState field of MSR instruction.
+ unsigned int sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
+ arm64_prefetch_op prefetch; ///< PRFM operation.
+ arm64_barrier_op barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions).
+ };
+
+ /// How is this operand accessed? (READ, WRITE or READ|WRITE)
+ /// This field is combined of cs_ac_type.
+ /// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+ uint8_t access;
+} cs_arm64_op;
+
+/// Instruction structure
+typedef struct cs_arm64 {
+ arm64_cc cc; ///< conditional code for this insn
+ bool update_flags; ///< does this insn update flags?
+ bool writeback; ///< does this insn request writeback? 'True' means 'yes'
+
+ /// Number of operands of this instruction,
+ /// or 0 when instruction has no operand.
+ uint8_t op_count;
+
+ cs_arm64_op operands[8]; ///< operands for this instruction.
+} cs_arm64;
+
+/// ARM64 instruction
+typedef enum arm64_insn {
+ ARM64_INS_INVALID = 0,
+
+ ARM64_INS_ABS,
+ ARM64_INS_ADC,
+ ARM64_INS_ADDHN,
+ ARM64_INS_ADDHN2,
+ ARM64_INS_ADDP,
+ ARM64_INS_ADD,
+ ARM64_INS_ADDV,
+ ARM64_INS_ADR,
+ ARM64_INS_ADRP,
+ ARM64_INS_AESD,
+ ARM64_INS_AESE,
+ ARM64_INS_AESIMC,
+ ARM64_INS_AESMC,
+ ARM64_INS_AND,
+ ARM64_INS_ASR,
+ ARM64_INS_B,
+ ARM64_INS_BFM,
+ ARM64_INS_BIC,
+ ARM64_INS_BIF,
+ ARM64_INS_BIT,
+ ARM64_INS_BL,
+ ARM64_INS_BLR,
+ ARM64_INS_BR,
+ ARM64_INS_BRK,
+ ARM64_INS_BSL,
+ ARM64_INS_CBNZ,
+ ARM64_INS_CBZ,
+ ARM64_INS_CCMN,
+ ARM64_INS_CCMP,
+ ARM64_INS_CLREX,
+ ARM64_INS_CLS,
+ ARM64_INS_CLZ,
+ ARM64_INS_CMEQ,
+ ARM64_INS_CMGE,
+ ARM64_INS_CMGT,
+ ARM64_INS_CMHI,
+ ARM64_INS_CMHS,
+ ARM64_INS_CMLE,
+ ARM64_INS_CMLT,
+ ARM64_INS_CMTST,
+ ARM64_INS_CNT,
+ ARM64_INS_MOV,
+ ARM64_INS_CRC32B,
+ ARM64_INS_CRC32CB,
+ ARM64_INS_CRC32CH,
+ ARM64_INS_CRC32CW,
+ ARM64_INS_CRC32CX,
+ ARM64_INS_CRC32H,
+ ARM64_INS_CRC32W,
+ ARM64_INS_CRC32X,
+ ARM64_INS_CSEL,
+ ARM64_INS_CSINC,
+ ARM64_INS_CSINV,
+ ARM64_INS_CSNEG,
+ ARM64_INS_DCPS1,
+ ARM64_INS_DCPS2,
+ ARM64_INS_DCPS3,
+ ARM64_INS_DMB,
+ ARM64_INS_DRPS,
+ ARM64_INS_DSB,
+ ARM64_INS_DUP,
+ ARM64_INS_EON,
+ ARM64_INS_EOR,
+ ARM64_INS_ERET,
+ ARM64_INS_EXTR,
+ ARM64_INS_EXT,
+ ARM64_INS_FABD,
+ ARM64_INS_FABS,
+ ARM64_INS_FACGE,
+ ARM64_INS_FACGT,
+ ARM64_INS_FADD,
+ ARM64_INS_FADDP,
+ ARM64_INS_FCCMP,
+ ARM64_INS_FCCMPE,
+ ARM64_INS_FCMEQ,
+ ARM64_INS_FCMGE,
+ ARM64_INS_FCMGT,
+ ARM64_INS_FCMLE,
+ ARM64_INS_FCMLT,
+ ARM64_INS_FCMP,
+ ARM64_INS_FCMPE,
+ ARM64_INS_FCSEL,
+ ARM64_INS_FCVTAS,
+ ARM64_INS_FCVTAU,
+ ARM64_INS_FCVT,
+ ARM64_INS_FCVTL,
+ ARM64_INS_FCVTL2,
+ ARM64_INS_FCVTMS,
+ ARM64_INS_FCVTMU,
+ ARM64_INS_FCVTNS,
+ ARM64_INS_FCVTNU,
+ ARM64_INS_FCVTN,
+ ARM64_INS_FCVTN2,
+ ARM64_INS_FCVTPS,
+ ARM64_INS_FCVTPU,
+ ARM64_INS_FCVTXN,
+ ARM64_INS_FCVTXN2,
+ ARM64_INS_FCVTZS,
+ ARM64_INS_FCVTZU,
+ ARM64_INS_FDIV,
+ ARM64_INS_FMADD,
+ ARM64_INS_FMAX,
+ ARM64_INS_FMAXNM,
+ ARM64_INS_FMAXNMP,
+ ARM64_INS_FMAXNMV,
+ ARM64_INS_FMAXP,
+ ARM64_INS_FMAXV,
+ ARM64_INS_FMIN,
+ ARM64_INS_FMINNM,
+ ARM64_INS_FMINNMP,
+ ARM64_INS_FMINNMV,
+ ARM64_INS_FMINP,
+ ARM64_INS_FMINV,
+ ARM64_INS_FMLA,
+ ARM64_INS_FMLS,
+ ARM64_INS_FMOV,
+ ARM64_INS_FMSUB,
+ ARM64_INS_FMUL,
+ ARM64_INS_FMULX,
+ ARM64_INS_FNEG,
+ ARM64_INS_FNMADD,
+ ARM64_INS_FNMSUB,
+ ARM64_INS_FNMUL,
+ ARM64_INS_FRECPE,
+ ARM64_INS_FRECPS,
+ ARM64_INS_FRECPX,
+ ARM64_INS_FRINTA,
+ ARM64_INS_FRINTI,
+ ARM64_INS_FRINTM,
+ ARM64_INS_FRINTN,
+ ARM64_INS_FRINTP,
+ ARM64_INS_FRINTX,
+ ARM64_INS_FRINTZ,
+ ARM64_INS_FRSQRTE,
+ ARM64_INS_FRSQRTS,
+ ARM64_INS_FSQRT,
+ ARM64_INS_FSUB,
+ ARM64_INS_HINT,
+ ARM64_INS_HLT,
+ ARM64_INS_HVC,
+ ARM64_INS_INS,
+
+ ARM64_INS_ISB,
+ ARM64_INS_LD1,
+ ARM64_INS_LD1R,
+ ARM64_INS_LD2R,
+ ARM64_INS_LD2,
+ ARM64_INS_LD3R,
+ ARM64_INS_LD3,
+ ARM64_INS_LD4,
+ ARM64_INS_LD4R,
+
+ ARM64_INS_LDARB,
+ ARM64_INS_LDARH,
+ ARM64_INS_LDAR,
+ ARM64_INS_LDAXP,
+ ARM64_INS_LDAXRB,
+ ARM64_INS_LDAXRH,
+ ARM64_INS_LDAXR,
+ ARM64_INS_LDNP,
+ ARM64_INS_LDP,
+ ARM64_INS_LDPSW,
+ ARM64_INS_LDRB,
+ ARM64_INS_LDR,
+ ARM64_INS_LDRH,
+ ARM64_INS_LDRSB,
+ ARM64_INS_LDRSH,
+ ARM64_INS_LDRSW,
+ ARM64_INS_LDTRB,
+ ARM64_INS_LDTRH,
+ ARM64_INS_LDTRSB,
+
+ ARM64_INS_LDTRSH,
+ ARM64_INS_LDTRSW,
+ ARM64_INS_LDTR,
+ ARM64_INS_LDURB,
+ ARM64_INS_LDUR,
+ ARM64_INS_LDURH,
+ ARM64_INS_LDURSB,
+ ARM64_INS_LDURSH,
+ ARM64_INS_LDURSW,
+ ARM64_INS_LDXP,
+ ARM64_INS_LDXRB,
+ ARM64_INS_LDXRH,
+ ARM64_INS_LDXR,
+ ARM64_INS_LSL,
+ ARM64_INS_LSR,
+ ARM64_INS_MADD,
+ ARM64_INS_MLA,
+ ARM64_INS_MLS,
+ ARM64_INS_MOVI,
+ ARM64_INS_MOVK,
+ ARM64_INS_MOVN,
+ ARM64_INS_MOVZ,
+ ARM64_INS_MRS,
+ ARM64_INS_MSR,
+ ARM64_INS_MSUB,
+ ARM64_INS_MUL,
+ ARM64_INS_MVNI,
+ ARM64_INS_NEG,
+ ARM64_INS_NOT,
+ ARM64_INS_ORN,
+ ARM64_INS_ORR,
+ ARM64_INS_PMULL2,
+ ARM64_INS_PMULL,
+ ARM64_INS_PMUL,
+ ARM64_INS_PRFM,
+ ARM64_INS_PRFUM,
+ ARM64_INS_RADDHN,
+ ARM64_INS_RADDHN2,
+ ARM64_INS_RBIT,
+ ARM64_INS_RET,
+ ARM64_INS_REV16,
+ ARM64_INS_REV32,
+ ARM64_INS_REV64,
+ ARM64_INS_REV,
+ ARM64_INS_ROR,
+ ARM64_INS_RSHRN2,
+ ARM64_INS_RSHRN,
+ ARM64_INS_RSUBHN,
+ ARM64_INS_RSUBHN2,
+ ARM64_INS_SABAL2,
+ ARM64_INS_SABAL,
+
+ ARM64_INS_SABA,
+ ARM64_INS_SABDL2,
+ ARM64_INS_SABDL,
+ ARM64_INS_SABD,
+ ARM64_INS_SADALP,
+ ARM64_INS_SADDLP,
+ ARM64_INS_SADDLV,
+ ARM64_INS_SADDL2,
+ ARM64_INS_SADDL,
+ ARM64_INS_SADDW2,
+ ARM64_INS_SADDW,
+ ARM64_INS_SBC,
+ ARM64_INS_SBFM,
+ ARM64_INS_SCVTF,
+ ARM64_INS_SDIV,
+ ARM64_INS_SHA1C,
+ ARM64_INS_SHA1H,
+ ARM64_INS_SHA1M,
+ ARM64_INS_SHA1P,
+ ARM64_INS_SHA1SU0,
+ ARM64_INS_SHA1SU1,
+ ARM64_INS_SHA256H2,
+ ARM64_INS_SHA256H,
+ ARM64_INS_SHA256SU0,
+ ARM64_INS_SHA256SU1,
+ ARM64_INS_SHADD,
+ ARM64_INS_SHLL2,
+ ARM64_INS_SHLL,
+ ARM64_INS_SHL,
+ ARM64_INS_SHRN2,
+ ARM64_INS_SHRN,
+ ARM64_INS_SHSUB,
+ ARM64_INS_SLI,
+ ARM64_INS_SMADDL,
+ ARM64_INS_SMAXP,
+ ARM64_INS_SMAXV,
+ ARM64_INS_SMAX,
+ ARM64_INS_SMC,
+ ARM64_INS_SMINP,
+ ARM64_INS_SMINV,
+ ARM64_INS_SMIN,
+ ARM64_INS_SMLAL2,
+ ARM64_INS_SMLAL,
+ ARM64_INS_SMLSL2,
+ ARM64_INS_SMLSL,
+ ARM64_INS_SMOV,
+ ARM64_INS_SMSUBL,
+ ARM64_INS_SMULH,
+ ARM64_INS_SMULL2,
+ ARM64_INS_SMULL,
+ ARM64_INS_SQABS,
+ ARM64_INS_SQADD,
+ ARM64_INS_SQDMLAL,
+ ARM64_INS_SQDMLAL2,
+ ARM64_INS_SQDMLSL,
+ ARM64_INS_SQDMLSL2,
+ ARM64_INS_SQDMULH,
+ ARM64_INS_SQDMULL,
+ ARM64_INS_SQDMULL2,
+ ARM64_INS_SQNEG,
+ ARM64_INS_SQRDMULH,
+ ARM64_INS_SQRSHL,
+ ARM64_INS_SQRSHRN,
+ ARM64_INS_SQRSHRN2,
+ ARM64_INS_SQRSHRUN,
+ ARM64_INS_SQRSHRUN2,
+ ARM64_INS_SQSHLU,
+ ARM64_INS_SQSHL,
+ ARM64_INS_SQSHRN,
+ ARM64_INS_SQSHRN2,
+ ARM64_INS_SQSHRUN,
+ ARM64_INS_SQSHRUN2,
+ ARM64_INS_SQSUB,
+ ARM64_INS_SQXTN2,
+ ARM64_INS_SQXTN,
+ ARM64_INS_SQXTUN2,
+ ARM64_INS_SQXTUN,
+ ARM64_INS_SRHADD,
+ ARM64_INS_SRI,
+ ARM64_INS_SRSHL,
+ ARM64_INS_SRSHR,
+ ARM64_INS_SRSRA,
+ ARM64_INS_SSHLL2,
+ ARM64_INS_SSHLL,
+ ARM64_INS_SSHL,
+ ARM64_INS_SSHR,
+ ARM64_INS_SSRA,
+ ARM64_INS_SSUBL2,
+ ARM64_INS_SSUBL,
+ ARM64_INS_SSUBW2,
+ ARM64_INS_SSUBW,
+ ARM64_INS_ST1,
+ ARM64_INS_ST2,
+ ARM64_INS_ST3,
+ ARM64_INS_ST4,
+ ARM64_INS_STLRB,
+ ARM64_INS_STLRH,
+ ARM64_INS_STLR,
+ ARM64_INS_STLXP,
+ ARM64_INS_STLXRB,
+ ARM64_INS_STLXRH,
+ ARM64_INS_STLXR,
+ ARM64_INS_STNP,
+ ARM64_INS_STP,
+ ARM64_INS_STRB,
+ ARM64_INS_STR,
+ ARM64_INS_STRH,
+ ARM64_INS_STTRB,
+ ARM64_INS_STTRH,
+ ARM64_INS_STTR,
+ ARM64_INS_STURB,
+ ARM64_INS_STUR,
+ ARM64_INS_STURH,
+ ARM64_INS_STXP,
+ ARM64_INS_STXRB,
+ ARM64_INS_STXRH,
+ ARM64_INS_STXR,
+ ARM64_INS_SUBHN,
+ ARM64_INS_SUBHN2,
+ ARM64_INS_SUB,
+ ARM64_INS_SUQADD,
+ ARM64_INS_SVC,
+ ARM64_INS_SYSL,
+ ARM64_INS_SYS,
+ ARM64_INS_TBL,
+ ARM64_INS_TBNZ,
+ ARM64_INS_TBX,
+ ARM64_INS_TBZ,
+ ARM64_INS_TRN1,
+ ARM64_INS_TRN2,
+ ARM64_INS_UABAL2,
+ ARM64_INS_UABAL,
+ ARM64_INS_UABA,
+ ARM64_INS_UABDL2,
+ ARM64_INS_UABDL,
+ ARM64_INS_UABD,
+ ARM64_INS_UADALP,
+ ARM64_INS_UADDLP,
+ ARM64_INS_UADDLV,
+ ARM64_INS_UADDL2,
+ ARM64_INS_UADDL,
+ ARM64_INS_UADDW2,
+ ARM64_INS_UADDW,
+ ARM64_INS_UBFM,
+ ARM64_INS_UCVTF,
+ ARM64_INS_UDIV,
+ ARM64_INS_UHADD,
+ ARM64_INS_UHSUB,
+ ARM64_INS_UMADDL,
+ ARM64_INS_UMAXP,
+ ARM64_INS_UMAXV,
+ ARM64_INS_UMAX,
+ ARM64_INS_UMINP,
+ ARM64_INS_UMINV,
+ ARM64_INS_UMIN,
+ ARM64_INS_UMLAL2,
+ ARM64_INS_UMLAL,
+ ARM64_INS_UMLSL2,
+ ARM64_INS_UMLSL,
+ ARM64_INS_UMOV,
+ ARM64_INS_UMSUBL,
+ ARM64_INS_UMULH,
+ ARM64_INS_UMULL2,
+ ARM64_INS_UMULL,
+ ARM64_INS_UQADD,
+ ARM64_INS_UQRSHL,
+ ARM64_INS_UQRSHRN,
+ ARM64_INS_UQRSHRN2,
+ ARM64_INS_UQSHL,
+ ARM64_INS_UQSHRN,
+ ARM64_INS_UQSHRN2,
+ ARM64_INS_UQSUB,
+ ARM64_INS_UQXTN2,
+ ARM64_INS_UQXTN,
+ ARM64_INS_URECPE,
+ ARM64_INS_URHADD,
+ ARM64_INS_URSHL,
+ ARM64_INS_URSHR,
+ ARM64_INS_URSQRTE,
+ ARM64_INS_URSRA,
+ ARM64_INS_USHLL2,
+ ARM64_INS_USHLL,
+ ARM64_INS_USHL,
+ ARM64_INS_USHR,
+ ARM64_INS_USQADD,
+ ARM64_INS_USRA,
+ ARM64_INS_USUBL2,
+ ARM64_INS_USUBL,
+ ARM64_INS_USUBW2,
+ ARM64_INS_USUBW,
+ ARM64_INS_UZP1,
+ ARM64_INS_UZP2,
+ ARM64_INS_XTN2,
+ ARM64_INS_XTN,
+ ARM64_INS_ZIP1,
+ ARM64_INS_ZIP2,
+
+ // alias insn
+ ARM64_INS_MNEG,
+ ARM64_INS_UMNEGL,
+ ARM64_INS_SMNEGL,
+ ARM64_INS_NOP,
+ ARM64_INS_YIELD,
+ ARM64_INS_WFE,
+ ARM64_INS_WFI,
+ ARM64_INS_SEV,
+ ARM64_INS_SEVL,
+ ARM64_INS_NGC,
+ ARM64_INS_SBFIZ,
+ ARM64_INS_UBFIZ,
+ ARM64_INS_SBFX,
+ ARM64_INS_UBFX,
+ ARM64_INS_BFI,
+ ARM64_INS_BFXIL,
+ ARM64_INS_CMN,
+ ARM64_INS_MVN,
+ ARM64_INS_TST,
+ ARM64_INS_CSET,
+ ARM64_INS_CINC,
+ ARM64_INS_CSETM,
+ ARM64_INS_CINV,
+ ARM64_INS_CNEG,
+ ARM64_INS_SXTB,
+ ARM64_INS_SXTH,
+ ARM64_INS_SXTW,
+ ARM64_INS_CMP,
+ ARM64_INS_UXTB,
+ ARM64_INS_UXTH,
+ ARM64_INS_UXTW,
+ ARM64_INS_IC,
+ ARM64_INS_DC,
+ ARM64_INS_AT,
+ ARM64_INS_TLBI,
+
+ ARM64_INS_NEGS,
+ ARM64_INS_NGCS,
+
+ ARM64_INS_ENDING, // <-- mark the end of the list of insn
+} arm64_insn;
+
+/// Group of ARM64 instructions
+typedef enum arm64_insn_group {
+ ARM64_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ ARM64_GRP_JUMP, ///< = CS_GRP_JUMP
+ ARM64_GRP_CALL,
+ ARM64_GRP_RET,
+ ARM64_GRP_INT,
+ ARM64_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE
+ ARM64_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+ // Architecture-specific groups
+ ARM64_GRP_CRYPTO = 128,
+ ARM64_GRP_FPARMV8,
+ ARM64_GRP_NEON,
+ ARM64_GRP_CRC,
+
+ ARM64_GRP_ENDING, // <-- mark the end of the list of groups
+} arm64_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/capstone.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/capstone.h
new file mode 100644
index 00000000..23c13d5f
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/capstone.h
@@ -0,0 +1,766 @@
+#ifndef CAPSTONE_ENGINE_H
+#define CAPSTONE_ENGINE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2013-2016 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include
+#else
+#include
+#include
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#pragma warning(disable:4100)
+#define CAPSTONE_API __cdecl
+#ifdef CAPSTONE_SHARED
+#define CAPSTONE_EXPORT __declspec(dllexport)
+#else // defined(CAPSTONE_STATIC)
+#define CAPSTONE_EXPORT
+#endif
+#else
+#define CAPSTONE_API
+#if defined(__GNUC__) && !defined(CAPSTONE_STATIC)
+#define CAPSTONE_EXPORT __attribute__((visibility("default")))
+#else // defined(CAPSTONE_STATIC)
+#define CAPSTONE_EXPORT
+#endif
+#endif
+
+#ifdef __GNUC__
+#define CAPSTONE_DEPRECATED __attribute__((deprecated))
+#elif defined(_MSC_VER)
+#define CAPSTONE_DEPRECATED __declspec(deprecated)
+#else
+#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")
+#define CAPSTONE_DEPRECATED
+#endif
+
+// Capstone API version
+#define CS_API_MAJOR 4
+#define CS_API_MINOR 0
+
+// Version for bleeding edge code of the Github's "next" branch.
+// Use this if you want the absolutely latest development code.
+// This version number will be bumped up whenever we have a new major change.
+#define CS_NEXT_VERSION 5
+
+// Capstone package version
+#define CS_VERSION_MAJOR CS_API_MAJOR
+#define CS_VERSION_MINOR CS_API_MINOR
+#define CS_VERSION_EXTRA 2
+
+/// Macro to create combined version which can be compared to
+/// result of cs_version() API.
+#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor)
+
+/// Maximum size of an instruction mnemonic string.
+#define CS_MNEMONIC_SIZE 32
+
+// Handle using with all API
+typedef size_t csh;
+
+/// Architecture type
+typedef enum cs_arch {
+ CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2)
+ CS_ARCH_ARM64, ///< ARM-64, also called AArch64
+ CS_ARCH_MIPS, ///< Mips architecture
+ CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64)
+ CS_ARCH_PPC, ///< PowerPC architecture
+ CS_ARCH_SPARC, ///< Sparc architecture
+ CS_ARCH_SYSZ, ///< SystemZ architecture
+ CS_ARCH_XCORE, ///< XCore architecture
+ CS_ARCH_M68K, ///< 68K architecture
+ CS_ARCH_TMS320C64X, ///< TMS320C64x architecture
+ CS_ARCH_M680X, ///< 680X architecture
+ CS_ARCH_EVM, ///< Ethereum architecture
+ CS_ARCH_MAX,
+ CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
+} cs_arch;
+
+// Support value to verify diet mode of the engine.
+// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled
+// in diet mode.
+#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1)
+
+// Support value to verify X86 reduce mode of the engine.
+// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled
+// in X86 reduce mode.
+#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2)
+
+/// Mode type
+typedef enum cs_mode {
+ CS_MODE_LITTLE_ENDIAN = 0, ///< little-endian mode (default mode)
+ CS_MODE_ARM = 0, ///< 32-bit ARM
+ CS_MODE_16 = 1 << 1, ///< 16-bit mode (X86)
+ CS_MODE_32 = 1 << 2, ///< 32-bit mode (X86)
+ CS_MODE_64 = 1 << 3, ///< 64-bit mode (X86, PPC)
+ CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2
+ CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series
+ CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM
+ CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS)
+ CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA
+ CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA
+ CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA
+ CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc)
+ CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)
+ CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode
+ CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode
+ CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode
+ CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode
+ CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode
+ CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode
+ CS_MODE_BIG_ENDIAN = 1 << 31, ///< big-endian mode
+ CS_MODE_MIPS32 = CS_MODE_32, ///< Mips32 ISA (Mips)
+ CS_MODE_MIPS64 = CS_MODE_64, ///< Mips64 ISA (Mips)
+ CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode
+ CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode
+ CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode
+ CS_MODE_M680X_6801 = 1 << 4, ///< M680X Motorola 6801,6803 mode
+ CS_MODE_M680X_6805 = 1 << 5, ///< M680X Motorola/Freescale 6805 mode
+ CS_MODE_M680X_6808 = 1 << 6, ///< M680X Motorola/Freescale/NXP 68HC08 mode
+ CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode
+ CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode
+ CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12
+ ///< used on M68HC12/HCS12
+ CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode
+} cs_mode;
+
+typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
+typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size);
+typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size);
+typedef void (CAPSTONE_API *cs_free_t)(void *ptr);
+typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap);
+
+
+/// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()
+/// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf().
+typedef struct cs_opt_mem {
+ cs_malloc_t malloc;
+ cs_calloc_t calloc;
+ cs_realloc_t realloc;
+ cs_free_t free;
+ cs_vsnprintf_t vsnprintf;
+} cs_opt_mem;
+
+/// Customize mnemonic for instructions with alternative name.
+/// To reset existing customized instruction to its default mnemonic,
+/// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value
+/// for @mnemonic.
+typedef struct cs_opt_mnem {
+ /// ID of instruction to be customized.
+ unsigned int id;
+ /// Customized instruction mnemonic.
+ const char *mnemonic;
+} cs_opt_mnem;
+
+/// Runtime option for the disassembled engine
+typedef enum cs_opt_type {
+ CS_OPT_INVALID = 0, ///< No option specified
+ CS_OPT_SYNTAX, ///< Assembly output syntax
+ CS_OPT_DETAIL, ///< Break down instruction structure into details
+ CS_OPT_MODE, ///< Change engine's mode at run-time
+ CS_OPT_MEM, ///< User-defined dynamic memory related functions
+ CS_OPT_SKIPDATA, ///< Skip data when disassembling. Then engine is in SKIPDATA mode.
+ CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option
+ CS_OPT_MNEMONIC, ///< Customize instruction mnemonic
+ CS_OPT_UNSIGNED, ///< print immediate operands in unsigned form
+} cs_opt_type;
+
+/// Runtime option value (associated with option type above)
+typedef enum cs_opt_value {
+ CS_OPT_OFF = 0, ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED.
+ CS_OPT_ON = 3, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
+ CS_OPT_SYNTAX_DEFAULT = 0, ///< Default asm syntax (CS_OPT_SYNTAX).
+ CS_OPT_SYNTAX_INTEL, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
+ CS_OPT_SYNTAX_ATT, ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
+ CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX)
+ CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
+} cs_opt_value;
+
+/// Common instruction operand types - to be consistent across all architectures.
+typedef enum cs_op_type {
+ CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
+ CS_OP_REG, ///< Register operand.
+ CS_OP_IMM, ///< Immediate operand.
+ CS_OP_MEM, ///< Memory operand.
+ CS_OP_FP, ///< Floating-Point operand.
+} cs_op_type;
+
+/// Common instruction operand access types - to be consistent across all architectures.
+/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
+typedef enum cs_ac_type {
+ CS_AC_INVALID = 0, ///< Uninitialized/invalid access type.
+ CS_AC_READ = 1 << 0, ///< Operand read from memory or register.
+ CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register.
+} cs_ac_type;
+
+/// Common instruction groups - to be consistent across all architectures.
+typedef enum cs_group_type {
+ CS_GRP_INVALID = 0, ///< uninitialized/invalid group.
+ CS_GRP_JUMP, ///< all jump instructions (conditional+direct+indirect jumps)
+ CS_GRP_CALL, ///< all call instructions
+ CS_GRP_RET, ///< all return instructions
+ CS_GRP_INT, ///< all interrupt instructions (int+syscall)
+ CS_GRP_IRET, ///< all interrupt return instructions
+ CS_GRP_PRIVILEGE, ///< all privileged instructions
+ CS_GRP_BRANCH_RELATIVE, ///< all relative branching instructions
+} cs_group_type;
+
+/**
+ User-defined callback function for SKIPDATA option.
+ See tests/test_skipdata.c for sample code demonstrating this API.
+
+ @code: the input buffer containing code to be disassembled.
+ This is the same buffer passed to cs_disasm().
+ @code_size: size (in bytes) of the above @code buffer.
+ @offset: the position of the currently-examining byte in the input
+ buffer @code mentioned above.
+ @user_data: user-data passed to cs_option() via @user_data field in
+ cs_opt_skipdata struct below.
+
+ @return: return number of bytes to skip, or 0 to immediately stop disassembling.
+*/
+typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data);
+
+/// User-customized setup for SKIPDATA option
+typedef struct cs_opt_skipdata {
+ /// Capstone considers data to skip as special "instructions".
+ /// User can specify the string for this instruction's "mnemonic" here.
+ /// By default (if @mnemonic is NULL), Capstone use ".byte".
+ const char *mnemonic;
+
+ /// User-defined callback function to be called when Capstone hits data.
+ /// If the returned value from this callback is positive (>0), Capstone
+ /// will skip exactly that number of bytes & continue. Otherwise, if
+ /// the callback returns 0, Capstone stops disassembling and returns
+ /// immediately from cs_disasm()
+ /// NOTE: if this callback pointer is NULL, Capstone would skip a number
+ /// of bytes depending on architectures, as following:
+ /// Arm: 2 bytes (Thumb mode) or 4 bytes.
+ /// Arm64: 4 bytes.
+ /// Mips: 4 bytes.
+ /// M680x: 1 byte.
+ /// PowerPC: 4 bytes.
+ /// Sparc: 4 bytes.
+ /// SystemZ: 2 bytes.
+ /// X86: 1 bytes.
+ /// XCore: 2 bytes.
+ /// EVM: 1 bytes.
+ cs_skipdata_cb_t callback; // default value is NULL
+
+ /// User-defined data to be passed to @callback function pointer.
+ void *user_data;
+} cs_opt_skipdata;
+
+
+#include "arm.h"
+#include "arm64.h"
+#include "m68k.h"
+#include "mips.h"
+#include "ppc.h"
+#include "sparc.h"
+#include "systemz.h"
+#include "x86.h"
+#include "xcore.h"
+#include "tms320c64x.h"
+#include "m680x.h"
+#include "evm.h"
+
+/// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
+/// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))
+/// by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c
+/// if cs_detail changes, in particular if a field is added after the union,
+/// then update arch/ARCH/ARCHDisassembler.c accordingly
+typedef struct cs_detail {
+ uint16_t regs_read[12]; ///< list of implicit registers read by this insn
+ uint8_t regs_read_count; ///< number of implicit registers read by this insn
+
+ uint16_t regs_write[20]; ///< list of implicit registers modified by this insn
+ uint8_t regs_write_count; ///< number of implicit registers modified by this insn
+
+ uint8_t groups[8]; ///< list of group this instruction belong to
+ uint8_t groups_count; ///< number of groups this insn belongs to
+
+ /// Architecture-specific instruction info
+ union {
+ cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode
+ cs_arm64 arm64; ///< ARM64 architecture (aka AArch64)
+ cs_arm arm; ///< ARM architecture (including Thumb/Thumb2)
+ cs_m68k m68k; ///< M68K architecture
+ cs_mips mips; ///< MIPS architecture
+ cs_ppc ppc; ///< PowerPC architecture
+ cs_sparc sparc; ///< Sparc architecture
+ cs_sysz sysz; ///< SystemZ architecture
+ cs_xcore xcore; ///< XCore architecture
+ cs_tms320c64x tms320c64x; ///< TMS320C64x architecture
+ cs_m680x m680x; ///< M680X architecture
+ cs_evm evm; ///< Ethereum architecture
+ };
+} cs_detail;
+
+/// Detail information of disassembled instruction
+typedef struct cs_insn {
+ /// Instruction ID (basically a numeric ID for the instruction mnemonic)
+ /// Find the instruction id in the '[ARCH]_insn' enum in the header file
+ /// of corresponding architecture, such as 'arm_insn' in arm.h for ARM,
+ /// 'x86_insn' in x86.h for X86, etc...
+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+ /// NOTE: in Skipdata mode, "data" instruction has 0 for this id field.
+ unsigned int id;
+
+ /// Address (EIP) of this instruction
+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+ uint64_t address;
+
+ /// Size of this instruction
+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+ uint16_t size;
+
+ /// Machine bytes of this instruction, with number of bytes indicated by @size above
+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+ uint8_t bytes[16];
+
+ /// Ascii text of instruction mnemonic
+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+ char mnemonic[CS_MNEMONIC_SIZE];
+
+ /// Ascii text of instruction operands
+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+ char op_str[160];
+
+ /// Pointer to cs_detail.
+ /// NOTE: detail pointer is only valid when both requirements below are met:
+ /// (1) CS_OP_DETAIL = CS_OPT_ON
+ /// (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)
+ ///
+ /// NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer
+ /// is not NULL, its content is still irrelevant.
+ cs_detail *detail;
+} cs_insn;
+
+
+/// Calculate the offset of a disassembled instruction in its buffer, given its position
+/// in its array of disassembled insn
+/// NOTE: this macro works with position (>=1), not index
+#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address)
+
+
+/// All type of errors encountered by Capstone API.
+/// These are values returned by cs_errno()
+typedef enum cs_err {
+ CS_ERR_OK = 0, ///< No error: everything was fine
+ CS_ERR_MEM, ///< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()
+ CS_ERR_ARCH, ///< Unsupported architecture: cs_open()
+ CS_ERR_HANDLE, ///< Invalid handle: cs_op_count(), cs_op_index()
+ CS_ERR_CSH, ///< Invalid csh argument: cs_close(), cs_errno(), cs_option()
+ CS_ERR_MODE, ///< Invalid/unsupported mode: cs_open()
+ CS_ERR_OPTION, ///< Invalid/unsupported option: cs_option()
+ CS_ERR_DETAIL, ///< Information is unavailable because detail option is OFF
+ CS_ERR_MEMSETUP, ///< Dynamic memory management uninitialized (see CS_OPT_MEM)
+ CS_ERR_VERSION, ///< Unsupported version (bindings)
+ CS_ERR_DIET, ///< Access irrelevant data in "diet" engine
+ CS_ERR_SKIPDATA, ///< Access irrelevant data for "data" instruction in SKIPDATA mode
+ CS_ERR_X86_ATT, ///< X86 AT&T syntax is unsupported (opt-out at compile time)
+ CS_ERR_X86_INTEL, ///< X86 Intel syntax is unsupported (opt-out at compile time)
+ CS_ERR_X86_MASM, ///< X86 Masm syntax is unsupported (opt-out at compile time)
+} cs_err;
+
+/**
+ Return combined API version & major and minor version numbers.
+
+ @major: major number of API version
+ @minor: minor number of API version
+
+ @return hexical number as (major << 8 | minor), which encodes both
+ major & minor versions.
+ NOTE: This returned value can be compared with version number made
+ with macro CS_MAKE_VERSION
+
+ For example, second API version would return 1 in @major, and 1 in @minor
+ The return value would be 0x0101
+
+ NOTE: if you only care about returned value, but not major and minor values,
+ set both @major & @minor arguments to NULL.
+*/
+CAPSTONE_EXPORT
+unsigned int CAPSTONE_API cs_version(int *major, int *minor);
+
+
+/**
+ This API can be used to either ask for archs supported by this library,
+ or check to see if the library was compile with 'diet' option (or called
+ in 'diet' mode).
+
+ To check if a particular arch is supported by this library, set @query to
+ arch mode (CS_ARCH_* value).
+ To verify if this library supports all the archs, use CS_ARCH_ALL.
+
+ To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.
+
+ @return True if this library supports the given arch, or in 'diet' mode.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_support(int query);
+
+/**
+ Initialize CS handle: this must be done before any usage of CS.
+
+ @arch: architecture type (CS_ARCH_*)
+ @mode: hardware mode. This is combined of CS_MODE_*
+ @handle: pointer to handle, which will be updated at return time
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle);
+
+/**
+ Close CS handle: MUST do to release the handle when it is not used anymore.
+ NOTE: this must be only called when there is no longer usage of Capstone,
+ not even access to cs_insn array. The reason is the this API releases some
+ cached memory, thus access to any Capstone API after cs_close() might crash
+ your application.
+
+ In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).
+
+ @handle: pointer to a handle returned by cs_open()
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_close(csh *handle);
+
+/**
+ Set option for disassembling engine at runtime
+
+ @handle: handle returned by cs_open()
+ @type: type of option to be set
+ @value: option value corresponding with @type
+
+ @return: CS_ERR_OK on success, or other value on failure.
+ Refer to cs_err enum for detailed error.
+
+ NOTE: in the case of CS_OPT_MEM, handle's value can be anything,
+ so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called
+ even before cs_open()
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value);
+
+/**
+ Report the last error number when some API function fail.
+ Like glibc's errno, cs_errno might not retain its old value once accessed.
+
+ @handle: handle returned by cs_open()
+
+ @return: error code of cs_err enum type (CS_ERR_*, see above)
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_errno(csh handle);
+
+
+/**
+ Return a string describing given error code.
+
+ @code: error code (see CS_ERR_* above)
+
+ @return: returns a pointer to a string that describes the error code
+ passed in the argument @code
+*/
+CAPSTONE_EXPORT
+const char * CAPSTONE_API cs_strerror(cs_err code);
+
+/**
+ Disassemble binary code, given the code buffer, size, address and number
+ of instructions to be decoded.
+ This API dynamically allocate memory to contain disassembled instruction.
+ Resulting instructions will be put into @*insn
+
+ NOTE 1: this API will automatically determine memory needed to contain
+ output disassembled instructions in @insn.
+
+ NOTE 2: caller must free the allocated memory itself to avoid memory leaking.
+
+ NOTE 3: for system with scarce memory to be dynamically allocated such as
+ OS kernel or firmware, the API cs_disasm_iter() might be a better choice than
+ cs_disasm(). The reason is that with cs_disasm(), based on limited available
+ memory, we have to calculate in advance how many instructions to be disassembled,
+ which complicates things. This is especially troublesome for the case @count=0,
+ when cs_disasm() runs uncontrollably (until either end of input buffer, or
+ when it encounters an invalid instruction).
+
+ @handle: handle returned by cs_open()
+ @code: buffer containing raw binary code to be disassembled.
+ @code_size: size of the above code buffer.
+ @address: address of the first instruction in given raw code buffer.
+ @insn: array of instructions filled in by this API.
+ NOTE: @insn will be allocated by this function, and should be freed
+ with cs_free() API.
+ @count: number of instructions to be disassembled, or 0 to get all of them
+
+ @return: the number of successfully disassembled instructions,
+ or 0 if this function failed to disassemble the given code
+
+ On failure, call cs_errno() for error code.
+*/
+CAPSTONE_EXPORT
+size_t CAPSTONE_API cs_disasm(csh handle,
+ const uint8_t *code, size_t code_size,
+ uint64_t address,
+ size_t count,
+ cs_insn **insn);
+
+/**
+ Deprecated function - to be retired in the next version!
+ Use cs_disasm() instead of cs_disasm_ex()
+*/
+CAPSTONE_EXPORT
+CAPSTONE_DEPRECATED
+size_t CAPSTONE_API cs_disasm_ex(csh handle,
+ const uint8_t *code, size_t code_size,
+ uint64_t address,
+ size_t count,
+ cs_insn **insn);
+
+/**
+ Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)
+
+ @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()
+ @count: number of cs_insn structures returned by cs_disasm(), or 1
+ to free memory allocated by cs_malloc().
+*/
+CAPSTONE_EXPORT
+void CAPSTONE_API cs_free(cs_insn *insn, size_t count);
+
+
+/**
+ Allocate memory for 1 instruction to be used by cs_disasm_iter().
+
+ @handle: handle returned by cs_open()
+
+ NOTE: when no longer in use, you can reclaim the memory allocated for
+ this instruction with cs_free(insn, 1)
+*/
+CAPSTONE_EXPORT
+cs_insn * CAPSTONE_API cs_malloc(csh handle);
+
+/**
+ Fast API to disassemble binary code, given the code buffer, size, address
+ and number of instructions to be decoded.
+ This API puts the resulting instruction into a given cache in @insn.
+ See tests/test_iter.c for sample code demonstrating this API.
+
+ NOTE 1: this API will update @code, @size & @address to point to the next
+ instruction in the input buffer. Therefore, it is convenient to use
+ cs_disasm_iter() inside a loop to quickly iterate all the instructions.
+ While decoding one instruction at a time can also be achieved with
+ cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%
+ faster on random input.
+
+ NOTE 2: the cache in @insn can be created with cs_malloc() API.
+
+ NOTE 3: for system with scarce memory to be dynamically allocated such as
+ OS kernel or firmware, this API is recommended over cs_disasm(), which
+ allocates memory based on the number of instructions to be disassembled.
+ The reason is that with cs_disasm(), based on limited available memory,
+ we have to calculate in advance how many instructions to be disassembled,
+ which complicates things. This is especially troublesome for the case
+ @count=0, when cs_disasm() runs uncontrollably (until either end of input
+ buffer, or when it encounters an invalid instruction).
+
+ @handle: handle returned by cs_open()
+ @code: buffer containing raw binary code to be disassembled
+ @size: size of above code
+ @address: address of the first insn in given raw code buffer
+ @insn: pointer to instruction to be filled in by this API.
+
+ @return: true if this API successfully decode 1 instruction,
+ or false otherwise.
+
+ On failure, call cs_errno() for error code.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_disasm_iter(csh handle,
+ const uint8_t **code, size_t *size,
+ uint64_t *address, cs_insn *insn);
+
+/**
+ Return friendly name of register in a string.
+ Find the instruction id from header file of corresponding architecture (arm.h for ARM,
+ x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because engine does not
+ store register name.
+
+ @handle: handle returned by cs_open()
+ @reg_id: register id
+
+ @return: string name of the register, or NULL if @reg_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id);
+
+/**
+ Return friendly name of an instruction in a string.
+ Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store instruction name.
+
+ @handle: handle returned by cs_open()
+ @insn_id: instruction id
+
+ @return: string name of the instruction, or NULL if @insn_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id);
+
+/**
+ Return friendly name of a group id (that an instruction can belong to)
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store group name.
+
+ @handle: handle returned by cs_open()
+ @group_id: group id
+
+ @return: string name of the group, or NULL if @group_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id);
+
+/**
+ Check if a disassembled instruction belong to a particular group.
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @group_id matches any member of insn->groups array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default).
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @groups array.
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @group_id: group that you want to check if this instruction belong to.
+
+ @return: true if this instruction indeed belongs to the given group, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id);
+
+/**
+ Check if a disassembled instruction IMPLICITLY used a particular register.
+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @regs_read array.
+
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @reg_id: register that you want to check if this instruction used it.
+
+ @return: true if this instruction indeed implicitly used the given register, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id);
+
+/**
+ Check if a disassembled instruction IMPLICITLY modified a particular register.
+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @regs_write array.
+
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @reg_id: register that you want to check if this instruction modified it.
+
+ @return: true if this instruction indeed implicitly modified the given register, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id);
+
+/**
+ Count the number of operands of a given type.
+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @op_type: Operand type to be found.
+
+ @return: number of operands of given type @op_type in instruction @insn,
+ or -1 on failure.
+*/
+CAPSTONE_EXPORT
+int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type);
+
+/**
+ Retrieve the position of operand of given type in .operands[] array.
+ Later, the operand can be accessed using the returned position.
+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @op_type: Operand type to be found.
+ @position: position of the operand to be found. This must be in the range
+ [1, cs_op_count(handle, insn, op_type)]
+
+ @return: index of operand of given type @op_type in .operands[] array
+ in instruction @insn, or -1 on failure.
+*/
+CAPSTONE_EXPORT
+int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type,
+ unsigned int position);
+
+/// Type of array to keep the list of registers
+typedef uint16_t cs_regs[64];
+
+/**
+ Retrieve all the registers accessed by an instruction, either explicitly or
+ implicitly.
+
+ WARN: when in 'diet' mode, this API is irrelevant because engine does not
+ store registers.
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()
+ @regs_read: on return, this array contains all registers read by instruction.
+ @regs_read_count: number of registers kept inside @regs_read array.
+ @regs_write: on return, this array contains all registers written by instruction.
+ @regs_write_count: number of registers kept inside @regs_write array.
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn,
+ cs_regs regs_read, uint8_t *regs_read_count,
+ cs_regs regs_write, uint8_t *regs_write_count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/evm.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/evm.h
new file mode 100644
index 00000000..78fb7c08
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/evm.h
@@ -0,0 +1,188 @@
+#ifndef CAPSTONE_EVM_H
+#define CAPSTONE_EVM_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2013-2018 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Instruction structure
+typedef struct cs_evm {
+ unsigned char pop; ///< number of items popped from the stack
+ unsigned char push; ///< number of items pushed into the stack
+ unsigned int fee; ///< gas fee for the instruction
+} cs_evm;
+
+/// EVM instruction
+typedef enum evm_insn {
+ EVM_INS_STOP = 0,
+ EVM_INS_ADD = 1,
+ EVM_INS_MUL = 2,
+ EVM_INS_SUB = 3,
+ EVM_INS_DIV = 4,
+ EVM_INS_SDIV = 5,
+ EVM_INS_MOD = 6,
+ EVM_INS_SMOD = 7,
+ EVM_INS_ADDMOD = 8,
+ EVM_INS_MULMOD = 9,
+ EVM_INS_EXP = 10,
+ EVM_INS_SIGNEXTEND = 11,
+ EVM_INS_LT = 16,
+ EVM_INS_GT = 17,
+ EVM_INS_SLT = 18,
+ EVM_INS_SGT = 19,
+ EVM_INS_EQ = 20,
+ EVM_INS_ISZERO = 21,
+ EVM_INS_AND = 22,
+ EVM_INS_OR = 23,
+ EVM_INS_XOR = 24,
+ EVM_INS_NOT = 25,
+ EVM_INS_BYTE = 26,
+ EVM_INS_SHA3 = 32,
+ EVM_INS_ADDRESS = 48,
+ EVM_INS_BALANCE = 49,
+ EVM_INS_ORIGIN = 50,
+ EVM_INS_CALLER = 51,
+ EVM_INS_CALLVALUE = 52,
+ EVM_INS_CALLDATALOAD = 53,
+ EVM_INS_CALLDATASIZE = 54,
+ EVM_INS_CALLDATACOPY = 55,
+ EVM_INS_CODESIZE = 56,
+ EVM_INS_CODECOPY = 57,
+ EVM_INS_GASPRICE = 58,
+ EVM_INS_EXTCODESIZE = 59,
+ EVM_INS_EXTCODECOPY = 60,
+ EVM_INS_RETURNDATASIZE = 61,
+ EVM_INS_RETURNDATACOPY = 62,
+ EVM_INS_BLOCKHASH = 64,
+ EVM_INS_COINBASE = 65,
+ EVM_INS_TIMESTAMP = 66,
+ EVM_INS_NUMBER = 67,
+ EVM_INS_DIFFICULTY = 68,
+ EVM_INS_GASLIMIT = 69,
+ EVM_INS_POP = 80,
+ EVM_INS_MLOAD = 81,
+ EVM_INS_MSTORE = 82,
+ EVM_INS_MSTORE8 = 83,
+ EVM_INS_SLOAD = 84,
+ EVM_INS_SSTORE = 85,
+ EVM_INS_JUMP = 86,
+ EVM_INS_JUMPI = 87,
+ EVM_INS_PC = 88,
+ EVM_INS_MSIZE = 89,
+ EVM_INS_GAS = 90,
+ EVM_INS_JUMPDEST = 91,
+ EVM_INS_PUSH1 = 96,
+ EVM_INS_PUSH2 = 97,
+ EVM_INS_PUSH3 = 98,
+ EVM_INS_PUSH4 = 99,
+ EVM_INS_PUSH5 = 100,
+ EVM_INS_PUSH6 = 101,
+ EVM_INS_PUSH7 = 102,
+ EVM_INS_PUSH8 = 103,
+ EVM_INS_PUSH9 = 104,
+ EVM_INS_PUSH10 = 105,
+ EVM_INS_PUSH11 = 106,
+ EVM_INS_PUSH12 = 107,
+ EVM_INS_PUSH13 = 108,
+ EVM_INS_PUSH14 = 109,
+ EVM_INS_PUSH15 = 110,
+ EVM_INS_PUSH16 = 111,
+ EVM_INS_PUSH17 = 112,
+ EVM_INS_PUSH18 = 113,
+ EVM_INS_PUSH19 = 114,
+ EVM_INS_PUSH20 = 115,
+ EVM_INS_PUSH21 = 116,
+ EVM_INS_PUSH22 = 117,
+ EVM_INS_PUSH23 = 118,
+ EVM_INS_PUSH24 = 119,
+ EVM_INS_PUSH25 = 120,
+ EVM_INS_PUSH26 = 121,
+ EVM_INS_PUSH27 = 122,
+ EVM_INS_PUSH28 = 123,
+ EVM_INS_PUSH29 = 124,
+ EVM_INS_PUSH30 = 125,
+ EVM_INS_PUSH31 = 126,
+ EVM_INS_PUSH32 = 127,
+ EVM_INS_DUP1 = 128,
+ EVM_INS_DUP2 = 129,
+ EVM_INS_DUP3 = 130,
+ EVM_INS_DUP4 = 131,
+ EVM_INS_DUP5 = 132,
+ EVM_INS_DUP6 = 133,
+ EVM_INS_DUP7 = 134,
+ EVM_INS_DUP8 = 135,
+ EVM_INS_DUP9 = 136,
+ EVM_INS_DUP10 = 137,
+ EVM_INS_DUP11 = 138,
+ EVM_INS_DUP12 = 139,
+ EVM_INS_DUP13 = 140,
+ EVM_INS_DUP14 = 141,
+ EVM_INS_DUP15 = 142,
+ EVM_INS_DUP16 = 143,
+ EVM_INS_SWAP1 = 144,
+ EVM_INS_SWAP2 = 145,
+ EVM_INS_SWAP3 = 146,
+ EVM_INS_SWAP4 = 147,
+ EVM_INS_SWAP5 = 148,
+ EVM_INS_SWAP6 = 149,
+ EVM_INS_SWAP7 = 150,
+ EVM_INS_SWAP8 = 151,
+ EVM_INS_SWAP9 = 152,
+ EVM_INS_SWAP10 = 153,
+ EVM_INS_SWAP11 = 154,
+ EVM_INS_SWAP12 = 155,
+ EVM_INS_SWAP13 = 156,
+ EVM_INS_SWAP14 = 157,
+ EVM_INS_SWAP15 = 158,
+ EVM_INS_SWAP16 = 159,
+ EVM_INS_LOG0 = 160,
+ EVM_INS_LOG1 = 161,
+ EVM_INS_LOG2 = 162,
+ EVM_INS_LOG3 = 163,
+ EVM_INS_LOG4 = 164,
+ EVM_INS_CREATE = 240,
+ EVM_INS_CALL = 241,
+ EVM_INS_CALLCODE = 242,
+ EVM_INS_RETURN = 243,
+ EVM_INS_DELEGATECALL = 244,
+ EVM_INS_CALLBLACKBOX = 245,
+ EVM_INS_STATICCALL = 250,
+ EVM_INS_REVERT = 253,
+ EVM_INS_SUICIDE = 255,
+
+ EVM_INS_INVALID = 512,
+ EVM_INS_ENDING, // <-- mark the end of the list of instructions
+} evm_insn;
+
+/// Group of EVM instructions
+typedef enum evm_insn_group {
+ EVM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ EVM_GRP_JUMP, ///< all jump instructions
+
+ EVM_GRP_MATH = 8, ///< math instructions
+ EVM_GRP_STACK_WRITE, ///< instructions write to stack
+ EVM_GRP_STACK_READ, ///< instructions read from stack
+ EVM_GRP_MEM_WRITE, ///< instructions write to memory
+ EVM_GRP_MEM_READ, ///< instructions read from memory
+ EVM_GRP_STORE_WRITE, ///< instructions write to storage
+ EVM_GRP_STORE_READ, ///< instructions read from storage
+ EVM_GRP_HALT, ///< instructions halt execution
+
+ EVM_GRP_ENDING, ///< <-- mark the end of the list of groups
+} evm_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/m680x.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/m680x.h
new file mode 100644
index 00000000..c8296e49
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/m680x.h
@@ -0,0 +1,537 @@
+#ifndef CAPSTONE_M680X_H
+#define CAPSTONE_M680X_H
+
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer 2017 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+#define M680X_OPERAND_COUNT 9
+
+/// M680X registers and special registers
+typedef enum m680x_reg {
+ M680X_REG_INVALID = 0,
+
+ M680X_REG_A, ///< M6800/1/2/3/9, HD6301/9
+ M680X_REG_B, ///< M6800/1/2/3/9, HD6301/9
+ M680X_REG_E, ///< HD6309
+ M680X_REG_F, ///< HD6309
+ M680X_REG_0, ///< HD6309
+
+ M680X_REG_D, ///< M6801/3/9, HD6301/9
+ M680X_REG_W, ///< HD6309
+
+ M680X_REG_CC, ///< M6800/1/2/3/9, M6301/9
+ M680X_REG_DP, ///< M6809/M6309
+ M680X_REG_MD, ///< M6309
+
+ M680X_REG_HX, ///< M6808
+ M680X_REG_H, ///< M6808
+ M680X_REG_X, ///< M6800/1/2/3/9, M6301/9
+ M680X_REG_Y, ///< M6809/M6309
+ M680X_REG_S, ///< M6809/M6309
+ M680X_REG_U, ///< M6809/M6309
+ M680X_REG_V, ///< M6309
+
+ M680X_REG_Q, ///< M6309
+
+ M680X_REG_PC, ///< M6800/1/2/3/9, M6301/9
+
+ M680X_REG_TMP2, ///< CPU12
+ M680X_REG_TMP3, ///< CPU12
+
+ M680X_REG_ENDING, ///< <-- mark the end of the list of registers
+} m680x_reg;
+
+/// Operand type for instruction's operands
+typedef enum m680x_op_type {
+ M680X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ M680X_OP_REGISTER, ///< = Register operand.
+ M680X_OP_IMMEDIATE, ///< = Immediate operand.
+ M680X_OP_INDEXED, ///< = Indexed addressing operand.
+ M680X_OP_EXTENDED, ///< = Extended addressing operand.
+ M680X_OP_DIRECT, ///< = Direct addressing operand.
+ M680X_OP_RELATIVE, ///< = Relative addressing operand.
+ M680X_OP_CONSTANT, ///< = constant operand (Displayed as number only).
+ ///< Used e.g. for a bit index or page number.
+} m680x_op_type;
+
+// Supported bit values for mem.idx.offset_bits
+#define M680X_OFFSET_NONE 0
+#define M680X_OFFSET_BITS_5 5
+#define M680X_OFFSET_BITS_8 8
+#define M680X_OFFSET_BITS_9 9
+#define M680X_OFFSET_BITS_16 16
+
+// Supported bit flags for mem.idx.flags
+// These flags can be combined
+#define M680X_IDX_INDIRECT 1
+#define M680X_IDX_NO_COMMA 2
+#define M680X_IDX_POST_INC_DEC 4
+
+/// Instruction's operand referring to indexed addressing
+typedef struct m680x_op_idx {
+ m680x_reg base_reg; ///< base register (or M680X_REG_INVALID if
+ ///< irrelevant)
+ m680x_reg offset_reg; ///< offset register (or M680X_REG_INVALID if
+ ///< irrelevant)
+ int16_t offset; ///< 5-,8- or 16-bit offset. See also offset_bits.
+ uint16_t offset_addr; ///< = offset addr. if base_reg == M680X_REG_PC.
+ ///< calculated as offset + PC
+ uint8_t offset_bits; ///< offset width in bits for indexed addressing
+ int8_t inc_dec; ///< inc. or dec. value:
+ ///< 0: no inc-/decrement
+ ///< 1 .. 8: increment by 1 .. 8
+ ///< -1 .. -8: decrement by 1 .. 8
+ ///< if flag M680X_IDX_POST_INC_DEC set it is post
+ ///< inc-/decrement otherwise pre inc-/decrement
+ uint8_t flags; ///< 8-bit flags (see above)
+} m680x_op_idx;
+
+/// Instruction's memory operand referring to relative addressing (Bcc/LBcc)
+typedef struct m680x_op_rel {
+ uint16_t address; ///< The absolute address.
+ ///< calculated as PC + offset. PC is the first
+ ///< address after the instruction.
+ int16_t offset; ///< the offset/displacement value
+} m680x_op_rel;
+
+/// Instruction's operand referring to extended addressing
+typedef struct m680x_op_ext {
+ uint16_t address; ///< The absolute address
+ bool indirect; ///< true if extended indirect addressing
+} m680x_op_ext;
+
+/// Instruction operand
+typedef struct cs_m680x_op {
+ m680x_op_type type;
+ union {
+ int32_t imm; ///< immediate value for IMM operand
+ m680x_reg reg; ///< register value for REG operand
+ m680x_op_idx idx; ///< Indexed addressing operand
+ m680x_op_rel rel; ///< Relative address. operand (Bcc/LBcc)
+ m680x_op_ext ext; ///< Extended address
+ uint8_t direct_addr; ///< Direct address (lower 8-bit)
+ uint8_t const_val; ///< constant value (bit index, page nr.)
+ };
+ uint8_t size; ///< size of this operand (in bytes)
+ /// How is this operand accessed? (READ, WRITE or READ|WRITE)
+ /// This field is combined of cs_ac_type.
+ /// NOTE: this field is irrelevant if engine is compiled in DIET
+ uint8_t access;
+} cs_m680x_op;
+
+/// Group of M680X instructions
+typedef enum m680x_group_type {
+ M680X_GRP_INVALID = 0, /// = CS_GRP_INVALID
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ M680X_GRP_JUMP, ///< = CS_GRP_JUMP
+ // all call instructions
+ M680X_GRP_CALL, ///< = CS_GRP_CALL
+ // all return instructions
+ M680X_GRP_RET, ///< = CS_GRP_RET
+ // all interrupt instructions (int+syscall)
+ M680X_GRP_INT, ///< = CS_GRP_INT
+ // all interrupt return instructions
+ M680X_GRP_IRET, ///< = CS_GRP_IRET
+ // all privileged instructions
+ M680X_GRP_PRIV, ///< = CS_GRP_PRIVILEDGE; not used
+ // all relative branching instructions
+ M680X_GRP_BRAREL, ///< = CS_GRP_BRANCH_RELATIVE
+
+ // Architecture-specific groups
+ M680X_GRP_ENDING, // <-- mark the end of the list of groups
+} m680x_group_type;
+
+// M680X instruction flags:
+
+/// The first (register) operand is part of the
+/// instruction mnemonic
+#define M680X_FIRST_OP_IN_MNEM 1
+/// The second (register) operand is part of the
+/// instruction mnemonic
+#define M680X_SECOND_OP_IN_MNEM 2
+
+/// The M680X instruction and it's operands
+typedef struct cs_m680x {
+ uint8_t flags; ///< See: M680X instruction flags
+ uint8_t op_count; ///< number of operands for the instruction or 0
+ cs_m680x_op operands[M680X_OPERAND_COUNT]; ///< operands for this insn.
+} cs_m680x;
+
+/// M680X instruction IDs
+typedef enum m680x_insn {
+ M680X_INS_INVLD = 0,
+ M680X_INS_ABA, ///< M6800/1/2/3
+ M680X_INS_ABX,
+ M680X_INS_ABY,
+ M680X_INS_ADC,
+ M680X_INS_ADCA,
+ M680X_INS_ADCB,
+ M680X_INS_ADCD,
+ M680X_INS_ADCR,
+ M680X_INS_ADD,
+ M680X_INS_ADDA,
+ M680X_INS_ADDB,
+ M680X_INS_ADDD,
+ M680X_INS_ADDE,
+ M680X_INS_ADDF,
+ M680X_INS_ADDR,
+ M680X_INS_ADDW,
+ M680X_INS_AIM,
+ M680X_INS_AIS,
+ M680X_INS_AIX,
+ M680X_INS_AND,
+ M680X_INS_ANDA,
+ M680X_INS_ANDB,
+ M680X_INS_ANDCC,
+ M680X_INS_ANDD,
+ M680X_INS_ANDR,
+ M680X_INS_ASL,
+ M680X_INS_ASLA,
+ M680X_INS_ASLB,
+ M680X_INS_ASLD, ///< or LSLD
+ M680X_INS_ASR,
+ M680X_INS_ASRA,
+ M680X_INS_ASRB,
+ M680X_INS_ASRD,
+ M680X_INS_ASRX,
+ M680X_INS_BAND,
+ M680X_INS_BCC, ///< or BHS
+ M680X_INS_BCLR,
+ M680X_INS_BCS, ///< or BLO
+ M680X_INS_BEOR,
+ M680X_INS_BEQ,
+ M680X_INS_BGE,
+ M680X_INS_BGND,
+ M680X_INS_BGT,
+ M680X_INS_BHCC,
+ M680X_INS_BHCS,
+ M680X_INS_BHI,
+ M680X_INS_BIAND,
+ M680X_INS_BIEOR,
+ M680X_INS_BIH,
+ M680X_INS_BIL,
+ M680X_INS_BIOR,
+ M680X_INS_BIT,
+ M680X_INS_BITA,
+ M680X_INS_BITB,
+ M680X_INS_BITD,
+ M680X_INS_BITMD,
+ M680X_INS_BLE,
+ M680X_INS_BLS,
+ M680X_INS_BLT,
+ M680X_INS_BMC,
+ M680X_INS_BMI,
+ M680X_INS_BMS,
+ M680X_INS_BNE,
+ M680X_INS_BOR,
+ M680X_INS_BPL,
+ M680X_INS_BRCLR,
+ M680X_INS_BRSET,
+ M680X_INS_BRA,
+ M680X_INS_BRN,
+ M680X_INS_BSET,
+ M680X_INS_BSR,
+ M680X_INS_BVC,
+ M680X_INS_BVS,
+ M680X_INS_CALL,
+ M680X_INS_CBA, ///< M6800/1/2/3
+ M680X_INS_CBEQ,
+ M680X_INS_CBEQA,
+ M680X_INS_CBEQX,
+ M680X_INS_CLC, ///< M6800/1/2/3
+ M680X_INS_CLI, ///< M6800/1/2/3
+ M680X_INS_CLR,
+ M680X_INS_CLRA,
+ M680X_INS_CLRB,
+ M680X_INS_CLRD,
+ M680X_INS_CLRE,
+ M680X_INS_CLRF,
+ M680X_INS_CLRH,
+ M680X_INS_CLRW,
+ M680X_INS_CLRX,
+ M680X_INS_CLV, ///< M6800/1/2/3
+ M680X_INS_CMP,
+ M680X_INS_CMPA,
+ M680X_INS_CMPB,
+ M680X_INS_CMPD,
+ M680X_INS_CMPE,
+ M680X_INS_CMPF,
+ M680X_INS_CMPR,
+ M680X_INS_CMPS,
+ M680X_INS_CMPU,
+ M680X_INS_CMPW,
+ M680X_INS_CMPX,
+ M680X_INS_CMPY,
+ M680X_INS_COM,
+ M680X_INS_COMA,
+ M680X_INS_COMB,
+ M680X_INS_COMD,
+ M680X_INS_COME,
+ M680X_INS_COMF,
+ M680X_INS_COMW,
+ M680X_INS_COMX,
+ M680X_INS_CPD,
+ M680X_INS_CPHX,
+ M680X_INS_CPS,
+ M680X_INS_CPX, ///< M6800/1/2/3
+ M680X_INS_CPY,
+ M680X_INS_CWAI,
+ M680X_INS_DAA,
+ M680X_INS_DBEQ,
+ M680X_INS_DBNE,
+ M680X_INS_DBNZ,
+ M680X_INS_DBNZA,
+ M680X_INS_DBNZX,
+ M680X_INS_DEC,
+ M680X_INS_DECA,
+ M680X_INS_DECB,
+ M680X_INS_DECD,
+ M680X_INS_DECE,
+ M680X_INS_DECF,
+ M680X_INS_DECW,
+ M680X_INS_DECX,
+ M680X_INS_DES, ///< M6800/1/2/3
+ M680X_INS_DEX, ///< M6800/1/2/3
+ M680X_INS_DEY,
+ M680X_INS_DIV,
+ M680X_INS_DIVD,
+ M680X_INS_DIVQ,
+ M680X_INS_EDIV,
+ M680X_INS_EDIVS,
+ M680X_INS_EIM,
+ M680X_INS_EMACS,
+ M680X_INS_EMAXD,
+ M680X_INS_EMAXM,
+ M680X_INS_EMIND,
+ M680X_INS_EMINM,
+ M680X_INS_EMUL,
+ M680X_INS_EMULS,
+ M680X_INS_EOR,
+ M680X_INS_EORA,
+ M680X_INS_EORB,
+ M680X_INS_EORD,
+ M680X_INS_EORR,
+ M680X_INS_ETBL,
+ M680X_INS_EXG,
+ M680X_INS_FDIV,
+ M680X_INS_IBEQ,
+ M680X_INS_IBNE,
+ M680X_INS_IDIV,
+ M680X_INS_IDIVS,
+ M680X_INS_ILLGL,
+ M680X_INS_INC,
+ M680X_INS_INCA,
+ M680X_INS_INCB,
+ M680X_INS_INCD,
+ M680X_INS_INCE,
+ M680X_INS_INCF,
+ M680X_INS_INCW,
+ M680X_INS_INCX,
+ M680X_INS_INS, ///< M6800/1/2/3
+ M680X_INS_INX, ///< M6800/1/2/3
+ M680X_INS_INY,
+ M680X_INS_JMP,
+ M680X_INS_JSR,
+ M680X_INS_LBCC, ///< or LBHS
+ M680X_INS_LBCS, ///< or LBLO
+ M680X_INS_LBEQ,
+ M680X_INS_LBGE,
+ M680X_INS_LBGT,
+ M680X_INS_LBHI,
+ M680X_INS_LBLE,
+ M680X_INS_LBLS,
+ M680X_INS_LBLT,
+ M680X_INS_LBMI,
+ M680X_INS_LBNE,
+ M680X_INS_LBPL,
+ M680X_INS_LBRA,
+ M680X_INS_LBRN,
+ M680X_INS_LBSR,
+ M680X_INS_LBVC,
+ M680X_INS_LBVS,
+ M680X_INS_LDA,
+ M680X_INS_LDAA, ///< M6800/1/2/3
+ M680X_INS_LDAB, ///< M6800/1/2/3
+ M680X_INS_LDB,
+ M680X_INS_LDBT,
+ M680X_INS_LDD,
+ M680X_INS_LDE,
+ M680X_INS_LDF,
+ M680X_INS_LDHX,
+ M680X_INS_LDMD,
+ M680X_INS_LDQ,
+ M680X_INS_LDS,
+ M680X_INS_LDU,
+ M680X_INS_LDW,
+ M680X_INS_LDX,
+ M680X_INS_LDY,
+ M680X_INS_LEAS,
+ M680X_INS_LEAU,
+ M680X_INS_LEAX,
+ M680X_INS_LEAY,
+ M680X_INS_LSL,
+ M680X_INS_LSLA,
+ M680X_INS_LSLB,
+ M680X_INS_LSLD,
+ M680X_INS_LSLX,
+ M680X_INS_LSR,
+ M680X_INS_LSRA,
+ M680X_INS_LSRB,
+ M680X_INS_LSRD, ///< or ASRD
+ M680X_INS_LSRW,
+ M680X_INS_LSRX,
+ M680X_INS_MAXA,
+ M680X_INS_MAXM,
+ M680X_INS_MEM,
+ M680X_INS_MINA,
+ M680X_INS_MINM,
+ M680X_INS_MOV,
+ M680X_INS_MOVB,
+ M680X_INS_MOVW,
+ M680X_INS_MUL,
+ M680X_INS_MULD,
+ M680X_INS_NEG,
+ M680X_INS_NEGA,
+ M680X_INS_NEGB,
+ M680X_INS_NEGD,
+ M680X_INS_NEGX,
+ M680X_INS_NOP,
+ M680X_INS_NSA,
+ M680X_INS_OIM,
+ M680X_INS_ORA,
+ M680X_INS_ORAA, ///< M6800/1/2/3
+ M680X_INS_ORAB, ///< M6800/1/2/3
+ M680X_INS_ORB,
+ M680X_INS_ORCC,
+ M680X_INS_ORD,
+ M680X_INS_ORR,
+ M680X_INS_PSHA, ///< M6800/1/2/3
+ M680X_INS_PSHB, ///< M6800/1/2/3
+ M680X_INS_PSHC,
+ M680X_INS_PSHD,
+ M680X_INS_PSHH,
+ M680X_INS_PSHS,
+ M680X_INS_PSHSW,
+ M680X_INS_PSHU,
+ M680X_INS_PSHUW,
+ M680X_INS_PSHX, ///< M6800/1/2/3
+ M680X_INS_PSHY,
+ M680X_INS_PULA, ///< M6800/1/2/3
+ M680X_INS_PULB, ///< M6800/1/2/3
+ M680X_INS_PULC,
+ M680X_INS_PULD,
+ M680X_INS_PULH,
+ M680X_INS_PULS,
+ M680X_INS_PULSW,
+ M680X_INS_PULU,
+ M680X_INS_PULUW,
+ M680X_INS_PULX, ///< M6800/1/2/3
+ M680X_INS_PULY,
+ M680X_INS_REV,
+ M680X_INS_REVW,
+ M680X_INS_ROL,
+ M680X_INS_ROLA,
+ M680X_INS_ROLB,
+ M680X_INS_ROLD,
+ M680X_INS_ROLW,
+ M680X_INS_ROLX,
+ M680X_INS_ROR,
+ M680X_INS_RORA,
+ M680X_INS_RORB,
+ M680X_INS_RORD,
+ M680X_INS_RORW,
+ M680X_INS_RORX,
+ M680X_INS_RSP,
+ M680X_INS_RTC,
+ M680X_INS_RTI,
+ M680X_INS_RTS,
+ M680X_INS_SBA, ///< M6800/1/2/3
+ M680X_INS_SBC,
+ M680X_INS_SBCA,
+ M680X_INS_SBCB,
+ M680X_INS_SBCD,
+ M680X_INS_SBCR,
+ M680X_INS_SEC,
+ M680X_INS_SEI,
+ M680X_INS_SEV,
+ M680X_INS_SEX,
+ M680X_INS_SEXW,
+ M680X_INS_SLP,
+ M680X_INS_STA,
+ M680X_INS_STAA, ///< M6800/1/2/3
+ M680X_INS_STAB, ///< M6800/1/2/3
+ M680X_INS_STB,
+ M680X_INS_STBT,
+ M680X_INS_STD,
+ M680X_INS_STE,
+ M680X_INS_STF,
+ M680X_INS_STOP,
+ M680X_INS_STHX,
+ M680X_INS_STQ,
+ M680X_INS_STS,
+ M680X_INS_STU,
+ M680X_INS_STW,
+ M680X_INS_STX,
+ M680X_INS_STY,
+ M680X_INS_SUB,
+ M680X_INS_SUBA,
+ M680X_INS_SUBB,
+ M680X_INS_SUBD,
+ M680X_INS_SUBE,
+ M680X_INS_SUBF,
+ M680X_INS_SUBR,
+ M680X_INS_SUBW,
+ M680X_INS_SWI,
+ M680X_INS_SWI2,
+ M680X_INS_SWI3,
+ M680X_INS_SYNC,
+ M680X_INS_TAB, ///< M6800/1/2/3
+ M680X_INS_TAP, ///< M6800/1/2/3
+ M680X_INS_TAX,
+ M680X_INS_TBA, ///< M6800/1/2/3
+ M680X_INS_TBEQ,
+ M680X_INS_TBL,
+ M680X_INS_TBNE,
+ M680X_INS_TEST,
+ M680X_INS_TFM,
+ M680X_INS_TFR,
+ M680X_INS_TIM,
+ M680X_INS_TPA, ///< M6800/1/2/3
+ M680X_INS_TST,
+ M680X_INS_TSTA,
+ M680X_INS_TSTB,
+ M680X_INS_TSTD,
+ M680X_INS_TSTE,
+ M680X_INS_TSTF,
+ M680X_INS_TSTW,
+ M680X_INS_TSTX,
+ M680X_INS_TSX, ///< M6800/1/2/3
+ M680X_INS_TSY,
+ M680X_INS_TXA,
+ M680X_INS_TXS, ///< M6800/1/2/3
+ M680X_INS_TYS,
+ M680X_INS_WAI, ///< M6800/1/2/3
+ M680X_INS_WAIT,
+ M680X_INS_WAV,
+ M680X_INS_WAVR,
+ M680X_INS_XGDX, ///< HD6301
+ M680X_INS_XGDY,
+ M680X_INS_ENDING, // <-- mark the end of the list of instructions
+} m680x_insn;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/m68k.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/m68k.h
new file mode 100644
index 00000000..41e23f38
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/m68k.h
@@ -0,0 +1,613 @@
+#ifndef CAPSTONE_M68K_H
+#define CAPSTONE_M68K_H
+
+/* Capstone Disassembly Engine */
+/* By Daniel Collin , 2015-2016 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+#define M68K_OPERAND_COUNT 4
+
+/// M68K registers and special registers
+typedef enum m68k_reg {
+ M68K_REG_INVALID = 0,
+
+ M68K_REG_D0,
+ M68K_REG_D1,
+ M68K_REG_D2,
+ M68K_REG_D3,
+ M68K_REG_D4,
+ M68K_REG_D5,
+ M68K_REG_D6,
+ M68K_REG_D7,
+
+ M68K_REG_A0,
+ M68K_REG_A1,
+ M68K_REG_A2,
+ M68K_REG_A3,
+ M68K_REG_A4,
+ M68K_REG_A5,
+ M68K_REG_A6,
+ M68K_REG_A7,
+
+ M68K_REG_FP0,
+ M68K_REG_FP1,
+ M68K_REG_FP2,
+ M68K_REG_FP3,
+ M68K_REG_FP4,
+ M68K_REG_FP5,
+ M68K_REG_FP6,
+ M68K_REG_FP7,
+
+ M68K_REG_PC,
+
+ M68K_REG_SR,
+ M68K_REG_CCR,
+ M68K_REG_SFC,
+ M68K_REG_DFC,
+ M68K_REG_USP,
+ M68K_REG_VBR,
+ M68K_REG_CACR,
+ M68K_REG_CAAR,
+ M68K_REG_MSP,
+ M68K_REG_ISP,
+ M68K_REG_TC,
+ M68K_REG_ITT0,
+ M68K_REG_ITT1,
+ M68K_REG_DTT0,
+ M68K_REG_DTT1,
+ M68K_REG_MMUSR,
+ M68K_REG_URP,
+ M68K_REG_SRP,
+
+ M68K_REG_FPCR,
+ M68K_REG_FPSR,
+ M68K_REG_FPIAR,
+
+ M68K_REG_ENDING, // <-- mark the end of the list of registers
+} m68k_reg;
+
+/// M68K Addressing Modes
+typedef enum m68k_address_mode {
+ M68K_AM_NONE = 0, ///< No address mode.
+
+ M68K_AM_REG_DIRECT_DATA, ///< Register Direct - Data
+ M68K_AM_REG_DIRECT_ADDR, ///< Register Direct - Address
+
+ M68K_AM_REGI_ADDR, ///< Register Indirect - Address
+ M68K_AM_REGI_ADDR_POST_INC, ///< Register Indirect - Address with Postincrement
+ M68K_AM_REGI_ADDR_PRE_DEC, ///< Register Indirect - Address with Predecrement
+ M68K_AM_REGI_ADDR_DISP, ///< Register Indirect - Address with Displacement
+
+ M68K_AM_AREGI_INDEX_8_BIT_DISP, ///< Address Register Indirect With Index- 8-bit displacement
+ M68K_AM_AREGI_INDEX_BASE_DISP, ///< Address Register Indirect With Index- Base displacement
+
+ M68K_AM_MEMI_POST_INDEX, ///< Memory indirect - Postindex
+ M68K_AM_MEMI_PRE_INDEX, ///< Memory indirect - Preindex
+
+ M68K_AM_PCI_DISP, ///< Program Counter Indirect - with Displacement
+
+ M68K_AM_PCI_INDEX_8_BIT_DISP, ///< Program Counter Indirect with Index - with 8-Bit Displacement
+ M68K_AM_PCI_INDEX_BASE_DISP, ///< Program Counter Indirect with Index - with Base Displacement
+
+ M68K_AM_PC_MEMI_POST_INDEX, ///< Program Counter Memory Indirect - Postindexed
+ M68K_AM_PC_MEMI_PRE_INDEX, ///< Program Counter Memory Indirect - Preindexed
+
+ M68K_AM_ABSOLUTE_DATA_SHORT, ///< Absolute Data Addressing - Short
+ M68K_AM_ABSOLUTE_DATA_LONG, ///< Absolute Data Addressing - Long
+ M68K_AM_IMMEDIATE, ///< Immediate value
+
+ M68K_AM_BRANCH_DISPLACEMENT, ///< Address as displacement from (PC+2) used by branches
+} m68k_address_mode;
+
+/// Operand type for instruction's operands
+typedef enum m68k_op_type {
+ M68K_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ M68K_OP_REG, ///< = CS_OP_REG (Register operand).
+ M68K_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ M68K_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+ M68K_OP_FP_SINGLE, ///< single precision Floating-Point operand
+ M68K_OP_FP_DOUBLE, ///< double precision Floating-Point operand
+ M68K_OP_REG_BITS, ///< Register bits move
+ M68K_OP_REG_PAIR, ///< Register pair in the same op (upper 4 bits for first reg, lower for second)
+ M68K_OP_BR_DISP, ///< Branch displacement
+} m68k_op_type;
+
+/// Instruction's operand referring to memory
+/// This is associated with M68K_OP_MEM operand type above
+typedef struct m68k_op_mem {
+ m68k_reg base_reg; ///< base register (or M68K_REG_INVALID if irrelevant)
+ m68k_reg index_reg; ///< index register (or M68K_REG_INVALID if irrelevant)
+ m68k_reg in_base_reg; ///< indirect base register (or M68K_REG_INVALID if irrelevant)
+ uint32_t in_disp; ///< indirect displacement
+ uint32_t out_disp; ///< other displacement
+ int16_t disp; ///< displacement value
+ uint8_t scale; ///< scale for index register
+ uint8_t bitfield; ///< set to true if the two values below should be used
+ uint8_t width; ///< used for bf* instructions
+ uint8_t offset; ///< used for bf* instructions
+ uint8_t index_size; ///< 0 = w, 1 = l
+} m68k_op_mem;
+
+/// Operand type for instruction's operands
+typedef enum m68k_op_br_disp_size {
+ M68K_OP_BR_DISP_SIZE_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ M68K_OP_BR_DISP_SIZE_BYTE = 1, ///< signed 8-bit displacement
+ M68K_OP_BR_DISP_SIZE_WORD = 2, ///< signed 16-bit displacement
+ M68K_OP_BR_DISP_SIZE_LONG = 4, ///< signed 32-bit displacement
+} m68k_op_br_disp_size;
+
+typedef struct m68k_op_br_disp {
+ int32_t disp; ///< displacement value
+ uint8_t disp_size; ///< Size from m68k_op_br_disp_size type above
+} m68k_op_br_disp;
+
+/// Register pair in one operand.
+typedef struct cs_m68k_op_reg_pair {
+ m68k_reg reg_0;
+ m68k_reg reg_1;
+} cs_m68k_op_reg_pair;
+
+/// Instruction operand
+typedef struct cs_m68k_op {
+ union {
+ uint64_t imm; ///< immediate value for IMM operand
+ double dimm; ///< double imm
+ float simm; ///< float imm
+ m68k_reg reg; ///< register value for REG operand
+ cs_m68k_op_reg_pair reg_pair; ///< register pair in one operand
+ };
+
+ m68k_op_mem mem; ///< data when operand is targeting memory
+ m68k_op_br_disp br_disp; ///< data when operand is a branch displacement
+ uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)
+ m68k_op_type type;
+ m68k_address_mode address_mode; ///< M68K addressing mode for this op
+} cs_m68k_op;
+
+/// Operation size of the CPU instructions
+typedef enum m68k_cpu_size {
+ M68K_CPU_SIZE_NONE = 0, ///< unsized or unspecified
+ M68K_CPU_SIZE_BYTE = 1, ///< 1 byte in size
+ M68K_CPU_SIZE_WORD = 2, ///< 2 bytes in size
+ M68K_CPU_SIZE_LONG = 4, ///< 4 bytes in size
+} m68k_cpu_size;
+
+/// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)
+typedef enum m68k_fpu_size {
+ M68K_FPU_SIZE_NONE = 0, ///< unsized like fsave/frestore
+ M68K_FPU_SIZE_SINGLE = 4, ///< 4 byte in size (single float)
+ M68K_FPU_SIZE_DOUBLE = 8, ///< 8 byte in size (double)
+ M68K_FPU_SIZE_EXTENDED = 12, ///< 12 byte in size (extended real format)
+} m68k_fpu_size;
+
+/// Type of size that is being used for the current instruction
+typedef enum m68k_size_type {
+ M68K_SIZE_TYPE_INVALID = 0,
+
+ M68K_SIZE_TYPE_CPU,
+ M68K_SIZE_TYPE_FPU,
+} m68k_size_type;
+
+/// Operation size of the current instruction (NOT the actually size of instruction)
+typedef struct m68k_op_size {
+ m68k_size_type type;
+ union {
+ m68k_cpu_size cpu_size;
+ m68k_fpu_size fpu_size;
+ };
+} m68k_op_size;
+
+/// The M68K instruction and it's operands
+typedef struct cs_m68k {
+ // Number of operands of this instruction or 0 when instruction has no operand.
+ cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction.
+ m68k_op_size op_size; ///< size of data operand works on in bytes (.b, .w, .l, etc)
+ uint8_t op_count; ///< number of operands for the instruction
+} cs_m68k;
+
+/// M68K instruction
+typedef enum m68k_insn {
+ M68K_INS_INVALID = 0,
+
+ M68K_INS_ABCD,
+ M68K_INS_ADD,
+ M68K_INS_ADDA,
+ M68K_INS_ADDI,
+ M68K_INS_ADDQ,
+ M68K_INS_ADDX,
+ M68K_INS_AND,
+ M68K_INS_ANDI,
+ M68K_INS_ASL,
+ M68K_INS_ASR,
+ M68K_INS_BHS,
+ M68K_INS_BLO,
+ M68K_INS_BHI,
+ M68K_INS_BLS,
+ M68K_INS_BCC,
+ M68K_INS_BCS,
+ M68K_INS_BNE,
+ M68K_INS_BEQ,
+ M68K_INS_BVC,
+ M68K_INS_BVS,
+ M68K_INS_BPL,
+ M68K_INS_BMI,
+ M68K_INS_BGE,
+ M68K_INS_BLT,
+ M68K_INS_BGT,
+ M68K_INS_BLE,
+ M68K_INS_BRA,
+ M68K_INS_BSR,
+ M68K_INS_BCHG,
+ M68K_INS_BCLR,
+ M68K_INS_BSET,
+ M68K_INS_BTST,
+ M68K_INS_BFCHG,
+ M68K_INS_BFCLR,
+ M68K_INS_BFEXTS,
+ M68K_INS_BFEXTU,
+ M68K_INS_BFFFO,
+ M68K_INS_BFINS,
+ M68K_INS_BFSET,
+ M68K_INS_BFTST,
+ M68K_INS_BKPT,
+ M68K_INS_CALLM,
+ M68K_INS_CAS,
+ M68K_INS_CAS2,
+ M68K_INS_CHK,
+ M68K_INS_CHK2,
+ M68K_INS_CLR,
+ M68K_INS_CMP,
+ M68K_INS_CMPA,
+ M68K_INS_CMPI,
+ M68K_INS_CMPM,
+ M68K_INS_CMP2,
+ M68K_INS_CINVL,
+ M68K_INS_CINVP,
+ M68K_INS_CINVA,
+ M68K_INS_CPUSHL,
+ M68K_INS_CPUSHP,
+ M68K_INS_CPUSHA,
+ M68K_INS_DBT,
+ M68K_INS_DBF,
+ M68K_INS_DBHI,
+ M68K_INS_DBLS,
+ M68K_INS_DBCC,
+ M68K_INS_DBCS,
+ M68K_INS_DBNE,
+ M68K_INS_DBEQ,
+ M68K_INS_DBVC,
+ M68K_INS_DBVS,
+ M68K_INS_DBPL,
+ M68K_INS_DBMI,
+ M68K_INS_DBGE,
+ M68K_INS_DBLT,
+ M68K_INS_DBGT,
+ M68K_INS_DBLE,
+ M68K_INS_DBRA,
+ M68K_INS_DIVS,
+ M68K_INS_DIVSL,
+ M68K_INS_DIVU,
+ M68K_INS_DIVUL,
+ M68K_INS_EOR,
+ M68K_INS_EORI,
+ M68K_INS_EXG,
+ M68K_INS_EXT,
+ M68K_INS_EXTB,
+ M68K_INS_FABS,
+ M68K_INS_FSABS,
+ M68K_INS_FDABS,
+ M68K_INS_FACOS,
+ M68K_INS_FADD,
+ M68K_INS_FSADD,
+ M68K_INS_FDADD,
+ M68K_INS_FASIN,
+ M68K_INS_FATAN,
+ M68K_INS_FATANH,
+ M68K_INS_FBF,
+ M68K_INS_FBEQ,
+ M68K_INS_FBOGT,
+ M68K_INS_FBOGE,
+ M68K_INS_FBOLT,
+ M68K_INS_FBOLE,
+ M68K_INS_FBOGL,
+ M68K_INS_FBOR,
+ M68K_INS_FBUN,
+ M68K_INS_FBUEQ,
+ M68K_INS_FBUGT,
+ M68K_INS_FBUGE,
+ M68K_INS_FBULT,
+ M68K_INS_FBULE,
+ M68K_INS_FBNE,
+ M68K_INS_FBT,
+ M68K_INS_FBSF,
+ M68K_INS_FBSEQ,
+ M68K_INS_FBGT,
+ M68K_INS_FBGE,
+ M68K_INS_FBLT,
+ M68K_INS_FBLE,
+ M68K_INS_FBGL,
+ M68K_INS_FBGLE,
+ M68K_INS_FBNGLE,
+ M68K_INS_FBNGL,
+ M68K_INS_FBNLE,
+ M68K_INS_FBNLT,
+ M68K_INS_FBNGE,
+ M68K_INS_FBNGT,
+ M68K_INS_FBSNE,
+ M68K_INS_FBST,
+ M68K_INS_FCMP,
+ M68K_INS_FCOS,
+ M68K_INS_FCOSH,
+ M68K_INS_FDBF,
+ M68K_INS_FDBEQ,
+ M68K_INS_FDBOGT,
+ M68K_INS_FDBOGE,
+ M68K_INS_FDBOLT,
+ M68K_INS_FDBOLE,
+ M68K_INS_FDBOGL,
+ M68K_INS_FDBOR,
+ M68K_INS_FDBUN,
+ M68K_INS_FDBUEQ,
+ M68K_INS_FDBUGT,
+ M68K_INS_FDBUGE,
+ M68K_INS_FDBULT,
+ M68K_INS_FDBULE,
+ M68K_INS_FDBNE,
+ M68K_INS_FDBT,
+ M68K_INS_FDBSF,
+ M68K_INS_FDBSEQ,
+ M68K_INS_FDBGT,
+ M68K_INS_FDBGE,
+ M68K_INS_FDBLT,
+ M68K_INS_FDBLE,
+ M68K_INS_FDBGL,
+ M68K_INS_FDBGLE,
+ M68K_INS_FDBNGLE,
+ M68K_INS_FDBNGL,
+ M68K_INS_FDBNLE,
+ M68K_INS_FDBNLT,
+ M68K_INS_FDBNGE,
+ M68K_INS_FDBNGT,
+ M68K_INS_FDBSNE,
+ M68K_INS_FDBST,
+ M68K_INS_FDIV,
+ M68K_INS_FSDIV,
+ M68K_INS_FDDIV,
+ M68K_INS_FETOX,
+ M68K_INS_FETOXM1,
+ M68K_INS_FGETEXP,
+ M68K_INS_FGETMAN,
+ M68K_INS_FINT,
+ M68K_INS_FINTRZ,
+ M68K_INS_FLOG10,
+ M68K_INS_FLOG2,
+ M68K_INS_FLOGN,
+ M68K_INS_FLOGNP1,
+ M68K_INS_FMOD,
+ M68K_INS_FMOVE,
+ M68K_INS_FSMOVE,
+ M68K_INS_FDMOVE,
+ M68K_INS_FMOVECR,
+ M68K_INS_FMOVEM,
+ M68K_INS_FMUL,
+ M68K_INS_FSMUL,
+ M68K_INS_FDMUL,
+ M68K_INS_FNEG,
+ M68K_INS_FSNEG,
+ M68K_INS_FDNEG,
+ M68K_INS_FNOP,
+ M68K_INS_FREM,
+ M68K_INS_FRESTORE,
+ M68K_INS_FSAVE,
+ M68K_INS_FSCALE,
+ M68K_INS_FSGLDIV,
+ M68K_INS_FSGLMUL,
+ M68K_INS_FSIN,
+ M68K_INS_FSINCOS,
+ M68K_INS_FSINH,
+ M68K_INS_FSQRT,
+ M68K_INS_FSSQRT,
+ M68K_INS_FDSQRT,
+ M68K_INS_FSF,
+ M68K_INS_FSBEQ,
+ M68K_INS_FSOGT,
+ M68K_INS_FSOGE,
+ M68K_INS_FSOLT,
+ M68K_INS_FSOLE,
+ M68K_INS_FSOGL,
+ M68K_INS_FSOR,
+ M68K_INS_FSUN,
+ M68K_INS_FSUEQ,
+ M68K_INS_FSUGT,
+ M68K_INS_FSUGE,
+ M68K_INS_FSULT,
+ M68K_INS_FSULE,
+ M68K_INS_FSNE,
+ M68K_INS_FST,
+ M68K_INS_FSSF,
+ M68K_INS_FSSEQ,
+ M68K_INS_FSGT,
+ M68K_INS_FSGE,
+ M68K_INS_FSLT,
+ M68K_INS_FSLE,
+ M68K_INS_FSGL,
+ M68K_INS_FSGLE,
+ M68K_INS_FSNGLE,
+ M68K_INS_FSNGL,
+ M68K_INS_FSNLE,
+ M68K_INS_FSNLT,
+ M68K_INS_FSNGE,
+ M68K_INS_FSNGT,
+ M68K_INS_FSSNE,
+ M68K_INS_FSST,
+ M68K_INS_FSUB,
+ M68K_INS_FSSUB,
+ M68K_INS_FDSUB,
+ M68K_INS_FTAN,
+ M68K_INS_FTANH,
+ M68K_INS_FTENTOX,
+ M68K_INS_FTRAPF,
+ M68K_INS_FTRAPEQ,
+ M68K_INS_FTRAPOGT,
+ M68K_INS_FTRAPOGE,
+ M68K_INS_FTRAPOLT,
+ M68K_INS_FTRAPOLE,
+ M68K_INS_FTRAPOGL,
+ M68K_INS_FTRAPOR,
+ M68K_INS_FTRAPUN,
+ M68K_INS_FTRAPUEQ,
+ M68K_INS_FTRAPUGT,
+ M68K_INS_FTRAPUGE,
+ M68K_INS_FTRAPULT,
+ M68K_INS_FTRAPULE,
+ M68K_INS_FTRAPNE,
+ M68K_INS_FTRAPT,
+ M68K_INS_FTRAPSF,
+ M68K_INS_FTRAPSEQ,
+ M68K_INS_FTRAPGT,
+ M68K_INS_FTRAPGE,
+ M68K_INS_FTRAPLT,
+ M68K_INS_FTRAPLE,
+ M68K_INS_FTRAPGL,
+ M68K_INS_FTRAPGLE,
+ M68K_INS_FTRAPNGLE,
+ M68K_INS_FTRAPNGL,
+ M68K_INS_FTRAPNLE,
+ M68K_INS_FTRAPNLT,
+ M68K_INS_FTRAPNGE,
+ M68K_INS_FTRAPNGT,
+ M68K_INS_FTRAPSNE,
+ M68K_INS_FTRAPST,
+ M68K_INS_FTST,
+ M68K_INS_FTWOTOX,
+ M68K_INS_HALT,
+ M68K_INS_ILLEGAL,
+ M68K_INS_JMP,
+ M68K_INS_JSR,
+ M68K_INS_LEA,
+ M68K_INS_LINK,
+ M68K_INS_LPSTOP,
+ M68K_INS_LSL,
+ M68K_INS_LSR,
+ M68K_INS_MOVE,
+ M68K_INS_MOVEA,
+ M68K_INS_MOVEC,
+ M68K_INS_MOVEM,
+ M68K_INS_MOVEP,
+ M68K_INS_MOVEQ,
+ M68K_INS_MOVES,
+ M68K_INS_MOVE16,
+ M68K_INS_MULS,
+ M68K_INS_MULU,
+ M68K_INS_NBCD,
+ M68K_INS_NEG,
+ M68K_INS_NEGX,
+ M68K_INS_NOP,
+ M68K_INS_NOT,
+ M68K_INS_OR,
+ M68K_INS_ORI,
+ M68K_INS_PACK,
+ M68K_INS_PEA,
+ M68K_INS_PFLUSH,
+ M68K_INS_PFLUSHA,
+ M68K_INS_PFLUSHAN,
+ M68K_INS_PFLUSHN,
+ M68K_INS_PLOADR,
+ M68K_INS_PLOADW,
+ M68K_INS_PLPAR,
+ M68K_INS_PLPAW,
+ M68K_INS_PMOVE,
+ M68K_INS_PMOVEFD,
+ M68K_INS_PTESTR,
+ M68K_INS_PTESTW,
+ M68K_INS_PULSE,
+ M68K_INS_REMS,
+ M68K_INS_REMU,
+ M68K_INS_RESET,
+ M68K_INS_ROL,
+ M68K_INS_ROR,
+ M68K_INS_ROXL,
+ M68K_INS_ROXR,
+ M68K_INS_RTD,
+ M68K_INS_RTE,
+ M68K_INS_RTM,
+ M68K_INS_RTR,
+ M68K_INS_RTS,
+ M68K_INS_SBCD,
+ M68K_INS_ST,
+ M68K_INS_SF,
+ M68K_INS_SHI,
+ M68K_INS_SLS,
+ M68K_INS_SCC,
+ M68K_INS_SHS,
+ M68K_INS_SCS,
+ M68K_INS_SLO,
+ M68K_INS_SNE,
+ M68K_INS_SEQ,
+ M68K_INS_SVC,
+ M68K_INS_SVS,
+ M68K_INS_SPL,
+ M68K_INS_SMI,
+ M68K_INS_SGE,
+ M68K_INS_SLT,
+ M68K_INS_SGT,
+ M68K_INS_SLE,
+ M68K_INS_STOP,
+ M68K_INS_SUB,
+ M68K_INS_SUBA,
+ M68K_INS_SUBI,
+ M68K_INS_SUBQ,
+ M68K_INS_SUBX,
+ M68K_INS_SWAP,
+ M68K_INS_TAS,
+ M68K_INS_TRAP,
+ M68K_INS_TRAPV,
+ M68K_INS_TRAPT,
+ M68K_INS_TRAPF,
+ M68K_INS_TRAPHI,
+ M68K_INS_TRAPLS,
+ M68K_INS_TRAPCC,
+ M68K_INS_TRAPHS,
+ M68K_INS_TRAPCS,
+ M68K_INS_TRAPLO,
+ M68K_INS_TRAPNE,
+ M68K_INS_TRAPEQ,
+ M68K_INS_TRAPVC,
+ M68K_INS_TRAPVS,
+ M68K_INS_TRAPPL,
+ M68K_INS_TRAPMI,
+ M68K_INS_TRAPGE,
+ M68K_INS_TRAPLT,
+ M68K_INS_TRAPGT,
+ M68K_INS_TRAPLE,
+ M68K_INS_TST,
+ M68K_INS_UNLK,
+ M68K_INS_UNPK,
+ M68K_INS_ENDING, // <-- mark the end of the list of instructions
+} m68k_insn;
+
+/// Group of M68K instructions
+typedef enum m68k_group_type {
+ M68K_GRP_INVALID = 0, ///< CS_GRUP_INVALID
+ M68K_GRP_JUMP, ///< = CS_GRP_JUMP
+ M68K_GRP_RET = 3, ///< = CS_GRP_RET
+ M68K_GRP_IRET = 5, ///< = CS_GRP_IRET
+ M68K_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE
+
+ M68K_GRP_ENDING,// <-- mark the end of the list of groups
+} m68k_group_type;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/mips.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/mips.h
new file mode 100644
index 00000000..f10c3033
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/mips.h
@@ -0,0 +1,956 @@
+#ifndef CAPSTONE_MIPS_H
+#define CAPSTONE_MIPS_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2013-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+// GCC MIPS toolchain has a default macro called "mips" which breaks
+// compilation
+#undef mips
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Operand type for instruction's operands
+typedef enum mips_op_type {
+ MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ MIPS_OP_REG, ///< = CS_OP_REG (Register operand).
+ MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} mips_op_type;
+
+/// MIPS registers
+typedef enum mips_reg {
+ MIPS_REG_INVALID = 0,
+ // General purpose registers
+ MIPS_REG_PC,
+
+ MIPS_REG_0,
+ MIPS_REG_1,
+ MIPS_REG_2,
+ MIPS_REG_3,
+ MIPS_REG_4,
+ MIPS_REG_5,
+ MIPS_REG_6,
+ MIPS_REG_7,
+ MIPS_REG_8,
+ MIPS_REG_9,
+ MIPS_REG_10,
+ MIPS_REG_11,
+ MIPS_REG_12,
+ MIPS_REG_13,
+ MIPS_REG_14,
+ MIPS_REG_15,
+ MIPS_REG_16,
+ MIPS_REG_17,
+ MIPS_REG_18,
+ MIPS_REG_19,
+ MIPS_REG_20,
+ MIPS_REG_21,
+ MIPS_REG_22,
+ MIPS_REG_23,
+ MIPS_REG_24,
+ MIPS_REG_25,
+ MIPS_REG_26,
+ MIPS_REG_27,
+ MIPS_REG_28,
+ MIPS_REG_29,
+ MIPS_REG_30,
+ MIPS_REG_31,
+
+ // DSP registers
+ MIPS_REG_DSPCCOND,
+ MIPS_REG_DSPCARRY,
+ MIPS_REG_DSPEFI,
+ MIPS_REG_DSPOUTFLAG,
+ MIPS_REG_DSPOUTFLAG16_19,
+ MIPS_REG_DSPOUTFLAG20,
+ MIPS_REG_DSPOUTFLAG21,
+ MIPS_REG_DSPOUTFLAG22,
+ MIPS_REG_DSPOUTFLAG23,
+ MIPS_REG_DSPPOS,
+ MIPS_REG_DSPSCOUNT,
+
+ // ACC registers
+ MIPS_REG_AC0,
+ MIPS_REG_AC1,
+ MIPS_REG_AC2,
+ MIPS_REG_AC3,
+
+ // COP registers
+ MIPS_REG_CC0,
+ MIPS_REG_CC1,
+ MIPS_REG_CC2,
+ MIPS_REG_CC3,
+ MIPS_REG_CC4,
+ MIPS_REG_CC5,
+ MIPS_REG_CC6,
+ MIPS_REG_CC7,
+
+ // FPU registers
+ MIPS_REG_F0,
+ MIPS_REG_F1,
+ MIPS_REG_F2,
+ MIPS_REG_F3,
+ MIPS_REG_F4,
+ MIPS_REG_F5,
+ MIPS_REG_F6,
+ MIPS_REG_F7,
+ MIPS_REG_F8,
+ MIPS_REG_F9,
+ MIPS_REG_F10,
+ MIPS_REG_F11,
+ MIPS_REG_F12,
+ MIPS_REG_F13,
+ MIPS_REG_F14,
+ MIPS_REG_F15,
+ MIPS_REG_F16,
+ MIPS_REG_F17,
+ MIPS_REG_F18,
+ MIPS_REG_F19,
+ MIPS_REG_F20,
+ MIPS_REG_F21,
+ MIPS_REG_F22,
+ MIPS_REG_F23,
+ MIPS_REG_F24,
+ MIPS_REG_F25,
+ MIPS_REG_F26,
+ MIPS_REG_F27,
+ MIPS_REG_F28,
+ MIPS_REG_F29,
+ MIPS_REG_F30,
+ MIPS_REG_F31,
+
+ MIPS_REG_FCC0,
+ MIPS_REG_FCC1,
+ MIPS_REG_FCC2,
+ MIPS_REG_FCC3,
+ MIPS_REG_FCC4,
+ MIPS_REG_FCC5,
+ MIPS_REG_FCC6,
+ MIPS_REG_FCC7,
+
+ // AFPR128
+ MIPS_REG_W0,
+ MIPS_REG_W1,
+ MIPS_REG_W2,
+ MIPS_REG_W3,
+ MIPS_REG_W4,
+ MIPS_REG_W5,
+ MIPS_REG_W6,
+ MIPS_REG_W7,
+ MIPS_REG_W8,
+ MIPS_REG_W9,
+ MIPS_REG_W10,
+ MIPS_REG_W11,
+ MIPS_REG_W12,
+ MIPS_REG_W13,
+ MIPS_REG_W14,
+ MIPS_REG_W15,
+ MIPS_REG_W16,
+ MIPS_REG_W17,
+ MIPS_REG_W18,
+ MIPS_REG_W19,
+ MIPS_REG_W20,
+ MIPS_REG_W21,
+ MIPS_REG_W22,
+ MIPS_REG_W23,
+ MIPS_REG_W24,
+ MIPS_REG_W25,
+ MIPS_REG_W26,
+ MIPS_REG_W27,
+ MIPS_REG_W28,
+ MIPS_REG_W29,
+ MIPS_REG_W30,
+ MIPS_REG_W31,
+
+ MIPS_REG_HI,
+ MIPS_REG_LO,
+
+ MIPS_REG_P0,
+ MIPS_REG_P1,
+ MIPS_REG_P2,
+
+ MIPS_REG_MPL0,
+ MIPS_REG_MPL1,
+ MIPS_REG_MPL2,
+
+ MIPS_REG_ENDING, // <-- mark the end of the list or registers
+
+ // alias registers
+ MIPS_REG_ZERO = MIPS_REG_0,
+ MIPS_REG_AT = MIPS_REG_1,
+ MIPS_REG_V0 = MIPS_REG_2,
+ MIPS_REG_V1 = MIPS_REG_3,
+ MIPS_REG_A0 = MIPS_REG_4,
+ MIPS_REG_A1 = MIPS_REG_5,
+ MIPS_REG_A2 = MIPS_REG_6,
+ MIPS_REG_A3 = MIPS_REG_7,
+ MIPS_REG_T0 = MIPS_REG_8,
+ MIPS_REG_T1 = MIPS_REG_9,
+ MIPS_REG_T2 = MIPS_REG_10,
+ MIPS_REG_T3 = MIPS_REG_11,
+ MIPS_REG_T4 = MIPS_REG_12,
+ MIPS_REG_T5 = MIPS_REG_13,
+ MIPS_REG_T6 = MIPS_REG_14,
+ MIPS_REG_T7 = MIPS_REG_15,
+ MIPS_REG_S0 = MIPS_REG_16,
+ MIPS_REG_S1 = MIPS_REG_17,
+ MIPS_REG_S2 = MIPS_REG_18,
+ MIPS_REG_S3 = MIPS_REG_19,
+ MIPS_REG_S4 = MIPS_REG_20,
+ MIPS_REG_S5 = MIPS_REG_21,
+ MIPS_REG_S6 = MIPS_REG_22,
+ MIPS_REG_S7 = MIPS_REG_23,
+ MIPS_REG_T8 = MIPS_REG_24,
+ MIPS_REG_T9 = MIPS_REG_25,
+ MIPS_REG_K0 = MIPS_REG_26,
+ MIPS_REG_K1 = MIPS_REG_27,
+ MIPS_REG_GP = MIPS_REG_28,
+ MIPS_REG_SP = MIPS_REG_29,
+ MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,
+ MIPS_REG_RA = MIPS_REG_31,
+
+ MIPS_REG_HI0 = MIPS_REG_AC0,
+ MIPS_REG_HI1 = MIPS_REG_AC1,
+ MIPS_REG_HI2 = MIPS_REG_AC2,
+ MIPS_REG_HI3 = MIPS_REG_AC3,
+
+ MIPS_REG_LO0 = MIPS_REG_HI0,
+ MIPS_REG_LO1 = MIPS_REG_HI1,
+ MIPS_REG_LO2 = MIPS_REG_HI2,
+ MIPS_REG_LO3 = MIPS_REG_HI3,
+} mips_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with MIPS_OP_MEM operand type above
+typedef struct mips_op_mem {
+ mips_reg base; ///< base register
+ int64_t disp; ///< displacement/offset value
+} mips_op_mem;
+
+/// Instruction operand
+typedef struct cs_mips_op {
+ mips_op_type type; ///< operand type
+ union {
+ mips_reg reg; ///< register value for REG operand
+ int64_t imm; ///< immediate value for IMM operand
+ mips_op_mem mem; ///< base/index/scale/disp value for MEM operand
+ };
+} cs_mips_op;
+
+/// Instruction structure
+typedef struct cs_mips {
+ /// Number of operands of this instruction,
+ /// or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_mips_op operands[10]; ///< operands for this instruction.
+} cs_mips;
+
+/// MIPS instruction
+typedef enum mips_insn {
+ MIPS_INS_INVALID = 0,
+
+ MIPS_INS_ABSQ_S,
+ MIPS_INS_ADD,
+ MIPS_INS_ADDIUPC,
+ MIPS_INS_ADDIUR1SP,
+ MIPS_INS_ADDIUR2,
+ MIPS_INS_ADDIUS5,
+ MIPS_INS_ADDIUSP,
+ MIPS_INS_ADDQH,
+ MIPS_INS_ADDQH_R,
+ MIPS_INS_ADDQ,
+ MIPS_INS_ADDQ_S,
+ MIPS_INS_ADDSC,
+ MIPS_INS_ADDS_A,
+ MIPS_INS_ADDS_S,
+ MIPS_INS_ADDS_U,
+ MIPS_INS_ADDU16,
+ MIPS_INS_ADDUH,
+ MIPS_INS_ADDUH_R,
+ MIPS_INS_ADDU,
+ MIPS_INS_ADDU_S,
+ MIPS_INS_ADDVI,
+ MIPS_INS_ADDV,
+ MIPS_INS_ADDWC,
+ MIPS_INS_ADD_A,
+ MIPS_INS_ADDI,
+ MIPS_INS_ADDIU,
+ MIPS_INS_ALIGN,
+ MIPS_INS_ALUIPC,
+ MIPS_INS_AND,
+ MIPS_INS_AND16,
+ MIPS_INS_ANDI16,
+ MIPS_INS_ANDI,
+ MIPS_INS_APPEND,
+ MIPS_INS_ASUB_S,
+ MIPS_INS_ASUB_U,
+ MIPS_INS_AUI,
+ MIPS_INS_AUIPC,
+ MIPS_INS_AVER_S,
+ MIPS_INS_AVER_U,
+ MIPS_INS_AVE_S,
+ MIPS_INS_AVE_U,
+ MIPS_INS_B16,
+ MIPS_INS_BADDU,
+ MIPS_INS_BAL,
+ MIPS_INS_BALC,
+ MIPS_INS_BALIGN,
+ MIPS_INS_BBIT0,
+ MIPS_INS_BBIT032,
+ MIPS_INS_BBIT1,
+ MIPS_INS_BBIT132,
+ MIPS_INS_BC,
+ MIPS_INS_BC0F,
+ MIPS_INS_BC0FL,
+ MIPS_INS_BC0T,
+ MIPS_INS_BC0TL,
+ MIPS_INS_BC1EQZ,
+ MIPS_INS_BC1F,
+ MIPS_INS_BC1FL,
+ MIPS_INS_BC1NEZ,
+ MIPS_INS_BC1T,
+ MIPS_INS_BC1TL,
+ MIPS_INS_BC2EQZ,
+ MIPS_INS_BC2F,
+ MIPS_INS_BC2FL,
+ MIPS_INS_BC2NEZ,
+ MIPS_INS_BC2T,
+ MIPS_INS_BC2TL,
+ MIPS_INS_BC3F,
+ MIPS_INS_BC3FL,
+ MIPS_INS_BC3T,
+ MIPS_INS_BC3TL,
+ MIPS_INS_BCLRI,
+ MIPS_INS_BCLR,
+ MIPS_INS_BEQ,
+ MIPS_INS_BEQC,
+ MIPS_INS_BEQL,
+ MIPS_INS_BEQZ16,
+ MIPS_INS_BEQZALC,
+ MIPS_INS_BEQZC,
+ MIPS_INS_BGEC,
+ MIPS_INS_BGEUC,
+ MIPS_INS_BGEZ,
+ MIPS_INS_BGEZAL,
+ MIPS_INS_BGEZALC,
+ MIPS_INS_BGEZALL,
+ MIPS_INS_BGEZALS,
+ MIPS_INS_BGEZC,
+ MIPS_INS_BGEZL,
+ MIPS_INS_BGTZ,
+ MIPS_INS_BGTZALC,
+ MIPS_INS_BGTZC,
+ MIPS_INS_BGTZL,
+ MIPS_INS_BINSLI,
+ MIPS_INS_BINSL,
+ MIPS_INS_BINSRI,
+ MIPS_INS_BINSR,
+ MIPS_INS_BITREV,
+ MIPS_INS_BITSWAP,
+ MIPS_INS_BLEZ,
+ MIPS_INS_BLEZALC,
+ MIPS_INS_BLEZC,
+ MIPS_INS_BLEZL,
+ MIPS_INS_BLTC,
+ MIPS_INS_BLTUC,
+ MIPS_INS_BLTZ,
+ MIPS_INS_BLTZAL,
+ MIPS_INS_BLTZALC,
+ MIPS_INS_BLTZALL,
+ MIPS_INS_BLTZALS,
+ MIPS_INS_BLTZC,
+ MIPS_INS_BLTZL,
+ MIPS_INS_BMNZI,
+ MIPS_INS_BMNZ,
+ MIPS_INS_BMZI,
+ MIPS_INS_BMZ,
+ MIPS_INS_BNE,
+ MIPS_INS_BNEC,
+ MIPS_INS_BNEGI,
+ MIPS_INS_BNEG,
+ MIPS_INS_BNEL,
+ MIPS_INS_BNEZ16,
+ MIPS_INS_BNEZALC,
+ MIPS_INS_BNEZC,
+ MIPS_INS_BNVC,
+ MIPS_INS_BNZ,
+ MIPS_INS_BOVC,
+ MIPS_INS_BPOSGE32,
+ MIPS_INS_BREAK,
+ MIPS_INS_BREAK16,
+ MIPS_INS_BSELI,
+ MIPS_INS_BSEL,
+ MIPS_INS_BSETI,
+ MIPS_INS_BSET,
+ MIPS_INS_BZ,
+ MIPS_INS_BEQZ,
+ MIPS_INS_B,
+ MIPS_INS_BNEZ,
+ MIPS_INS_BTEQZ,
+ MIPS_INS_BTNEZ,
+ MIPS_INS_CACHE,
+ MIPS_INS_CEIL,
+ MIPS_INS_CEQI,
+ MIPS_INS_CEQ,
+ MIPS_INS_CFC1,
+ MIPS_INS_CFCMSA,
+ MIPS_INS_CINS,
+ MIPS_INS_CINS32,
+ MIPS_INS_CLASS,
+ MIPS_INS_CLEI_S,
+ MIPS_INS_CLEI_U,
+ MIPS_INS_CLE_S,
+ MIPS_INS_CLE_U,
+ MIPS_INS_CLO,
+ MIPS_INS_CLTI_S,
+ MIPS_INS_CLTI_U,
+ MIPS_INS_CLT_S,
+ MIPS_INS_CLT_U,
+ MIPS_INS_CLZ,
+ MIPS_INS_CMPGDU,
+ MIPS_INS_CMPGU,
+ MIPS_INS_CMPU,
+ MIPS_INS_CMP,
+ MIPS_INS_COPY_S,
+ MIPS_INS_COPY_U,
+ MIPS_INS_CTC1,
+ MIPS_INS_CTCMSA,
+ MIPS_INS_CVT,
+ MIPS_INS_C,
+ MIPS_INS_CMPI,
+ MIPS_INS_DADD,
+ MIPS_INS_DADDI,
+ MIPS_INS_DADDIU,
+ MIPS_INS_DADDU,
+ MIPS_INS_DAHI,
+ MIPS_INS_DALIGN,
+ MIPS_INS_DATI,
+ MIPS_INS_DAUI,
+ MIPS_INS_DBITSWAP,
+ MIPS_INS_DCLO,
+ MIPS_INS_DCLZ,
+ MIPS_INS_DDIV,
+ MIPS_INS_DDIVU,
+ MIPS_INS_DERET,
+ MIPS_INS_DEXT,
+ MIPS_INS_DEXTM,
+ MIPS_INS_DEXTU,
+ MIPS_INS_DI,
+ MIPS_INS_DINS,
+ MIPS_INS_DINSM,
+ MIPS_INS_DINSU,
+ MIPS_INS_DIV,
+ MIPS_INS_DIVU,
+ MIPS_INS_DIV_S,
+ MIPS_INS_DIV_U,
+ MIPS_INS_DLSA,
+ MIPS_INS_DMFC0,
+ MIPS_INS_DMFC1,
+ MIPS_INS_DMFC2,
+ MIPS_INS_DMOD,
+ MIPS_INS_DMODU,
+ MIPS_INS_DMTC0,
+ MIPS_INS_DMTC1,
+ MIPS_INS_DMTC2,
+ MIPS_INS_DMUH,
+ MIPS_INS_DMUHU,
+ MIPS_INS_DMUL,
+ MIPS_INS_DMULT,
+ MIPS_INS_DMULTU,
+ MIPS_INS_DMULU,
+ MIPS_INS_DOTP_S,
+ MIPS_INS_DOTP_U,
+ MIPS_INS_DPADD_S,
+ MIPS_INS_DPADD_U,
+ MIPS_INS_DPAQX_SA,
+ MIPS_INS_DPAQX_S,
+ MIPS_INS_DPAQ_SA,
+ MIPS_INS_DPAQ_S,
+ MIPS_INS_DPAU,
+ MIPS_INS_DPAX,
+ MIPS_INS_DPA,
+ MIPS_INS_DPOP,
+ MIPS_INS_DPSQX_SA,
+ MIPS_INS_DPSQX_S,
+ MIPS_INS_DPSQ_SA,
+ MIPS_INS_DPSQ_S,
+ MIPS_INS_DPSUB_S,
+ MIPS_INS_DPSUB_U,
+ MIPS_INS_DPSU,
+ MIPS_INS_DPSX,
+ MIPS_INS_DPS,
+ MIPS_INS_DROTR,
+ MIPS_INS_DROTR32,
+ MIPS_INS_DROTRV,
+ MIPS_INS_DSBH,
+ MIPS_INS_DSHD,
+ MIPS_INS_DSLL,
+ MIPS_INS_DSLL32,
+ MIPS_INS_DSLLV,
+ MIPS_INS_DSRA,
+ MIPS_INS_DSRA32,
+ MIPS_INS_DSRAV,
+ MIPS_INS_DSRL,
+ MIPS_INS_DSRL32,
+ MIPS_INS_DSRLV,
+ MIPS_INS_DSUB,
+ MIPS_INS_DSUBU,
+ MIPS_INS_EHB,
+ MIPS_INS_EI,
+ MIPS_INS_ERET,
+ MIPS_INS_EXT,
+ MIPS_INS_EXTP,
+ MIPS_INS_EXTPDP,
+ MIPS_INS_EXTPDPV,
+ MIPS_INS_EXTPV,
+ MIPS_INS_EXTRV_RS,
+ MIPS_INS_EXTRV_R,
+ MIPS_INS_EXTRV_S,
+ MIPS_INS_EXTRV,
+ MIPS_INS_EXTR_RS,
+ MIPS_INS_EXTR_R,
+ MIPS_INS_EXTR_S,
+ MIPS_INS_EXTR,
+ MIPS_INS_EXTS,
+ MIPS_INS_EXTS32,
+ MIPS_INS_ABS,
+ MIPS_INS_FADD,
+ MIPS_INS_FCAF,
+ MIPS_INS_FCEQ,
+ MIPS_INS_FCLASS,
+ MIPS_INS_FCLE,
+ MIPS_INS_FCLT,
+ MIPS_INS_FCNE,
+ MIPS_INS_FCOR,
+ MIPS_INS_FCUEQ,
+ MIPS_INS_FCULE,
+ MIPS_INS_FCULT,
+ MIPS_INS_FCUNE,
+ MIPS_INS_FCUN,
+ MIPS_INS_FDIV,
+ MIPS_INS_FEXDO,
+ MIPS_INS_FEXP2,
+ MIPS_INS_FEXUPL,
+ MIPS_INS_FEXUPR,
+ MIPS_INS_FFINT_S,
+ MIPS_INS_FFINT_U,
+ MIPS_INS_FFQL,
+ MIPS_INS_FFQR,
+ MIPS_INS_FILL,
+ MIPS_INS_FLOG2,
+ MIPS_INS_FLOOR,
+ MIPS_INS_FMADD,
+ MIPS_INS_FMAX_A,
+ MIPS_INS_FMAX,
+ MIPS_INS_FMIN_A,
+ MIPS_INS_FMIN,
+ MIPS_INS_MOV,
+ MIPS_INS_FMSUB,
+ MIPS_INS_FMUL,
+ MIPS_INS_MUL,
+ MIPS_INS_NEG,
+ MIPS_INS_FRCP,
+ MIPS_INS_FRINT,
+ MIPS_INS_FRSQRT,
+ MIPS_INS_FSAF,
+ MIPS_INS_FSEQ,
+ MIPS_INS_FSLE,
+ MIPS_INS_FSLT,
+ MIPS_INS_FSNE,
+ MIPS_INS_FSOR,
+ MIPS_INS_FSQRT,
+ MIPS_INS_SQRT,
+ MIPS_INS_FSUB,
+ MIPS_INS_SUB,
+ MIPS_INS_FSUEQ,
+ MIPS_INS_FSULE,
+ MIPS_INS_FSULT,
+ MIPS_INS_FSUNE,
+ MIPS_INS_FSUN,
+ MIPS_INS_FTINT_S,
+ MIPS_INS_FTINT_U,
+ MIPS_INS_FTQ,
+ MIPS_INS_FTRUNC_S,
+ MIPS_INS_FTRUNC_U,
+ MIPS_INS_HADD_S,
+ MIPS_INS_HADD_U,
+ MIPS_INS_HSUB_S,
+ MIPS_INS_HSUB_U,
+ MIPS_INS_ILVEV,
+ MIPS_INS_ILVL,
+ MIPS_INS_ILVOD,
+ MIPS_INS_ILVR,
+ MIPS_INS_INS,
+ MIPS_INS_INSERT,
+ MIPS_INS_INSV,
+ MIPS_INS_INSVE,
+ MIPS_INS_J,
+ MIPS_INS_JAL,
+ MIPS_INS_JALR,
+ MIPS_INS_JALRS16,
+ MIPS_INS_JALRS,
+ MIPS_INS_JALS,
+ MIPS_INS_JALX,
+ MIPS_INS_JIALC,
+ MIPS_INS_JIC,
+ MIPS_INS_JR,
+ MIPS_INS_JR16,
+ MIPS_INS_JRADDIUSP,
+ MIPS_INS_JRC,
+ MIPS_INS_JALRC,
+ MIPS_INS_LB,
+ MIPS_INS_LBU16,
+ MIPS_INS_LBUX,
+ MIPS_INS_LBU,
+ MIPS_INS_LD,
+ MIPS_INS_LDC1,
+ MIPS_INS_LDC2,
+ MIPS_INS_LDC3,
+ MIPS_INS_LDI,
+ MIPS_INS_LDL,
+ MIPS_INS_LDPC,
+ MIPS_INS_LDR,
+ MIPS_INS_LDXC1,
+ MIPS_INS_LH,
+ MIPS_INS_LHU16,
+ MIPS_INS_LHX,
+ MIPS_INS_LHU,
+ MIPS_INS_LI16,
+ MIPS_INS_LL,
+ MIPS_INS_LLD,
+ MIPS_INS_LSA,
+ MIPS_INS_LUXC1,
+ MIPS_INS_LUI,
+ MIPS_INS_LW,
+ MIPS_INS_LW16,
+ MIPS_INS_LWC1,
+ MIPS_INS_LWC2,
+ MIPS_INS_LWC3,
+ MIPS_INS_LWL,
+ MIPS_INS_LWM16,
+ MIPS_INS_LWM32,
+ MIPS_INS_LWPC,
+ MIPS_INS_LWP,
+ MIPS_INS_LWR,
+ MIPS_INS_LWUPC,
+ MIPS_INS_LWU,
+ MIPS_INS_LWX,
+ MIPS_INS_LWXC1,
+ MIPS_INS_LWXS,
+ MIPS_INS_LI,
+ MIPS_INS_MADD,
+ MIPS_INS_MADDF,
+ MIPS_INS_MADDR_Q,
+ MIPS_INS_MADDU,
+ MIPS_INS_MADDV,
+ MIPS_INS_MADD_Q,
+ MIPS_INS_MAQ_SA,
+ MIPS_INS_MAQ_S,
+ MIPS_INS_MAXA,
+ MIPS_INS_MAXI_S,
+ MIPS_INS_MAXI_U,
+ MIPS_INS_MAX_A,
+ MIPS_INS_MAX,
+ MIPS_INS_MAX_S,
+ MIPS_INS_MAX_U,
+ MIPS_INS_MFC0,
+ MIPS_INS_MFC1,
+ MIPS_INS_MFC2,
+ MIPS_INS_MFHC1,
+ MIPS_INS_MFHI,
+ MIPS_INS_MFLO,
+ MIPS_INS_MINA,
+ MIPS_INS_MINI_S,
+ MIPS_INS_MINI_U,
+ MIPS_INS_MIN_A,
+ MIPS_INS_MIN,
+ MIPS_INS_MIN_S,
+ MIPS_INS_MIN_U,
+ MIPS_INS_MOD,
+ MIPS_INS_MODSUB,
+ MIPS_INS_MODU,
+ MIPS_INS_MOD_S,
+ MIPS_INS_MOD_U,
+ MIPS_INS_MOVE,
+ MIPS_INS_MOVEP,
+ MIPS_INS_MOVF,
+ MIPS_INS_MOVN,
+ MIPS_INS_MOVT,
+ MIPS_INS_MOVZ,
+ MIPS_INS_MSUB,
+ MIPS_INS_MSUBF,
+ MIPS_INS_MSUBR_Q,
+ MIPS_INS_MSUBU,
+ MIPS_INS_MSUBV,
+ MIPS_INS_MSUB_Q,
+ MIPS_INS_MTC0,
+ MIPS_INS_MTC1,
+ MIPS_INS_MTC2,
+ MIPS_INS_MTHC1,
+ MIPS_INS_MTHI,
+ MIPS_INS_MTHLIP,
+ MIPS_INS_MTLO,
+ MIPS_INS_MTM0,
+ MIPS_INS_MTM1,
+ MIPS_INS_MTM2,
+ MIPS_INS_MTP0,
+ MIPS_INS_MTP1,
+ MIPS_INS_MTP2,
+ MIPS_INS_MUH,
+ MIPS_INS_MUHU,
+ MIPS_INS_MULEQ_S,
+ MIPS_INS_MULEU_S,
+ MIPS_INS_MULQ_RS,
+ MIPS_INS_MULQ_S,
+ MIPS_INS_MULR_Q,
+ MIPS_INS_MULSAQ_S,
+ MIPS_INS_MULSA,
+ MIPS_INS_MULT,
+ MIPS_INS_MULTU,
+ MIPS_INS_MULU,
+ MIPS_INS_MULV,
+ MIPS_INS_MUL_Q,
+ MIPS_INS_MUL_S,
+ MIPS_INS_NLOC,
+ MIPS_INS_NLZC,
+ MIPS_INS_NMADD,
+ MIPS_INS_NMSUB,
+ MIPS_INS_NOR,
+ MIPS_INS_NORI,
+ MIPS_INS_NOT16,
+ MIPS_INS_NOT,
+ MIPS_INS_OR,
+ MIPS_INS_OR16,
+ MIPS_INS_ORI,
+ MIPS_INS_PACKRL,
+ MIPS_INS_PAUSE,
+ MIPS_INS_PCKEV,
+ MIPS_INS_PCKOD,
+ MIPS_INS_PCNT,
+ MIPS_INS_PICK,
+ MIPS_INS_POP,
+ MIPS_INS_PRECEQU,
+ MIPS_INS_PRECEQ,
+ MIPS_INS_PRECEU,
+ MIPS_INS_PRECRQU_S,
+ MIPS_INS_PRECRQ,
+ MIPS_INS_PRECRQ_RS,
+ MIPS_INS_PRECR,
+ MIPS_INS_PRECR_SRA,
+ MIPS_INS_PRECR_SRA_R,
+ MIPS_INS_PREF,
+ MIPS_INS_PREPEND,
+ MIPS_INS_RADDU,
+ MIPS_INS_RDDSP,
+ MIPS_INS_RDHWR,
+ MIPS_INS_REPLV,
+ MIPS_INS_REPL,
+ MIPS_INS_RINT,
+ MIPS_INS_ROTR,
+ MIPS_INS_ROTRV,
+ MIPS_INS_ROUND,
+ MIPS_INS_SAT_S,
+ MIPS_INS_SAT_U,
+ MIPS_INS_SB,
+ MIPS_INS_SB16,
+ MIPS_INS_SC,
+ MIPS_INS_SCD,
+ MIPS_INS_SD,
+ MIPS_INS_SDBBP,
+ MIPS_INS_SDBBP16,
+ MIPS_INS_SDC1,
+ MIPS_INS_SDC2,
+ MIPS_INS_SDC3,
+ MIPS_INS_SDL,
+ MIPS_INS_SDR,
+ MIPS_INS_SDXC1,
+ MIPS_INS_SEB,
+ MIPS_INS_SEH,
+ MIPS_INS_SELEQZ,
+ MIPS_INS_SELNEZ,
+ MIPS_INS_SEL,
+ MIPS_INS_SEQ,
+ MIPS_INS_SEQI,
+ MIPS_INS_SH,
+ MIPS_INS_SH16,
+ MIPS_INS_SHF,
+ MIPS_INS_SHILO,
+ MIPS_INS_SHILOV,
+ MIPS_INS_SHLLV,
+ MIPS_INS_SHLLV_S,
+ MIPS_INS_SHLL,
+ MIPS_INS_SHLL_S,
+ MIPS_INS_SHRAV,
+ MIPS_INS_SHRAV_R,
+ MIPS_INS_SHRA,
+ MIPS_INS_SHRA_R,
+ MIPS_INS_SHRLV,
+ MIPS_INS_SHRL,
+ MIPS_INS_SLDI,
+ MIPS_INS_SLD,
+ MIPS_INS_SLL,
+ MIPS_INS_SLL16,
+ MIPS_INS_SLLI,
+ MIPS_INS_SLLV,
+ MIPS_INS_SLT,
+ MIPS_INS_SLTI,
+ MIPS_INS_SLTIU,
+ MIPS_INS_SLTU,
+ MIPS_INS_SNE,
+ MIPS_INS_SNEI,
+ MIPS_INS_SPLATI,
+ MIPS_INS_SPLAT,
+ MIPS_INS_SRA,
+ MIPS_INS_SRAI,
+ MIPS_INS_SRARI,
+ MIPS_INS_SRAR,
+ MIPS_INS_SRAV,
+ MIPS_INS_SRL,
+ MIPS_INS_SRL16,
+ MIPS_INS_SRLI,
+ MIPS_INS_SRLRI,
+ MIPS_INS_SRLR,
+ MIPS_INS_SRLV,
+ MIPS_INS_SSNOP,
+ MIPS_INS_ST,
+ MIPS_INS_SUBQH,
+ MIPS_INS_SUBQH_R,
+ MIPS_INS_SUBQ,
+ MIPS_INS_SUBQ_S,
+ MIPS_INS_SUBSUS_U,
+ MIPS_INS_SUBSUU_S,
+ MIPS_INS_SUBS_S,
+ MIPS_INS_SUBS_U,
+ MIPS_INS_SUBU16,
+ MIPS_INS_SUBUH,
+ MIPS_INS_SUBUH_R,
+ MIPS_INS_SUBU,
+ MIPS_INS_SUBU_S,
+ MIPS_INS_SUBVI,
+ MIPS_INS_SUBV,
+ MIPS_INS_SUXC1,
+ MIPS_INS_SW,
+ MIPS_INS_SW16,
+ MIPS_INS_SWC1,
+ MIPS_INS_SWC2,
+ MIPS_INS_SWC3,
+ MIPS_INS_SWL,
+ MIPS_INS_SWM16,
+ MIPS_INS_SWM32,
+ MIPS_INS_SWP,
+ MIPS_INS_SWR,
+ MIPS_INS_SWXC1,
+ MIPS_INS_SYNC,
+ MIPS_INS_SYNCI,
+ MIPS_INS_SYSCALL,
+ MIPS_INS_TEQ,
+ MIPS_INS_TEQI,
+ MIPS_INS_TGE,
+ MIPS_INS_TGEI,
+ MIPS_INS_TGEIU,
+ MIPS_INS_TGEU,
+ MIPS_INS_TLBP,
+ MIPS_INS_TLBR,
+ MIPS_INS_TLBWI,
+ MIPS_INS_TLBWR,
+ MIPS_INS_TLT,
+ MIPS_INS_TLTI,
+ MIPS_INS_TLTIU,
+ MIPS_INS_TLTU,
+ MIPS_INS_TNE,
+ MIPS_INS_TNEI,
+ MIPS_INS_TRUNC,
+ MIPS_INS_V3MULU,
+ MIPS_INS_VMM0,
+ MIPS_INS_VMULU,
+ MIPS_INS_VSHF,
+ MIPS_INS_WAIT,
+ MIPS_INS_WRDSP,
+ MIPS_INS_WSBH,
+ MIPS_INS_XOR,
+ MIPS_INS_XOR16,
+ MIPS_INS_XORI,
+
+ //> some alias instructions
+ MIPS_INS_NOP,
+ MIPS_INS_NEGU,
+
+ //> special instructions
+ MIPS_INS_JALR_HB, // jump and link with Hazard Barrier
+ MIPS_INS_JR_HB, // jump register with Hazard Barrier
+
+ MIPS_INS_ENDING,
+} mips_insn;
+
+/// Group of MIPS instructions
+typedef enum mips_insn_group {
+ MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ MIPS_GRP_JUMP, ///< = CS_GRP_JUMP
+ // all call instructions
+ MIPS_GRP_CALL, ///< = CS_GRP_CALL
+ // all return instructions
+ MIPS_GRP_RET, ///< = CS_GRP_RET
+ // all interrupt instructions (int+syscall)
+ MIPS_GRP_INT, ///< = CS_GRP_INT
+ // all interrupt return instructions
+ MIPS_GRP_IRET, ///< = CS_GRP_IRET
+ // all privileged instructions
+ MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE
+ // all relative branching instructions
+ MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+ // Architecture-specific groups
+ MIPS_GRP_BITCOUNT = 128,
+ MIPS_GRP_DSP,
+ MIPS_GRP_DSPR2,
+ MIPS_GRP_FPIDX,
+ MIPS_GRP_MSA,
+ MIPS_GRP_MIPS32R2,
+ MIPS_GRP_MIPS64,
+ MIPS_GRP_MIPS64R2,
+ MIPS_GRP_SEINREG,
+ MIPS_GRP_STDENC,
+ MIPS_GRP_SWAP,
+ MIPS_GRP_MICROMIPS,
+ MIPS_GRP_MIPS16MODE,
+ MIPS_GRP_FP64BIT,
+ MIPS_GRP_NONANSFPMATH,
+ MIPS_GRP_NOTFP64BIT,
+ MIPS_GRP_NOTINMICROMIPS,
+ MIPS_GRP_NOTNACL,
+ MIPS_GRP_NOTMIPS32R6,
+ MIPS_GRP_NOTMIPS64R6,
+ MIPS_GRP_CNMIPS,
+ MIPS_GRP_MIPS32,
+ MIPS_GRP_MIPS32R6,
+ MIPS_GRP_MIPS64R6,
+ MIPS_GRP_MIPS2,
+ MIPS_GRP_MIPS3,
+ MIPS_GRP_MIPS3_32,
+ MIPS_GRP_MIPS3_32R2,
+ MIPS_GRP_MIPS4_32,
+ MIPS_GRP_MIPS4_32R2,
+ MIPS_GRP_MIPS5_32R2,
+ MIPS_GRP_GP32BIT,
+ MIPS_GRP_GP64BIT,
+
+ MIPS_GRP_ENDING,
+} mips_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/platform.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/platform.h
new file mode 100644
index 00000000..a5a4bd23
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/platform.h
@@ -0,0 +1,122 @@
+/* Capstone Disassembly Engine */
+/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
+
+#ifndef CAPSTONE_PLATFORM_H
+#define CAPSTONE_PLATFORM_H
+
+
+// handle C99 issue (for pre-2013 VisualStudio)
+#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+// MSVC
+
+// stdbool.h
+#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)
+// this system does not have stdbool.h
+#ifndef __cplusplus
+typedef unsigned char bool;
+#define false 0
+#define true 1
+#endif // __cplusplus
+
+#else
+// VisualStudio 2013+ -> C99 is supported
+#include
+#endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE)
+
+#else
+// not MSVC -> C99 is supported
+#include
+#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+
+
+// handle inttypes.h / stdint.h compatibility
+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+#include "windowsce/stdint.h"
+#endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+
+#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
+// this system does not have inttypes.h
+
+#if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
+// this system does not have stdint.h
+typedef signed char int8_t;
+typedef signed short int16_t;
+typedef signed int int32_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef signed long long int64_t;
+typedef unsigned long long uint64_t;
+#endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
+
+#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
+#define INT8_MIN (-127i8 - 1)
+#define INT16_MIN (-32767i16 - 1)
+#define INT32_MIN (-2147483647i32 - 1)
+#define INT64_MIN (-9223372036854775807i64 - 1)
+#define INT8_MAX 127i8
+#define INT16_MAX 32767i16
+#define INT32_MAX 2147483647i32
+#define INT64_MAX 9223372036854775807i64
+#define UINT8_MAX 0xffui8
+#define UINT16_MAX 0xffffui16
+#define UINT32_MAX 0xffffffffui32
+#define UINT64_MAX 0xffffffffffffffffui64
+#endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
+
+#ifdef CAPSTONE_HAS_OSXKERNEL
+// this system has stdint.h
+#include
+#endif
+
+#define __PRI_8_LENGTH_MODIFIER__ "hh"
+#define __PRI_64_LENGTH_MODIFIER__ "ll"
+
+#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
+#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
+#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
+#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
+#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
+#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
+
+#define PRId16 "hd"
+#define PRIi16 "hi"
+#define PRIo16 "ho"
+#define PRIu16 "hu"
+#define PRIx16 "hx"
+#define PRIX16 "hX"
+
+#if defined(_MSC_VER) && _MSC_VER <= 1700
+#define PRId32 "ld"
+#define PRIi32 "li"
+#define PRIo32 "lo"
+#define PRIu32 "lu"
+#define PRIx32 "lx"
+#define PRIX32 "lX"
+#else // OSX
+#define PRId32 "d"
+#define PRIi32 "i"
+#define PRIo32 "o"
+#define PRIu32 "u"
+#define PRIx32 "x"
+#define PRIX32 "X"
+#endif // defined(_MSC_VER) && _MSC_VER <= 1700
+
+#if defined(_MSC_VER) && _MSC_VER <= 1700
+// redefine functions from inttypes.h used in cstool
+#define strtoull _strtoui64
+#endif
+
+#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
+#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
+#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
+#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
+#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
+#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
+
+#else
+// this system has inttypes.h by default
+#include
+#endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/ppc.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/ppc.h
new file mode 100644
index 00000000..97ce15b7
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/ppc.h
@@ -0,0 +1,1463 @@
+#ifndef CAPSTONE_PPC_H
+#define CAPSTONE_PPC_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2013-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// PPC branch codes for some branch instructions
+typedef enum ppc_bc {
+ PPC_BC_INVALID = 0,
+ PPC_BC_LT = (0 << 5) | 12,
+ PPC_BC_LE = (1 << 5) | 4,
+ PPC_BC_EQ = (2 << 5) | 12,
+ PPC_BC_GE = (0 << 5) | 4,
+ PPC_BC_GT = (1 << 5) | 12,
+ PPC_BC_NE = (2 << 5) | 4,
+ PPC_BC_UN = (3 << 5) | 12,
+ PPC_BC_NU = (3 << 5) | 4,
+
+ // extra conditions
+ PPC_BC_SO = (4 << 5) | 12, ///< summary overflow
+ PPC_BC_NS = (4 << 5) | 4, ///< not summary overflow
+} ppc_bc;
+
+/// PPC branch hint for some branch instructions
+typedef enum ppc_bh {
+ PPC_BH_INVALID = 0, ///< no hint
+ PPC_BH_PLUS, ///< PLUS hint
+ PPC_BH_MINUS, ///< MINUS hint
+} ppc_bh;
+
+/// Operand type for instruction's operands
+typedef enum ppc_op_type {
+ PPC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ PPC_OP_REG, ///< = CS_OP_REG (Register operand).
+ PPC_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ PPC_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+ PPC_OP_CRX = 64, ///< Condition Register field
+} ppc_op_type;
+
+/// PPC registers
+typedef enum ppc_reg {
+ PPC_REG_INVALID = 0,
+
+ PPC_REG_CARRY,
+ PPC_REG_CR0,
+ PPC_REG_CR1,
+ PPC_REG_CR2,
+ PPC_REG_CR3,
+ PPC_REG_CR4,
+ PPC_REG_CR5,
+ PPC_REG_CR6,
+ PPC_REG_CR7,
+ PPC_REG_CTR,
+ PPC_REG_F0,
+ PPC_REG_F1,
+ PPC_REG_F2,
+ PPC_REG_F3,
+ PPC_REG_F4,
+ PPC_REG_F5,
+ PPC_REG_F6,
+ PPC_REG_F7,
+ PPC_REG_F8,
+ PPC_REG_F9,
+ PPC_REG_F10,
+ PPC_REG_F11,
+ PPC_REG_F12,
+ PPC_REG_F13,
+ PPC_REG_F14,
+ PPC_REG_F15,
+ PPC_REG_F16,
+ PPC_REG_F17,
+ PPC_REG_F18,
+ PPC_REG_F19,
+ PPC_REG_F20,
+ PPC_REG_F21,
+ PPC_REG_F22,
+ PPC_REG_F23,
+ PPC_REG_F24,
+ PPC_REG_F25,
+ PPC_REG_F26,
+ PPC_REG_F27,
+ PPC_REG_F28,
+ PPC_REG_F29,
+ PPC_REG_F30,
+ PPC_REG_F31,
+ PPC_REG_LR,
+ PPC_REG_R0,
+ PPC_REG_R1,
+ PPC_REG_R2,
+ PPC_REG_R3,
+ PPC_REG_R4,
+ PPC_REG_R5,
+ PPC_REG_R6,
+ PPC_REG_R7,
+ PPC_REG_R8,
+ PPC_REG_R9,
+ PPC_REG_R10,
+ PPC_REG_R11,
+ PPC_REG_R12,
+ PPC_REG_R13,
+ PPC_REG_R14,
+ PPC_REG_R15,
+ PPC_REG_R16,
+ PPC_REG_R17,
+ PPC_REG_R18,
+ PPC_REG_R19,
+ PPC_REG_R20,
+ PPC_REG_R21,
+ PPC_REG_R22,
+ PPC_REG_R23,
+ PPC_REG_R24,
+ PPC_REG_R25,
+ PPC_REG_R26,
+ PPC_REG_R27,
+ PPC_REG_R28,
+ PPC_REG_R29,
+ PPC_REG_R30,
+ PPC_REG_R31,
+ PPC_REG_V0,
+ PPC_REG_V1,
+ PPC_REG_V2,
+ PPC_REG_V3,
+ PPC_REG_V4,
+ PPC_REG_V5,
+ PPC_REG_V6,
+ PPC_REG_V7,
+ PPC_REG_V8,
+ PPC_REG_V9,
+ PPC_REG_V10,
+ PPC_REG_V11,
+ PPC_REG_V12,
+ PPC_REG_V13,
+ PPC_REG_V14,
+ PPC_REG_V15,
+ PPC_REG_V16,
+ PPC_REG_V17,
+ PPC_REG_V18,
+ PPC_REG_V19,
+ PPC_REG_V20,
+ PPC_REG_V21,
+ PPC_REG_V22,
+ PPC_REG_V23,
+ PPC_REG_V24,
+ PPC_REG_V25,
+ PPC_REG_V26,
+ PPC_REG_V27,
+ PPC_REG_V28,
+ PPC_REG_V29,
+ PPC_REG_V30,
+ PPC_REG_V31,
+ PPC_REG_VRSAVE,
+ PPC_REG_VS0,
+ PPC_REG_VS1,
+ PPC_REG_VS2,
+ PPC_REG_VS3,
+ PPC_REG_VS4,
+ PPC_REG_VS5,
+ PPC_REG_VS6,
+ PPC_REG_VS7,
+ PPC_REG_VS8,
+ PPC_REG_VS9,
+ PPC_REG_VS10,
+ PPC_REG_VS11,
+ PPC_REG_VS12,
+ PPC_REG_VS13,
+ PPC_REG_VS14,
+ PPC_REG_VS15,
+ PPC_REG_VS16,
+ PPC_REG_VS17,
+ PPC_REG_VS18,
+ PPC_REG_VS19,
+ PPC_REG_VS20,
+ PPC_REG_VS21,
+ PPC_REG_VS22,
+ PPC_REG_VS23,
+ PPC_REG_VS24,
+ PPC_REG_VS25,
+ PPC_REG_VS26,
+ PPC_REG_VS27,
+ PPC_REG_VS28,
+ PPC_REG_VS29,
+ PPC_REG_VS30,
+ PPC_REG_VS31,
+ PPC_REG_VS32,
+ PPC_REG_VS33,
+ PPC_REG_VS34,
+ PPC_REG_VS35,
+ PPC_REG_VS36,
+ PPC_REG_VS37,
+ PPC_REG_VS38,
+ PPC_REG_VS39,
+ PPC_REG_VS40,
+ PPC_REG_VS41,
+ PPC_REG_VS42,
+ PPC_REG_VS43,
+ PPC_REG_VS44,
+ PPC_REG_VS45,
+ PPC_REG_VS46,
+ PPC_REG_VS47,
+ PPC_REG_VS48,
+ PPC_REG_VS49,
+ PPC_REG_VS50,
+ PPC_REG_VS51,
+ PPC_REG_VS52,
+ PPC_REG_VS53,
+ PPC_REG_VS54,
+ PPC_REG_VS55,
+ PPC_REG_VS56,
+ PPC_REG_VS57,
+ PPC_REG_VS58,
+ PPC_REG_VS59,
+ PPC_REG_VS60,
+ PPC_REG_VS61,
+ PPC_REG_VS62,
+ PPC_REG_VS63,
+ PPC_REG_Q0,
+ PPC_REG_Q1,
+ PPC_REG_Q2,
+ PPC_REG_Q3,
+ PPC_REG_Q4,
+ PPC_REG_Q5,
+ PPC_REG_Q6,
+ PPC_REG_Q7,
+ PPC_REG_Q8,
+ PPC_REG_Q9,
+ PPC_REG_Q10,
+ PPC_REG_Q11,
+ PPC_REG_Q12,
+ PPC_REG_Q13,
+ PPC_REG_Q14,
+ PPC_REG_Q15,
+ PPC_REG_Q16,
+ PPC_REG_Q17,
+ PPC_REG_Q18,
+ PPC_REG_Q19,
+ PPC_REG_Q20,
+ PPC_REG_Q21,
+ PPC_REG_Q22,
+ PPC_REG_Q23,
+ PPC_REG_Q24,
+ PPC_REG_Q25,
+ PPC_REG_Q26,
+ PPC_REG_Q27,
+ PPC_REG_Q28,
+ PPC_REG_Q29,
+ PPC_REG_Q30,
+ PPC_REG_Q31,
+
+ // extra registers for PPCMapping.c
+ PPC_REG_RM,
+ PPC_REG_CTR8,
+ PPC_REG_LR8,
+ PPC_REG_CR1EQ,
+ PPC_REG_X2,
+
+ PPC_REG_ENDING, // <-- mark the end of the list of registers
+} ppc_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with PPC_OP_MEM operand type above
+typedef struct ppc_op_mem {
+ ppc_reg base; ///< base register
+ int32_t disp; ///< displacement/offset value
+} ppc_op_mem;
+
+typedef struct ppc_op_crx {
+ unsigned int scale;
+ ppc_reg reg;
+ ppc_bc cond;
+} ppc_op_crx;
+
+/// Instruction operand
+typedef struct cs_ppc_op {
+ ppc_op_type type; ///< operand type
+ union {
+ ppc_reg reg; ///< register value for REG operand
+ int64_t imm; ///< immediate value for IMM operand
+ ppc_op_mem mem; ///< base/disp value for MEM operand
+ ppc_op_crx crx; ///< operand with condition register
+ };
+} cs_ppc_op;
+
+/// Instruction structure
+typedef struct cs_ppc {
+ /// branch code for branch instructions
+ ppc_bc bc;
+
+ /// branch hint for branch instructions
+ ppc_bh bh;
+
+ /// if update_cr0 = True, then this 'dot' insn updates CR0
+ bool update_cr0;
+
+ /// Number of operands of this instruction,
+ /// or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_ppc_op operands[8]; ///< operands for this instruction.
+} cs_ppc;
+
+/// PPC instruction
+typedef enum ppc_insn {
+ PPC_INS_INVALID = 0,
+
+ PPC_INS_ADD,
+ PPC_INS_ADDC,
+ PPC_INS_ADDE,
+ PPC_INS_ADDI,
+ PPC_INS_ADDIC,
+ PPC_INS_ADDIS,
+ PPC_INS_ADDME,
+ PPC_INS_ADDZE,
+ PPC_INS_AND,
+ PPC_INS_ANDC,
+ PPC_INS_ANDIS,
+ PPC_INS_ANDI,
+ PPC_INS_ATTN,
+ PPC_INS_B,
+ PPC_INS_BA,
+ PPC_INS_BC,
+ PPC_INS_BCCTR,
+ PPC_INS_BCCTRL,
+ PPC_INS_BCL,
+ PPC_INS_BCLR,
+ PPC_INS_BCLRL,
+ PPC_INS_BCTR,
+ PPC_INS_BCTRL,
+ PPC_INS_BCT,
+ PPC_INS_BDNZ,
+ PPC_INS_BDNZA,
+ PPC_INS_BDNZL,
+ PPC_INS_BDNZLA,
+ PPC_INS_BDNZLR,
+ PPC_INS_BDNZLRL,
+ PPC_INS_BDZ,
+ PPC_INS_BDZA,
+ PPC_INS_BDZL,
+ PPC_INS_BDZLA,
+ PPC_INS_BDZLR,
+ PPC_INS_BDZLRL,
+ PPC_INS_BL,
+ PPC_INS_BLA,
+ PPC_INS_BLR,
+ PPC_INS_BLRL,
+ PPC_INS_BRINC,
+ PPC_INS_CMPB,
+ PPC_INS_CMPD,
+ PPC_INS_CMPDI,
+ PPC_INS_CMPLD,
+ PPC_INS_CMPLDI,
+ PPC_INS_CMPLW,
+ PPC_INS_CMPLWI,
+ PPC_INS_CMPW,
+ PPC_INS_CMPWI,
+ PPC_INS_CNTLZD,
+ PPC_INS_CNTLZW,
+ PPC_INS_CREQV,
+ PPC_INS_CRXOR,
+ PPC_INS_CRAND,
+ PPC_INS_CRANDC,
+ PPC_INS_CRNAND,
+ PPC_INS_CRNOR,
+ PPC_INS_CROR,
+ PPC_INS_CRORC,
+ PPC_INS_DCBA,
+ PPC_INS_DCBF,
+ PPC_INS_DCBI,
+ PPC_INS_DCBST,
+ PPC_INS_DCBT,
+ PPC_INS_DCBTST,
+ PPC_INS_DCBZ,
+ PPC_INS_DCBZL,
+ PPC_INS_DCCCI,
+ PPC_INS_DIVD,
+ PPC_INS_DIVDU,
+ PPC_INS_DIVW,
+ PPC_INS_DIVWU,
+ PPC_INS_DSS,
+ PPC_INS_DSSALL,
+ PPC_INS_DST,
+ PPC_INS_DSTST,
+ PPC_INS_DSTSTT,
+ PPC_INS_DSTT,
+ PPC_INS_EQV,
+ PPC_INS_EVABS,
+ PPC_INS_EVADDIW,
+ PPC_INS_EVADDSMIAAW,
+ PPC_INS_EVADDSSIAAW,
+ PPC_INS_EVADDUMIAAW,
+ PPC_INS_EVADDUSIAAW,
+ PPC_INS_EVADDW,
+ PPC_INS_EVAND,
+ PPC_INS_EVANDC,
+ PPC_INS_EVCMPEQ,
+ PPC_INS_EVCMPGTS,
+ PPC_INS_EVCMPGTU,
+ PPC_INS_EVCMPLTS,
+ PPC_INS_EVCMPLTU,
+ PPC_INS_EVCNTLSW,
+ PPC_INS_EVCNTLZW,
+ PPC_INS_EVDIVWS,
+ PPC_INS_EVDIVWU,
+ PPC_INS_EVEQV,
+ PPC_INS_EVEXTSB,
+ PPC_INS_EVEXTSH,
+ PPC_INS_EVLDD,
+ PPC_INS_EVLDDX,
+ PPC_INS_EVLDH,
+ PPC_INS_EVLDHX,
+ PPC_INS_EVLDW,
+ PPC_INS_EVLDWX,
+ PPC_INS_EVLHHESPLAT,
+ PPC_INS_EVLHHESPLATX,
+ PPC_INS_EVLHHOSSPLAT,
+ PPC_INS_EVLHHOSSPLATX,
+ PPC_INS_EVLHHOUSPLAT,
+ PPC_INS_EVLHHOUSPLATX,
+ PPC_INS_EVLWHE,
+ PPC_INS_EVLWHEX,
+ PPC_INS_EVLWHOS,
+ PPC_INS_EVLWHOSX,
+ PPC_INS_EVLWHOU,
+ PPC_INS_EVLWHOUX,
+ PPC_INS_EVLWHSPLAT,
+ PPC_INS_EVLWHSPLATX,
+ PPC_INS_EVLWWSPLAT,
+ PPC_INS_EVLWWSPLATX,
+ PPC_INS_EVMERGEHI,
+ PPC_INS_EVMERGEHILO,
+ PPC_INS_EVMERGELO,
+ PPC_INS_EVMERGELOHI,
+ PPC_INS_EVMHEGSMFAA,
+ PPC_INS_EVMHEGSMFAN,
+ PPC_INS_EVMHEGSMIAA,
+ PPC_INS_EVMHEGSMIAN,
+ PPC_INS_EVMHEGUMIAA,
+ PPC_INS_EVMHEGUMIAN,
+ PPC_INS_EVMHESMF,
+ PPC_INS_EVMHESMFA,
+ PPC_INS_EVMHESMFAAW,
+ PPC_INS_EVMHESMFANW,
+ PPC_INS_EVMHESMI,
+ PPC_INS_EVMHESMIA,
+ PPC_INS_EVMHESMIAAW,
+ PPC_INS_EVMHESMIANW,
+ PPC_INS_EVMHESSF,
+ PPC_INS_EVMHESSFA,
+ PPC_INS_EVMHESSFAAW,
+ PPC_INS_EVMHESSFANW,
+ PPC_INS_EVMHESSIAAW,
+ PPC_INS_EVMHESSIANW,
+ PPC_INS_EVMHEUMI,
+ PPC_INS_EVMHEUMIA,
+ PPC_INS_EVMHEUMIAAW,
+ PPC_INS_EVMHEUMIANW,
+ PPC_INS_EVMHEUSIAAW,
+ PPC_INS_EVMHEUSIANW,
+ PPC_INS_EVMHOGSMFAA,
+ PPC_INS_EVMHOGSMFAN,
+ PPC_INS_EVMHOGSMIAA,
+ PPC_INS_EVMHOGSMIAN,
+ PPC_INS_EVMHOGUMIAA,
+ PPC_INS_EVMHOGUMIAN,
+ PPC_INS_EVMHOSMF,
+ PPC_INS_EVMHOSMFA,
+ PPC_INS_EVMHOSMFAAW,
+ PPC_INS_EVMHOSMFANW,
+ PPC_INS_EVMHOSMI,
+ PPC_INS_EVMHOSMIA,
+ PPC_INS_EVMHOSMIAAW,
+ PPC_INS_EVMHOSMIANW,
+ PPC_INS_EVMHOSSF,
+ PPC_INS_EVMHOSSFA,
+ PPC_INS_EVMHOSSFAAW,
+ PPC_INS_EVMHOSSFANW,
+ PPC_INS_EVMHOSSIAAW,
+ PPC_INS_EVMHOSSIANW,
+ PPC_INS_EVMHOUMI,
+ PPC_INS_EVMHOUMIA,
+ PPC_INS_EVMHOUMIAAW,
+ PPC_INS_EVMHOUMIANW,
+ PPC_INS_EVMHOUSIAAW,
+ PPC_INS_EVMHOUSIANW,
+ PPC_INS_EVMRA,
+ PPC_INS_EVMWHSMF,
+ PPC_INS_EVMWHSMFA,
+ PPC_INS_EVMWHSMI,
+ PPC_INS_EVMWHSMIA,
+ PPC_INS_EVMWHSSF,
+ PPC_INS_EVMWHSSFA,
+ PPC_INS_EVMWHUMI,
+ PPC_INS_EVMWHUMIA,
+ PPC_INS_EVMWLSMIAAW,
+ PPC_INS_EVMWLSMIANW,
+ PPC_INS_EVMWLSSIAAW,
+ PPC_INS_EVMWLSSIANW,
+ PPC_INS_EVMWLUMI,
+ PPC_INS_EVMWLUMIA,
+ PPC_INS_EVMWLUMIAAW,
+ PPC_INS_EVMWLUMIANW,
+ PPC_INS_EVMWLUSIAAW,
+ PPC_INS_EVMWLUSIANW,
+ PPC_INS_EVMWSMF,
+ PPC_INS_EVMWSMFA,
+ PPC_INS_EVMWSMFAA,
+ PPC_INS_EVMWSMFAN,
+ PPC_INS_EVMWSMI,
+ PPC_INS_EVMWSMIA,
+ PPC_INS_EVMWSMIAA,
+ PPC_INS_EVMWSMIAN,
+ PPC_INS_EVMWSSF,
+ PPC_INS_EVMWSSFA,
+ PPC_INS_EVMWSSFAA,
+ PPC_INS_EVMWSSFAN,
+ PPC_INS_EVMWUMI,
+ PPC_INS_EVMWUMIA,
+ PPC_INS_EVMWUMIAA,
+ PPC_INS_EVMWUMIAN,
+ PPC_INS_EVNAND,
+ PPC_INS_EVNEG,
+ PPC_INS_EVNOR,
+ PPC_INS_EVOR,
+ PPC_INS_EVORC,
+ PPC_INS_EVRLW,
+ PPC_INS_EVRLWI,
+ PPC_INS_EVRNDW,
+ PPC_INS_EVSLW,
+ PPC_INS_EVSLWI,
+ PPC_INS_EVSPLATFI,
+ PPC_INS_EVSPLATI,
+ PPC_INS_EVSRWIS,
+ PPC_INS_EVSRWIU,
+ PPC_INS_EVSRWS,
+ PPC_INS_EVSRWU,
+ PPC_INS_EVSTDD,
+ PPC_INS_EVSTDDX,
+ PPC_INS_EVSTDH,
+ PPC_INS_EVSTDHX,
+ PPC_INS_EVSTDW,
+ PPC_INS_EVSTDWX,
+ PPC_INS_EVSTWHE,
+ PPC_INS_EVSTWHEX,
+ PPC_INS_EVSTWHO,
+ PPC_INS_EVSTWHOX,
+ PPC_INS_EVSTWWE,
+ PPC_INS_EVSTWWEX,
+ PPC_INS_EVSTWWO,
+ PPC_INS_EVSTWWOX,
+ PPC_INS_EVSUBFSMIAAW,
+ PPC_INS_EVSUBFSSIAAW,
+ PPC_INS_EVSUBFUMIAAW,
+ PPC_INS_EVSUBFUSIAAW,
+ PPC_INS_EVSUBFW,
+ PPC_INS_EVSUBIFW,
+ PPC_INS_EVXOR,
+ PPC_INS_EXTSB,
+ PPC_INS_EXTSH,
+ PPC_INS_EXTSW,
+ PPC_INS_EIEIO,
+ PPC_INS_FABS,
+ PPC_INS_FADD,
+ PPC_INS_FADDS,
+ PPC_INS_FCFID,
+ PPC_INS_FCFIDS,
+ PPC_INS_FCFIDU,
+ PPC_INS_FCFIDUS,
+ PPC_INS_FCMPU,
+ PPC_INS_FCPSGN,
+ PPC_INS_FCTID,
+ PPC_INS_FCTIDUZ,
+ PPC_INS_FCTIDZ,
+ PPC_INS_FCTIW,
+ PPC_INS_FCTIWUZ,
+ PPC_INS_FCTIWZ,
+ PPC_INS_FDIV,
+ PPC_INS_FDIVS,
+ PPC_INS_FMADD,
+ PPC_INS_FMADDS,
+ PPC_INS_FMR,
+ PPC_INS_FMSUB,
+ PPC_INS_FMSUBS,
+ PPC_INS_FMUL,
+ PPC_INS_FMULS,
+ PPC_INS_FNABS,
+ PPC_INS_FNEG,
+ PPC_INS_FNMADD,
+ PPC_INS_FNMADDS,
+ PPC_INS_FNMSUB,
+ PPC_INS_FNMSUBS,
+ PPC_INS_FRE,
+ PPC_INS_FRES,
+ PPC_INS_FRIM,
+ PPC_INS_FRIN,
+ PPC_INS_FRIP,
+ PPC_INS_FRIZ,
+ PPC_INS_FRSP,
+ PPC_INS_FRSQRTE,
+ PPC_INS_FRSQRTES,
+ PPC_INS_FSEL,
+ PPC_INS_FSQRT,
+ PPC_INS_FSQRTS,
+ PPC_INS_FSUB,
+ PPC_INS_FSUBS,
+ PPC_INS_ICBI,
+ PPC_INS_ICBT,
+ PPC_INS_ICCCI,
+ PPC_INS_ISEL,
+ PPC_INS_ISYNC,
+ PPC_INS_LA,
+ PPC_INS_LBZ,
+ PPC_INS_LBZCIX,
+ PPC_INS_LBZU,
+ PPC_INS_LBZUX,
+ PPC_INS_LBZX,
+ PPC_INS_LD,
+ PPC_INS_LDARX,
+ PPC_INS_LDBRX,
+ PPC_INS_LDCIX,
+ PPC_INS_LDU,
+ PPC_INS_LDUX,
+ PPC_INS_LDX,
+ PPC_INS_LFD,
+ PPC_INS_LFDU,
+ PPC_INS_LFDUX,
+ PPC_INS_LFDX,
+ PPC_INS_LFIWAX,
+ PPC_INS_LFIWZX,
+ PPC_INS_LFS,
+ PPC_INS_LFSU,
+ PPC_INS_LFSUX,
+ PPC_INS_LFSX,
+ PPC_INS_LHA,
+ PPC_INS_LHAU,
+ PPC_INS_LHAUX,
+ PPC_INS_LHAX,
+ PPC_INS_LHBRX,
+ PPC_INS_LHZ,
+ PPC_INS_LHZCIX,
+ PPC_INS_LHZU,
+ PPC_INS_LHZUX,
+ PPC_INS_LHZX,
+ PPC_INS_LI,
+ PPC_INS_LIS,
+ PPC_INS_LMW,
+ PPC_INS_LSWI,
+ PPC_INS_LVEBX,
+ PPC_INS_LVEHX,
+ PPC_INS_LVEWX,
+ PPC_INS_LVSL,
+ PPC_INS_LVSR,
+ PPC_INS_LVX,
+ PPC_INS_LVXL,
+ PPC_INS_LWA,
+ PPC_INS_LWARX,
+ PPC_INS_LWAUX,
+ PPC_INS_LWAX,
+ PPC_INS_LWBRX,
+ PPC_INS_LWZ,
+ PPC_INS_LWZCIX,
+ PPC_INS_LWZU,
+ PPC_INS_LWZUX,
+ PPC_INS_LWZX,
+ PPC_INS_LXSDX,
+ PPC_INS_LXVD2X,
+ PPC_INS_LXVDSX,
+ PPC_INS_LXVW4X,
+ PPC_INS_MBAR,
+ PPC_INS_MCRF,
+ PPC_INS_MCRFS,
+ PPC_INS_MFCR,
+ PPC_INS_MFCTR,
+ PPC_INS_MFDCR,
+ PPC_INS_MFFS,
+ PPC_INS_MFLR,
+ PPC_INS_MFMSR,
+ PPC_INS_MFOCRF,
+ PPC_INS_MFSPR,
+ PPC_INS_MFSR,
+ PPC_INS_MFSRIN,
+ PPC_INS_MFTB,
+ PPC_INS_MFVSCR,
+ PPC_INS_MSYNC,
+ PPC_INS_MTCRF,
+ PPC_INS_MTCTR,
+ PPC_INS_MTDCR,
+ PPC_INS_MTFSB0,
+ PPC_INS_MTFSB1,
+ PPC_INS_MTFSF,
+ PPC_INS_MTFSFI,
+ PPC_INS_MTLR,
+ PPC_INS_MTMSR,
+ PPC_INS_MTMSRD,
+ PPC_INS_MTOCRF,
+ PPC_INS_MTSPR,
+ PPC_INS_MTSR,
+ PPC_INS_MTSRIN,
+ PPC_INS_MTVSCR,
+ PPC_INS_MULHD,
+ PPC_INS_MULHDU,
+ PPC_INS_MULHW,
+ PPC_INS_MULHWU,
+ PPC_INS_MULLD,
+ PPC_INS_MULLI,
+ PPC_INS_MULLW,
+ PPC_INS_NAND,
+ PPC_INS_NEG,
+ PPC_INS_NOP,
+ PPC_INS_ORI,
+ PPC_INS_NOR,
+ PPC_INS_OR,
+ PPC_INS_ORC,
+ PPC_INS_ORIS,
+ PPC_INS_POPCNTD,
+ PPC_INS_POPCNTW,
+ PPC_INS_QVALIGNI,
+ PPC_INS_QVESPLATI,
+ PPC_INS_QVFABS,
+ PPC_INS_QVFADD,
+ PPC_INS_QVFADDS,
+ PPC_INS_QVFCFID,
+ PPC_INS_QVFCFIDS,
+ PPC_INS_QVFCFIDU,
+ PPC_INS_QVFCFIDUS,
+ PPC_INS_QVFCMPEQ,
+ PPC_INS_QVFCMPGT,
+ PPC_INS_QVFCMPLT,
+ PPC_INS_QVFCPSGN,
+ PPC_INS_QVFCTID,
+ PPC_INS_QVFCTIDU,
+ PPC_INS_QVFCTIDUZ,
+ PPC_INS_QVFCTIDZ,
+ PPC_INS_QVFCTIW,
+ PPC_INS_QVFCTIWU,
+ PPC_INS_QVFCTIWUZ,
+ PPC_INS_QVFCTIWZ,
+ PPC_INS_QVFLOGICAL,
+ PPC_INS_QVFMADD,
+ PPC_INS_QVFMADDS,
+ PPC_INS_QVFMR,
+ PPC_INS_QVFMSUB,
+ PPC_INS_QVFMSUBS,
+ PPC_INS_QVFMUL,
+ PPC_INS_QVFMULS,
+ PPC_INS_QVFNABS,
+ PPC_INS_QVFNEG,
+ PPC_INS_QVFNMADD,
+ PPC_INS_QVFNMADDS,
+ PPC_INS_QVFNMSUB,
+ PPC_INS_QVFNMSUBS,
+ PPC_INS_QVFPERM,
+ PPC_INS_QVFRE,
+ PPC_INS_QVFRES,
+ PPC_INS_QVFRIM,
+ PPC_INS_QVFRIN,
+ PPC_INS_QVFRIP,
+ PPC_INS_QVFRIZ,
+ PPC_INS_QVFRSP,
+ PPC_INS_QVFRSQRTE,
+ PPC_INS_QVFRSQRTES,
+ PPC_INS_QVFSEL,
+ PPC_INS_QVFSUB,
+ PPC_INS_QVFSUBS,
+ PPC_INS_QVFTSTNAN,
+ PPC_INS_QVFXMADD,
+ PPC_INS_QVFXMADDS,
+ PPC_INS_QVFXMUL,
+ PPC_INS_QVFXMULS,
+ PPC_INS_QVFXXCPNMADD,
+ PPC_INS_QVFXXCPNMADDS,
+ PPC_INS_QVFXXMADD,
+ PPC_INS_QVFXXMADDS,
+ PPC_INS_QVFXXNPMADD,
+ PPC_INS_QVFXXNPMADDS,
+ PPC_INS_QVGPCI,
+ PPC_INS_QVLFCDUX,
+ PPC_INS_QVLFCDUXA,
+ PPC_INS_QVLFCDX,
+ PPC_INS_QVLFCDXA,
+ PPC_INS_QVLFCSUX,
+ PPC_INS_QVLFCSUXA,
+ PPC_INS_QVLFCSX,
+ PPC_INS_QVLFCSXA,
+ PPC_INS_QVLFDUX,
+ PPC_INS_QVLFDUXA,
+ PPC_INS_QVLFDX,
+ PPC_INS_QVLFDXA,
+ PPC_INS_QVLFIWAX,
+ PPC_INS_QVLFIWAXA,
+ PPC_INS_QVLFIWZX,
+ PPC_INS_QVLFIWZXA,
+ PPC_INS_QVLFSUX,
+ PPC_INS_QVLFSUXA,
+ PPC_INS_QVLFSX,
+ PPC_INS_QVLFSXA,
+ PPC_INS_QVLPCLDX,
+ PPC_INS_QVLPCLSX,
+ PPC_INS_QVLPCRDX,
+ PPC_INS_QVLPCRSX,
+ PPC_INS_QVSTFCDUX,
+ PPC_INS_QVSTFCDUXA,
+ PPC_INS_QVSTFCDUXI,
+ PPC_INS_QVSTFCDUXIA,
+ PPC_INS_QVSTFCDX,
+ PPC_INS_QVSTFCDXA,
+ PPC_INS_QVSTFCDXI,
+ PPC_INS_QVSTFCDXIA,
+ PPC_INS_QVSTFCSUX,
+ PPC_INS_QVSTFCSUXA,
+ PPC_INS_QVSTFCSUXI,
+ PPC_INS_QVSTFCSUXIA,
+ PPC_INS_QVSTFCSX,
+ PPC_INS_QVSTFCSXA,
+ PPC_INS_QVSTFCSXI,
+ PPC_INS_QVSTFCSXIA,
+ PPC_INS_QVSTFDUX,
+ PPC_INS_QVSTFDUXA,
+ PPC_INS_QVSTFDUXI,
+ PPC_INS_QVSTFDUXIA,
+ PPC_INS_QVSTFDX,
+ PPC_INS_QVSTFDXA,
+ PPC_INS_QVSTFDXI,
+ PPC_INS_QVSTFDXIA,
+ PPC_INS_QVSTFIWX,
+ PPC_INS_QVSTFIWXA,
+ PPC_INS_QVSTFSUX,
+ PPC_INS_QVSTFSUXA,
+ PPC_INS_QVSTFSUXI,
+ PPC_INS_QVSTFSUXIA,
+ PPC_INS_QVSTFSX,
+ PPC_INS_QVSTFSXA,
+ PPC_INS_QVSTFSXI,
+ PPC_INS_QVSTFSXIA,
+ PPC_INS_RFCI,
+ PPC_INS_RFDI,
+ PPC_INS_RFI,
+ PPC_INS_RFID,
+ PPC_INS_RFMCI,
+ PPC_INS_RLDCL,
+ PPC_INS_RLDCR,
+ PPC_INS_RLDIC,
+ PPC_INS_RLDICL,
+ PPC_INS_RLDICR,
+ PPC_INS_RLDIMI,
+ PPC_INS_RLWIMI,
+ PPC_INS_RLWINM,
+ PPC_INS_RLWNM,
+ PPC_INS_SC,
+ PPC_INS_SLBIA,
+ PPC_INS_SLBIE,
+ PPC_INS_SLBMFEE,
+ PPC_INS_SLBMTE,
+ PPC_INS_SLD,
+ PPC_INS_SLW,
+ PPC_INS_SRAD,
+ PPC_INS_SRADI,
+ PPC_INS_SRAW,
+ PPC_INS_SRAWI,
+ PPC_INS_SRD,
+ PPC_INS_SRW,
+ PPC_INS_STB,
+ PPC_INS_STBCIX,
+ PPC_INS_STBU,
+ PPC_INS_STBUX,
+ PPC_INS_STBX,
+ PPC_INS_STD,
+ PPC_INS_STDBRX,
+ PPC_INS_STDCIX,
+ PPC_INS_STDCX,
+ PPC_INS_STDU,
+ PPC_INS_STDUX,
+ PPC_INS_STDX,
+ PPC_INS_STFD,
+ PPC_INS_STFDU,
+ PPC_INS_STFDUX,
+ PPC_INS_STFDX,
+ PPC_INS_STFIWX,
+ PPC_INS_STFS,
+ PPC_INS_STFSU,
+ PPC_INS_STFSUX,
+ PPC_INS_STFSX,
+ PPC_INS_STH,
+ PPC_INS_STHBRX,
+ PPC_INS_STHCIX,
+ PPC_INS_STHU,
+ PPC_INS_STHUX,
+ PPC_INS_STHX,
+ PPC_INS_STMW,
+ PPC_INS_STSWI,
+ PPC_INS_STVEBX,
+ PPC_INS_STVEHX,
+ PPC_INS_STVEWX,
+ PPC_INS_STVX,
+ PPC_INS_STVXL,
+ PPC_INS_STW,
+ PPC_INS_STWBRX,
+ PPC_INS_STWCIX,
+ PPC_INS_STWCX,
+ PPC_INS_STWU,
+ PPC_INS_STWUX,
+ PPC_INS_STWX,
+ PPC_INS_STXSDX,
+ PPC_INS_STXVD2X,
+ PPC_INS_STXVW4X,
+ PPC_INS_SUBF,
+ PPC_INS_SUBFC,
+ PPC_INS_SUBFE,
+ PPC_INS_SUBFIC,
+ PPC_INS_SUBFME,
+ PPC_INS_SUBFZE,
+ PPC_INS_SYNC,
+ PPC_INS_TD,
+ PPC_INS_TDI,
+ PPC_INS_TLBIA,
+ PPC_INS_TLBIE,
+ PPC_INS_TLBIEL,
+ PPC_INS_TLBIVAX,
+ PPC_INS_TLBLD,
+ PPC_INS_TLBLI,
+ PPC_INS_TLBRE,
+ PPC_INS_TLBSX,
+ PPC_INS_TLBSYNC,
+ PPC_INS_TLBWE,
+ PPC_INS_TRAP,
+ PPC_INS_TW,
+ PPC_INS_TWI,
+ PPC_INS_VADDCUW,
+ PPC_INS_VADDFP,
+ PPC_INS_VADDSBS,
+ PPC_INS_VADDSHS,
+ PPC_INS_VADDSWS,
+ PPC_INS_VADDUBM,
+ PPC_INS_VADDUBS,
+ PPC_INS_VADDUDM,
+ PPC_INS_VADDUHM,
+ PPC_INS_VADDUHS,
+ PPC_INS_VADDUWM,
+ PPC_INS_VADDUWS,
+ PPC_INS_VAND,
+ PPC_INS_VANDC,
+ PPC_INS_VAVGSB,
+ PPC_INS_VAVGSH,
+ PPC_INS_VAVGSW,
+ PPC_INS_VAVGUB,
+ PPC_INS_VAVGUH,
+ PPC_INS_VAVGUW,
+ PPC_INS_VCFSX,
+ PPC_INS_VCFUX,
+ PPC_INS_VCLZB,
+ PPC_INS_VCLZD,
+ PPC_INS_VCLZH,
+ PPC_INS_VCLZW,
+ PPC_INS_VCMPBFP,
+ PPC_INS_VCMPEQFP,
+ PPC_INS_VCMPEQUB,
+ PPC_INS_VCMPEQUD,
+ PPC_INS_VCMPEQUH,
+ PPC_INS_VCMPEQUW,
+ PPC_INS_VCMPGEFP,
+ PPC_INS_VCMPGTFP,
+ PPC_INS_VCMPGTSB,
+ PPC_INS_VCMPGTSD,
+ PPC_INS_VCMPGTSH,
+ PPC_INS_VCMPGTSW,
+ PPC_INS_VCMPGTUB,
+ PPC_INS_VCMPGTUD,
+ PPC_INS_VCMPGTUH,
+ PPC_INS_VCMPGTUW,
+ PPC_INS_VCTSXS,
+ PPC_INS_VCTUXS,
+ PPC_INS_VEQV,
+ PPC_INS_VEXPTEFP,
+ PPC_INS_VLOGEFP,
+ PPC_INS_VMADDFP,
+ PPC_INS_VMAXFP,
+ PPC_INS_VMAXSB,
+ PPC_INS_VMAXSD,
+ PPC_INS_VMAXSH,
+ PPC_INS_VMAXSW,
+ PPC_INS_VMAXUB,
+ PPC_INS_VMAXUD,
+ PPC_INS_VMAXUH,
+ PPC_INS_VMAXUW,
+ PPC_INS_VMHADDSHS,
+ PPC_INS_VMHRADDSHS,
+ PPC_INS_VMINUD,
+ PPC_INS_VMINFP,
+ PPC_INS_VMINSB,
+ PPC_INS_VMINSD,
+ PPC_INS_VMINSH,
+ PPC_INS_VMINSW,
+ PPC_INS_VMINUB,
+ PPC_INS_VMINUH,
+ PPC_INS_VMINUW,
+ PPC_INS_VMLADDUHM,
+ PPC_INS_VMRGHB,
+ PPC_INS_VMRGHH,
+ PPC_INS_VMRGHW,
+ PPC_INS_VMRGLB,
+ PPC_INS_VMRGLH,
+ PPC_INS_VMRGLW,
+ PPC_INS_VMSUMMBM,
+ PPC_INS_VMSUMSHM,
+ PPC_INS_VMSUMSHS,
+ PPC_INS_VMSUMUBM,
+ PPC_INS_VMSUMUHM,
+ PPC_INS_VMSUMUHS,
+ PPC_INS_VMULESB,
+ PPC_INS_VMULESH,
+ PPC_INS_VMULESW,
+ PPC_INS_VMULEUB,
+ PPC_INS_VMULEUH,
+ PPC_INS_VMULEUW,
+ PPC_INS_VMULOSB,
+ PPC_INS_VMULOSH,
+ PPC_INS_VMULOSW,
+ PPC_INS_VMULOUB,
+ PPC_INS_VMULOUH,
+ PPC_INS_VMULOUW,
+ PPC_INS_VMULUWM,
+ PPC_INS_VNAND,
+ PPC_INS_VNMSUBFP,
+ PPC_INS_VNOR,
+ PPC_INS_VOR,
+ PPC_INS_VORC,
+ PPC_INS_VPERM,
+ PPC_INS_VPKPX,
+ PPC_INS_VPKSHSS,
+ PPC_INS_VPKSHUS,
+ PPC_INS_VPKSWSS,
+ PPC_INS_VPKSWUS,
+ PPC_INS_VPKUHUM,
+ PPC_INS_VPKUHUS,
+ PPC_INS_VPKUWUM,
+ PPC_INS_VPKUWUS,
+ PPC_INS_VPOPCNTB,
+ PPC_INS_VPOPCNTD,
+ PPC_INS_VPOPCNTH,
+ PPC_INS_VPOPCNTW,
+ PPC_INS_VREFP,
+ PPC_INS_VRFIM,
+ PPC_INS_VRFIN,
+ PPC_INS_VRFIP,
+ PPC_INS_VRFIZ,
+ PPC_INS_VRLB,
+ PPC_INS_VRLD,
+ PPC_INS_VRLH,
+ PPC_INS_VRLW,
+ PPC_INS_VRSQRTEFP,
+ PPC_INS_VSEL,
+ PPC_INS_VSL,
+ PPC_INS_VSLB,
+ PPC_INS_VSLD,
+ PPC_INS_VSLDOI,
+ PPC_INS_VSLH,
+ PPC_INS_VSLO,
+ PPC_INS_VSLW,
+ PPC_INS_VSPLTB,
+ PPC_INS_VSPLTH,
+ PPC_INS_VSPLTISB,
+ PPC_INS_VSPLTISH,
+ PPC_INS_VSPLTISW,
+ PPC_INS_VSPLTW,
+ PPC_INS_VSR,
+ PPC_INS_VSRAB,
+ PPC_INS_VSRAD,
+ PPC_INS_VSRAH,
+ PPC_INS_VSRAW,
+ PPC_INS_VSRB,
+ PPC_INS_VSRD,
+ PPC_INS_VSRH,
+ PPC_INS_VSRO,
+ PPC_INS_VSRW,
+ PPC_INS_VSUBCUW,
+ PPC_INS_VSUBFP,
+ PPC_INS_VSUBSBS,
+ PPC_INS_VSUBSHS,
+ PPC_INS_VSUBSWS,
+ PPC_INS_VSUBUBM,
+ PPC_INS_VSUBUBS,
+ PPC_INS_VSUBUDM,
+ PPC_INS_VSUBUHM,
+ PPC_INS_VSUBUHS,
+ PPC_INS_VSUBUWM,
+ PPC_INS_VSUBUWS,
+ PPC_INS_VSUM2SWS,
+ PPC_INS_VSUM4SBS,
+ PPC_INS_VSUM4SHS,
+ PPC_INS_VSUM4UBS,
+ PPC_INS_VSUMSWS,
+ PPC_INS_VUPKHPX,
+ PPC_INS_VUPKHSB,
+ PPC_INS_VUPKHSH,
+ PPC_INS_VUPKLPX,
+ PPC_INS_VUPKLSB,
+ PPC_INS_VUPKLSH,
+ PPC_INS_VXOR,
+ PPC_INS_WAIT,
+ PPC_INS_WRTEE,
+ PPC_INS_WRTEEI,
+ PPC_INS_XOR,
+ PPC_INS_XORI,
+ PPC_INS_XORIS,
+ PPC_INS_XSABSDP,
+ PPC_INS_XSADDDP,
+ PPC_INS_XSCMPODP,
+ PPC_INS_XSCMPUDP,
+ PPC_INS_XSCPSGNDP,
+ PPC_INS_XSCVDPSP,
+ PPC_INS_XSCVDPSXDS,
+ PPC_INS_XSCVDPSXWS,
+ PPC_INS_XSCVDPUXDS,
+ PPC_INS_XSCVDPUXWS,
+ PPC_INS_XSCVSPDP,
+ PPC_INS_XSCVSXDDP,
+ PPC_INS_XSCVUXDDP,
+ PPC_INS_XSDIVDP,
+ PPC_INS_XSMADDADP,
+ PPC_INS_XSMADDMDP,
+ PPC_INS_XSMAXDP,
+ PPC_INS_XSMINDP,
+ PPC_INS_XSMSUBADP,
+ PPC_INS_XSMSUBMDP,
+ PPC_INS_XSMULDP,
+ PPC_INS_XSNABSDP,
+ PPC_INS_XSNEGDP,
+ PPC_INS_XSNMADDADP,
+ PPC_INS_XSNMADDMDP,
+ PPC_INS_XSNMSUBADP,
+ PPC_INS_XSNMSUBMDP,
+ PPC_INS_XSRDPI,
+ PPC_INS_XSRDPIC,
+ PPC_INS_XSRDPIM,
+ PPC_INS_XSRDPIP,
+ PPC_INS_XSRDPIZ,
+ PPC_INS_XSREDP,
+ PPC_INS_XSRSQRTEDP,
+ PPC_INS_XSSQRTDP,
+ PPC_INS_XSSUBDP,
+ PPC_INS_XSTDIVDP,
+ PPC_INS_XSTSQRTDP,
+ PPC_INS_XVABSDP,
+ PPC_INS_XVABSSP,
+ PPC_INS_XVADDDP,
+ PPC_INS_XVADDSP,
+ PPC_INS_XVCMPEQDP,
+ PPC_INS_XVCMPEQSP,
+ PPC_INS_XVCMPGEDP,
+ PPC_INS_XVCMPGESP,
+ PPC_INS_XVCMPGTDP,
+ PPC_INS_XVCMPGTSP,
+ PPC_INS_XVCPSGNDP,
+ PPC_INS_XVCPSGNSP,
+ PPC_INS_XVCVDPSP,
+ PPC_INS_XVCVDPSXDS,
+ PPC_INS_XVCVDPSXWS,
+ PPC_INS_XVCVDPUXDS,
+ PPC_INS_XVCVDPUXWS,
+ PPC_INS_XVCVSPDP,
+ PPC_INS_XVCVSPSXDS,
+ PPC_INS_XVCVSPSXWS,
+ PPC_INS_XVCVSPUXDS,
+ PPC_INS_XVCVSPUXWS,
+ PPC_INS_XVCVSXDDP,
+ PPC_INS_XVCVSXDSP,
+ PPC_INS_XVCVSXWDP,
+ PPC_INS_XVCVSXWSP,
+ PPC_INS_XVCVUXDDP,
+ PPC_INS_XVCVUXDSP,
+ PPC_INS_XVCVUXWDP,
+ PPC_INS_XVCVUXWSP,
+ PPC_INS_XVDIVDP,
+ PPC_INS_XVDIVSP,
+ PPC_INS_XVMADDADP,
+ PPC_INS_XVMADDASP,
+ PPC_INS_XVMADDMDP,
+ PPC_INS_XVMADDMSP,
+ PPC_INS_XVMAXDP,
+ PPC_INS_XVMAXSP,
+ PPC_INS_XVMINDP,
+ PPC_INS_XVMINSP,
+ PPC_INS_XVMSUBADP,
+ PPC_INS_XVMSUBASP,
+ PPC_INS_XVMSUBMDP,
+ PPC_INS_XVMSUBMSP,
+ PPC_INS_XVMULDP,
+ PPC_INS_XVMULSP,
+ PPC_INS_XVNABSDP,
+ PPC_INS_XVNABSSP,
+ PPC_INS_XVNEGDP,
+ PPC_INS_XVNEGSP,
+ PPC_INS_XVNMADDADP,
+ PPC_INS_XVNMADDASP,
+ PPC_INS_XVNMADDMDP,
+ PPC_INS_XVNMADDMSP,
+ PPC_INS_XVNMSUBADP,
+ PPC_INS_XVNMSUBASP,
+ PPC_INS_XVNMSUBMDP,
+ PPC_INS_XVNMSUBMSP,
+ PPC_INS_XVRDPI,
+ PPC_INS_XVRDPIC,
+ PPC_INS_XVRDPIM,
+ PPC_INS_XVRDPIP,
+ PPC_INS_XVRDPIZ,
+ PPC_INS_XVREDP,
+ PPC_INS_XVRESP,
+ PPC_INS_XVRSPI,
+ PPC_INS_XVRSPIC,
+ PPC_INS_XVRSPIM,
+ PPC_INS_XVRSPIP,
+ PPC_INS_XVRSPIZ,
+ PPC_INS_XVRSQRTEDP,
+ PPC_INS_XVRSQRTESP,
+ PPC_INS_XVSQRTDP,
+ PPC_INS_XVSQRTSP,
+ PPC_INS_XVSUBDP,
+ PPC_INS_XVSUBSP,
+ PPC_INS_XVTDIVDP,
+ PPC_INS_XVTDIVSP,
+ PPC_INS_XVTSQRTDP,
+ PPC_INS_XVTSQRTSP,
+ PPC_INS_XXLAND,
+ PPC_INS_XXLANDC,
+ PPC_INS_XXLEQV,
+ PPC_INS_XXLNAND,
+ PPC_INS_XXLNOR,
+ PPC_INS_XXLOR,
+ PPC_INS_XXLORC,
+ PPC_INS_XXLXOR,
+ PPC_INS_XXMRGHW,
+ PPC_INS_XXMRGLW,
+ PPC_INS_XXPERMDI,
+ PPC_INS_XXSEL,
+ PPC_INS_XXSLDWI,
+ PPC_INS_XXSPLTW,
+ PPC_INS_BCA,
+ PPC_INS_BCLA,
+
+ // extra & alias instructions
+ PPC_INS_SLWI,
+ PPC_INS_SRWI,
+ PPC_INS_SLDI,
+
+ PPC_INS_BTA,
+ PPC_INS_CRSET,
+ PPC_INS_CRNOT,
+ PPC_INS_CRMOVE,
+ PPC_INS_CRCLR,
+ PPC_INS_MFBR0,
+ PPC_INS_MFBR1,
+ PPC_INS_MFBR2,
+ PPC_INS_MFBR3,
+ PPC_INS_MFBR4,
+ PPC_INS_MFBR5,
+ PPC_INS_MFBR6,
+ PPC_INS_MFBR7,
+ PPC_INS_MFXER,
+ PPC_INS_MFRTCU,
+ PPC_INS_MFRTCL,
+ PPC_INS_MFDSCR,
+ PPC_INS_MFDSISR,
+ PPC_INS_MFDAR,
+ PPC_INS_MFSRR2,
+ PPC_INS_MFSRR3,
+ PPC_INS_MFCFAR,
+ PPC_INS_MFAMR,
+ PPC_INS_MFPID,
+ PPC_INS_MFTBLO,
+ PPC_INS_MFTBHI,
+ PPC_INS_MFDBATU,
+ PPC_INS_MFDBATL,
+ PPC_INS_MFIBATU,
+ PPC_INS_MFIBATL,
+ PPC_INS_MFDCCR,
+ PPC_INS_MFICCR,
+ PPC_INS_MFDEAR,
+ PPC_INS_MFESR,
+ PPC_INS_MFSPEFSCR,
+ PPC_INS_MFTCR,
+ PPC_INS_MFASR,
+ PPC_INS_MFPVR,
+ PPC_INS_MFTBU,
+ PPC_INS_MTCR,
+ PPC_INS_MTBR0,
+ PPC_INS_MTBR1,
+ PPC_INS_MTBR2,
+ PPC_INS_MTBR3,
+ PPC_INS_MTBR4,
+ PPC_INS_MTBR5,
+ PPC_INS_MTBR6,
+ PPC_INS_MTBR7,
+ PPC_INS_MTXER,
+ PPC_INS_MTDSCR,
+ PPC_INS_MTDSISR,
+ PPC_INS_MTDAR,
+ PPC_INS_MTSRR2,
+ PPC_INS_MTSRR3,
+ PPC_INS_MTCFAR,
+ PPC_INS_MTAMR,
+ PPC_INS_MTPID,
+ PPC_INS_MTTBL,
+ PPC_INS_MTTBU,
+ PPC_INS_MTTBLO,
+ PPC_INS_MTTBHI,
+ PPC_INS_MTDBATU,
+ PPC_INS_MTDBATL,
+ PPC_INS_MTIBATU,
+ PPC_INS_MTIBATL,
+ PPC_INS_MTDCCR,
+ PPC_INS_MTICCR,
+ PPC_INS_MTDEAR,
+ PPC_INS_MTESR,
+ PPC_INS_MTSPEFSCR,
+ PPC_INS_MTTCR,
+ PPC_INS_NOT,
+ PPC_INS_MR,
+ PPC_INS_ROTLD,
+ PPC_INS_ROTLDI,
+ PPC_INS_CLRLDI,
+ PPC_INS_ROTLWI,
+ PPC_INS_CLRLWI,
+ PPC_INS_ROTLW,
+ PPC_INS_SUB,
+ PPC_INS_SUBC,
+ PPC_INS_LWSYNC,
+ PPC_INS_PTESYNC,
+ PPC_INS_TDLT,
+ PPC_INS_TDEQ,
+ PPC_INS_TDGT,
+ PPC_INS_TDNE,
+ PPC_INS_TDLLT,
+ PPC_INS_TDLGT,
+ PPC_INS_TDU,
+ PPC_INS_TDLTI,
+ PPC_INS_TDEQI,
+ PPC_INS_TDGTI,
+ PPC_INS_TDNEI,
+ PPC_INS_TDLLTI,
+ PPC_INS_TDLGTI,
+ PPC_INS_TDUI,
+ PPC_INS_TLBREHI,
+ PPC_INS_TLBRELO,
+ PPC_INS_TLBWEHI,
+ PPC_INS_TLBWELO,
+ PPC_INS_TWLT,
+ PPC_INS_TWEQ,
+ PPC_INS_TWGT,
+ PPC_INS_TWNE,
+ PPC_INS_TWLLT,
+ PPC_INS_TWLGT,
+ PPC_INS_TWU,
+ PPC_INS_TWLTI,
+ PPC_INS_TWEQI,
+ PPC_INS_TWGTI,
+ PPC_INS_TWNEI,
+ PPC_INS_TWLLTI,
+ PPC_INS_TWLGTI,
+ PPC_INS_TWUI,
+ PPC_INS_WAITRSV,
+ PPC_INS_WAITIMPL,
+ PPC_INS_XNOP,
+ PPC_INS_XVMOVDP,
+ PPC_INS_XVMOVSP,
+ PPC_INS_XXSPLTD,
+ PPC_INS_XXMRGHD,
+ PPC_INS_XXMRGLD,
+ PPC_INS_XXSWAPD,
+ PPC_INS_BT,
+ PPC_INS_BF,
+ PPC_INS_BDNZT,
+ PPC_INS_BDNZF,
+ PPC_INS_BDZF,
+ PPC_INS_BDZT,
+ PPC_INS_BFA,
+ PPC_INS_BDNZTA,
+ PPC_INS_BDNZFA,
+ PPC_INS_BDZTA,
+ PPC_INS_BDZFA,
+ PPC_INS_BTCTR,
+ PPC_INS_BFCTR,
+ PPC_INS_BTCTRL,
+ PPC_INS_BFCTRL,
+ PPC_INS_BTL,
+ PPC_INS_BFL,
+ PPC_INS_BDNZTL,
+ PPC_INS_BDNZFL,
+ PPC_INS_BDZTL,
+ PPC_INS_BDZFL,
+ PPC_INS_BTLA,
+ PPC_INS_BFLA,
+ PPC_INS_BDNZTLA,
+ PPC_INS_BDNZFLA,
+ PPC_INS_BDZTLA,
+ PPC_INS_BDZFLA,
+ PPC_INS_BTLR,
+ PPC_INS_BFLR,
+ PPC_INS_BDNZTLR,
+ PPC_INS_BDZTLR,
+ PPC_INS_BDZFLR,
+ PPC_INS_BTLRL,
+ PPC_INS_BFLRL,
+ PPC_INS_BDNZTLRL,
+ PPC_INS_BDNZFLRL,
+ PPC_INS_BDZTLRL,
+ PPC_INS_BDZFLRL,
+
+ // QPX
+ PPC_INS_QVFAND,
+ PPC_INS_QVFCLR,
+ PPC_INS_QVFANDC,
+ PPC_INS_QVFCTFB,
+ PPC_INS_QVFXOR,
+ PPC_INS_QVFOR,
+ PPC_INS_QVFNOR,
+ PPC_INS_QVFEQU,
+ PPC_INS_QVFNOT,
+ PPC_INS_QVFORC,
+ PPC_INS_QVFNAND,
+ PPC_INS_QVFSET,
+
+ PPC_INS_ENDING, // <-- mark the end of the list of instructions
+} ppc_insn;
+
+/// Group of PPC instructions
+typedef enum ppc_insn_group {
+ PPC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ PPC_GRP_JUMP, ///< = CS_GRP_JUMP
+
+ // Architecture-specific groups
+ PPC_GRP_ALTIVEC = 128,
+ PPC_GRP_MODE32,
+ PPC_GRP_MODE64,
+ PPC_GRP_BOOKE,
+ PPC_GRP_NOTBOOKE,
+ PPC_GRP_SPE,
+ PPC_GRP_VSX,
+ PPC_GRP_E500,
+ PPC_GRP_PPC4XX,
+ PPC_GRP_PPC6XX,
+ PPC_GRP_ICBT,
+ PPC_GRP_P8ALTIVEC,
+ PPC_GRP_P8VECTOR,
+ PPC_GRP_QPX,
+
+ PPC_GRP_ENDING, // <-- mark the end of the list of groups
+} ppc_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/sparc.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/sparc.h
new file mode 100644
index 00000000..e33d1739
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/sparc.h
@@ -0,0 +1,520 @@
+#ifndef CAPSTONE_SPARC_H
+#define CAPSTONE_SPARC_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2014-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+// GCC SPARC toolchain has a default macro called "sparc" which breaks
+// compilation
+#undef sparc
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Enums corresponding to Sparc condition codes, both icc's and fcc's.
+typedef enum sparc_cc {
+ SPARC_CC_INVALID = 0, ///< invalid CC (default)
+ // Integer condition codes
+ SPARC_CC_ICC_A = 8+256, ///< Always
+ SPARC_CC_ICC_N = 0+256, ///< Never
+ SPARC_CC_ICC_NE = 9+256, ///< Not Equal
+ SPARC_CC_ICC_E = 1+256, ///< Equal
+ SPARC_CC_ICC_G = 10+256, ///< Greater
+ SPARC_CC_ICC_LE = 2+256, ///< Less or Equal
+ SPARC_CC_ICC_GE = 11+256, ///< Greater or Equal
+ SPARC_CC_ICC_L = 3+256, ///< Less
+ SPARC_CC_ICC_GU = 12+256, ///< Greater Unsigned
+ SPARC_CC_ICC_LEU = 4+256, ///< Less or Equal Unsigned
+ SPARC_CC_ICC_CC = 13+256, ///< Carry Clear/Great or Equal Unsigned
+ SPARC_CC_ICC_CS = 5+256, ///< Carry Set/Less Unsigned
+ SPARC_CC_ICC_POS = 14+256, ///< Positive
+ SPARC_CC_ICC_NEG = 6+256, ///< Negative
+ SPARC_CC_ICC_VC = 15+256, ///< Overflow Clear
+ SPARC_CC_ICC_VS = 7+256, ///< Overflow Set
+
+ // Floating condition codes
+ SPARC_CC_FCC_A = 8+16+256, ///< Always
+ SPARC_CC_FCC_N = 0+16+256, ///< Never
+ SPARC_CC_FCC_U = 7+16+256, ///< Unordered
+ SPARC_CC_FCC_G = 6+16+256, ///< Greater
+ SPARC_CC_FCC_UG = 5+16+256, ///< Unordered or Greater
+ SPARC_CC_FCC_L = 4+16+256, ///< Less
+ SPARC_CC_FCC_UL = 3+16+256, ///< Unordered or Less
+ SPARC_CC_FCC_LG = 2+16+256, ///< Less or Greater
+ SPARC_CC_FCC_NE = 1+16+256, ///< Not Equal
+ SPARC_CC_FCC_E = 9+16+256, ///< Equal
+ SPARC_CC_FCC_UE = 10+16+256, ///< Unordered or Equal
+ SPARC_CC_FCC_GE = 11+16+256, ///< Greater or Equal
+ SPARC_CC_FCC_UGE = 12+16+256, ///< Unordered or Greater or Equal
+ SPARC_CC_FCC_LE = 13+16+256, ///< Less or Equal
+ SPARC_CC_FCC_ULE = 14+16+256, ///< Unordered or Less or Equal
+ SPARC_CC_FCC_O = 15+16+256, ///< Ordered
+} sparc_cc;
+
+/// Branch hint
+typedef enum sparc_hint {
+ SPARC_HINT_INVALID = 0, ///< no hint
+ SPARC_HINT_A = 1 << 0, ///< annul delay slot instruction
+ SPARC_HINT_PT = 1 << 1, ///< branch taken
+ SPARC_HINT_PN = 1 << 2, ///< branch NOT taken
+} sparc_hint;
+
+/// Operand type for instruction's operands
+typedef enum sparc_op_type {
+ SPARC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ SPARC_OP_REG, ///< = CS_OP_REG (Register operand).
+ SPARC_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ SPARC_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} sparc_op_type;
+
+/// SPARC registers
+typedef enum sparc_reg {
+ SPARC_REG_INVALID = 0,
+
+ SPARC_REG_F0,
+ SPARC_REG_F1,
+ SPARC_REG_F2,
+ SPARC_REG_F3,
+ SPARC_REG_F4,
+ SPARC_REG_F5,
+ SPARC_REG_F6,
+ SPARC_REG_F7,
+ SPARC_REG_F8,
+ SPARC_REG_F9,
+ SPARC_REG_F10,
+ SPARC_REG_F11,
+ SPARC_REG_F12,
+ SPARC_REG_F13,
+ SPARC_REG_F14,
+ SPARC_REG_F15,
+ SPARC_REG_F16,
+ SPARC_REG_F17,
+ SPARC_REG_F18,
+ SPARC_REG_F19,
+ SPARC_REG_F20,
+ SPARC_REG_F21,
+ SPARC_REG_F22,
+ SPARC_REG_F23,
+ SPARC_REG_F24,
+ SPARC_REG_F25,
+ SPARC_REG_F26,
+ SPARC_REG_F27,
+ SPARC_REG_F28,
+ SPARC_REG_F29,
+ SPARC_REG_F30,
+ SPARC_REG_F31,
+ SPARC_REG_F32,
+ SPARC_REG_F34,
+ SPARC_REG_F36,
+ SPARC_REG_F38,
+ SPARC_REG_F40,
+ SPARC_REG_F42,
+ SPARC_REG_F44,
+ SPARC_REG_F46,
+ SPARC_REG_F48,
+ SPARC_REG_F50,
+ SPARC_REG_F52,
+ SPARC_REG_F54,
+ SPARC_REG_F56,
+ SPARC_REG_F58,
+ SPARC_REG_F60,
+ SPARC_REG_F62,
+ SPARC_REG_FCC0, // Floating condition codes
+ SPARC_REG_FCC1,
+ SPARC_REG_FCC2,
+ SPARC_REG_FCC3,
+ SPARC_REG_FP,
+ SPARC_REG_G0,
+ SPARC_REG_G1,
+ SPARC_REG_G2,
+ SPARC_REG_G3,
+ SPARC_REG_G4,
+ SPARC_REG_G5,
+ SPARC_REG_G6,
+ SPARC_REG_G7,
+ SPARC_REG_I0,
+ SPARC_REG_I1,
+ SPARC_REG_I2,
+ SPARC_REG_I3,
+ SPARC_REG_I4,
+ SPARC_REG_I5,
+ SPARC_REG_I7,
+ SPARC_REG_ICC, // Integer condition codes
+ SPARC_REG_L0,
+ SPARC_REG_L1,
+ SPARC_REG_L2,
+ SPARC_REG_L3,
+ SPARC_REG_L4,
+ SPARC_REG_L5,
+ SPARC_REG_L6,
+ SPARC_REG_L7,
+ SPARC_REG_O0,
+ SPARC_REG_O1,
+ SPARC_REG_O2,
+ SPARC_REG_O3,
+ SPARC_REG_O4,
+ SPARC_REG_O5,
+ SPARC_REG_O7,
+ SPARC_REG_SP,
+ SPARC_REG_Y,
+
+ // special register
+ SPARC_REG_XCC,
+
+ SPARC_REG_ENDING, // <-- mark the end of the list of registers
+
+ // extras
+ SPARC_REG_O6 = SPARC_REG_SP,
+ SPARC_REG_I6 = SPARC_REG_FP,
+} sparc_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with SPARC_OP_MEM operand type above
+typedef struct sparc_op_mem {
+ uint8_t base; ///< base register, can be safely interpreted as
+ ///< a value of type `sparc_reg`, but it is only
+ ///< one byte wide
+ uint8_t index; ///< index register, same conditions apply here
+ int32_t disp; ///< displacement/offset value
+} sparc_op_mem;
+
+/// Instruction operand
+typedef struct cs_sparc_op {
+ sparc_op_type type; ///< operand type
+ union {
+ sparc_reg reg; ///< register value for REG operand
+ int64_t imm; ///< immediate value for IMM operand
+ sparc_op_mem mem; ///< base/disp value for MEM operand
+ };
+} cs_sparc_op;
+
+/// Instruction structure
+typedef struct cs_sparc {
+ sparc_cc cc; ///< code condition for this insn
+ sparc_hint hint; ///< branch hint: encoding as bitwise OR of sparc_hint.
+ /// Number of operands of this instruction,
+ /// or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_sparc_op operands[4]; ///< operands for this instruction.
+} cs_sparc;
+
+/// SPARC instruction
+typedef enum sparc_insn {
+ SPARC_INS_INVALID = 0,
+
+ SPARC_INS_ADDCC,
+ SPARC_INS_ADDX,
+ SPARC_INS_ADDXCC,
+ SPARC_INS_ADDXC,
+ SPARC_INS_ADDXCCC,
+ SPARC_INS_ADD,
+ SPARC_INS_ALIGNADDR,
+ SPARC_INS_ALIGNADDRL,
+ SPARC_INS_ANDCC,
+ SPARC_INS_ANDNCC,
+ SPARC_INS_ANDN,
+ SPARC_INS_AND,
+ SPARC_INS_ARRAY16,
+ SPARC_INS_ARRAY32,
+ SPARC_INS_ARRAY8,
+ SPARC_INS_B,
+ SPARC_INS_JMP,
+ SPARC_INS_BMASK,
+ SPARC_INS_FB,
+ SPARC_INS_BRGEZ,
+ SPARC_INS_BRGZ,
+ SPARC_INS_BRLEZ,
+ SPARC_INS_BRLZ,
+ SPARC_INS_BRNZ,
+ SPARC_INS_BRZ,
+ SPARC_INS_BSHUFFLE,
+ SPARC_INS_CALL,
+ SPARC_INS_CASX,
+ SPARC_INS_CAS,
+ SPARC_INS_CMASK16,
+ SPARC_INS_CMASK32,
+ SPARC_INS_CMASK8,
+ SPARC_INS_CMP,
+ SPARC_INS_EDGE16,
+ SPARC_INS_EDGE16L,
+ SPARC_INS_EDGE16LN,
+ SPARC_INS_EDGE16N,
+ SPARC_INS_EDGE32,
+ SPARC_INS_EDGE32L,
+ SPARC_INS_EDGE32LN,
+ SPARC_INS_EDGE32N,
+ SPARC_INS_EDGE8,
+ SPARC_INS_EDGE8L,
+ SPARC_INS_EDGE8LN,
+ SPARC_INS_EDGE8N,
+ SPARC_INS_FABSD,
+ SPARC_INS_FABSQ,
+ SPARC_INS_FABSS,
+ SPARC_INS_FADDD,
+ SPARC_INS_FADDQ,
+ SPARC_INS_FADDS,
+ SPARC_INS_FALIGNDATA,
+ SPARC_INS_FAND,
+ SPARC_INS_FANDNOT1,
+ SPARC_INS_FANDNOT1S,
+ SPARC_INS_FANDNOT2,
+ SPARC_INS_FANDNOT2S,
+ SPARC_INS_FANDS,
+ SPARC_INS_FCHKSM16,
+ SPARC_INS_FCMPD,
+ SPARC_INS_FCMPEQ16,
+ SPARC_INS_FCMPEQ32,
+ SPARC_INS_FCMPGT16,
+ SPARC_INS_FCMPGT32,
+ SPARC_INS_FCMPLE16,
+ SPARC_INS_FCMPLE32,
+ SPARC_INS_FCMPNE16,
+ SPARC_INS_FCMPNE32,
+ SPARC_INS_FCMPQ,
+ SPARC_INS_FCMPS,
+ SPARC_INS_FDIVD,
+ SPARC_INS_FDIVQ,
+ SPARC_INS_FDIVS,
+ SPARC_INS_FDMULQ,
+ SPARC_INS_FDTOI,
+ SPARC_INS_FDTOQ,
+ SPARC_INS_FDTOS,
+ SPARC_INS_FDTOX,
+ SPARC_INS_FEXPAND,
+ SPARC_INS_FHADDD,
+ SPARC_INS_FHADDS,
+ SPARC_INS_FHSUBD,
+ SPARC_INS_FHSUBS,
+ SPARC_INS_FITOD,
+ SPARC_INS_FITOQ,
+ SPARC_INS_FITOS,
+ SPARC_INS_FLCMPD,
+ SPARC_INS_FLCMPS,
+ SPARC_INS_FLUSHW,
+ SPARC_INS_FMEAN16,
+ SPARC_INS_FMOVD,
+ SPARC_INS_FMOVQ,
+ SPARC_INS_FMOVRDGEZ,
+ SPARC_INS_FMOVRQGEZ,
+ SPARC_INS_FMOVRSGEZ,
+ SPARC_INS_FMOVRDGZ,
+ SPARC_INS_FMOVRQGZ,
+ SPARC_INS_FMOVRSGZ,
+ SPARC_INS_FMOVRDLEZ,
+ SPARC_INS_FMOVRQLEZ,
+ SPARC_INS_FMOVRSLEZ,
+ SPARC_INS_FMOVRDLZ,
+ SPARC_INS_FMOVRQLZ,
+ SPARC_INS_FMOVRSLZ,
+ SPARC_INS_FMOVRDNZ,
+ SPARC_INS_FMOVRQNZ,
+ SPARC_INS_FMOVRSNZ,
+ SPARC_INS_FMOVRDZ,
+ SPARC_INS_FMOVRQZ,
+ SPARC_INS_FMOVRSZ,
+ SPARC_INS_FMOVS,
+ SPARC_INS_FMUL8SUX16,
+ SPARC_INS_FMUL8ULX16,
+ SPARC_INS_FMUL8X16,
+ SPARC_INS_FMUL8X16AL,
+ SPARC_INS_FMUL8X16AU,
+ SPARC_INS_FMULD,
+ SPARC_INS_FMULD8SUX16,
+ SPARC_INS_FMULD8ULX16,
+ SPARC_INS_FMULQ,
+ SPARC_INS_FMULS,
+ SPARC_INS_FNADDD,
+ SPARC_INS_FNADDS,
+ SPARC_INS_FNAND,
+ SPARC_INS_FNANDS,
+ SPARC_INS_FNEGD,
+ SPARC_INS_FNEGQ,
+ SPARC_INS_FNEGS,
+ SPARC_INS_FNHADDD,
+ SPARC_INS_FNHADDS,
+ SPARC_INS_FNOR,
+ SPARC_INS_FNORS,
+ SPARC_INS_FNOT1,
+ SPARC_INS_FNOT1S,
+ SPARC_INS_FNOT2,
+ SPARC_INS_FNOT2S,
+ SPARC_INS_FONE,
+ SPARC_INS_FONES,
+ SPARC_INS_FOR,
+ SPARC_INS_FORNOT1,
+ SPARC_INS_FORNOT1S,
+ SPARC_INS_FORNOT2,
+ SPARC_INS_FORNOT2S,
+ SPARC_INS_FORS,
+ SPARC_INS_FPACK16,
+ SPARC_INS_FPACK32,
+ SPARC_INS_FPACKFIX,
+ SPARC_INS_FPADD16,
+ SPARC_INS_FPADD16S,
+ SPARC_INS_FPADD32,
+ SPARC_INS_FPADD32S,
+ SPARC_INS_FPADD64,
+ SPARC_INS_FPMERGE,
+ SPARC_INS_FPSUB16,
+ SPARC_INS_FPSUB16S,
+ SPARC_INS_FPSUB32,
+ SPARC_INS_FPSUB32S,
+ SPARC_INS_FQTOD,
+ SPARC_INS_FQTOI,
+ SPARC_INS_FQTOS,
+ SPARC_INS_FQTOX,
+ SPARC_INS_FSLAS16,
+ SPARC_INS_FSLAS32,
+ SPARC_INS_FSLL16,
+ SPARC_INS_FSLL32,
+ SPARC_INS_FSMULD,
+ SPARC_INS_FSQRTD,
+ SPARC_INS_FSQRTQ,
+ SPARC_INS_FSQRTS,
+ SPARC_INS_FSRA16,
+ SPARC_INS_FSRA32,
+ SPARC_INS_FSRC1,
+ SPARC_INS_FSRC1S,
+ SPARC_INS_FSRC2,
+ SPARC_INS_FSRC2S,
+ SPARC_INS_FSRL16,
+ SPARC_INS_FSRL32,
+ SPARC_INS_FSTOD,
+ SPARC_INS_FSTOI,
+ SPARC_INS_FSTOQ,
+ SPARC_INS_FSTOX,
+ SPARC_INS_FSUBD,
+ SPARC_INS_FSUBQ,
+ SPARC_INS_FSUBS,
+ SPARC_INS_FXNOR,
+ SPARC_INS_FXNORS,
+ SPARC_INS_FXOR,
+ SPARC_INS_FXORS,
+ SPARC_INS_FXTOD,
+ SPARC_INS_FXTOQ,
+ SPARC_INS_FXTOS,
+ SPARC_INS_FZERO,
+ SPARC_INS_FZEROS,
+ SPARC_INS_JMPL,
+ SPARC_INS_LDD,
+ SPARC_INS_LD,
+ SPARC_INS_LDQ,
+ SPARC_INS_LDSB,
+ SPARC_INS_LDSH,
+ SPARC_INS_LDSW,
+ SPARC_INS_LDUB,
+ SPARC_INS_LDUH,
+ SPARC_INS_LDX,
+ SPARC_INS_LZCNT,
+ SPARC_INS_MEMBAR,
+ SPARC_INS_MOVDTOX,
+ SPARC_INS_MOV,
+ SPARC_INS_MOVRGEZ,
+ SPARC_INS_MOVRGZ,
+ SPARC_INS_MOVRLEZ,
+ SPARC_INS_MOVRLZ,
+ SPARC_INS_MOVRNZ,
+ SPARC_INS_MOVRZ,
+ SPARC_INS_MOVSTOSW,
+ SPARC_INS_MOVSTOUW,
+ SPARC_INS_MULX,
+ SPARC_INS_NOP,
+ SPARC_INS_ORCC,
+ SPARC_INS_ORNCC,
+ SPARC_INS_ORN,
+ SPARC_INS_OR,
+ SPARC_INS_PDIST,
+ SPARC_INS_PDISTN,
+ SPARC_INS_POPC,
+ SPARC_INS_RD,
+ SPARC_INS_RESTORE,
+ SPARC_INS_RETT,
+ SPARC_INS_SAVE,
+ SPARC_INS_SDIVCC,
+ SPARC_INS_SDIVX,
+ SPARC_INS_SDIV,
+ SPARC_INS_SETHI,
+ SPARC_INS_SHUTDOWN,
+ SPARC_INS_SIAM,
+ SPARC_INS_SLLX,
+ SPARC_INS_SLL,
+ SPARC_INS_SMULCC,
+ SPARC_INS_SMUL,
+ SPARC_INS_SRAX,
+ SPARC_INS_SRA,
+ SPARC_INS_SRLX,
+ SPARC_INS_SRL,
+ SPARC_INS_STBAR,
+ SPARC_INS_STB,
+ SPARC_INS_STD,
+ SPARC_INS_ST,
+ SPARC_INS_STH,
+ SPARC_INS_STQ,
+ SPARC_INS_STX,
+ SPARC_INS_SUBCC,
+ SPARC_INS_SUBX,
+ SPARC_INS_SUBXCC,
+ SPARC_INS_SUB,
+ SPARC_INS_SWAP,
+ SPARC_INS_TADDCCTV,
+ SPARC_INS_TADDCC,
+ SPARC_INS_T,
+ SPARC_INS_TSUBCCTV,
+ SPARC_INS_TSUBCC,
+ SPARC_INS_UDIVCC,
+ SPARC_INS_UDIVX,
+ SPARC_INS_UDIV,
+ SPARC_INS_UMULCC,
+ SPARC_INS_UMULXHI,
+ SPARC_INS_UMUL,
+ SPARC_INS_UNIMP,
+ SPARC_INS_FCMPED,
+ SPARC_INS_FCMPEQ,
+ SPARC_INS_FCMPES,
+ SPARC_INS_WR,
+ SPARC_INS_XMULX,
+ SPARC_INS_XMULXHI,
+ SPARC_INS_XNORCC,
+ SPARC_INS_XNOR,
+ SPARC_INS_XORCC,
+ SPARC_INS_XOR,
+
+ // alias instructions
+ SPARC_INS_RET,
+ SPARC_INS_RETL,
+
+ SPARC_INS_ENDING, // <-- mark the end of the list of instructions
+} sparc_insn;
+
+/// Group of SPARC instructions
+typedef enum sparc_insn_group {
+ SPARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ SPARC_GRP_JUMP, ///< = CS_GRP_JUMP
+
+ // Architecture-specific groups
+ SPARC_GRP_HARDQUAD = 128,
+ SPARC_GRP_V9,
+ SPARC_GRP_VIS,
+ SPARC_GRP_VIS2,
+ SPARC_GRP_VIS3,
+ SPARC_GRP_32BIT,
+ SPARC_GRP_64BIT,
+
+ SPARC_GRP_ENDING, // <-- mark the end of the list of groups
+} sparc_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/systemz.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/systemz.h
new file mode 100644
index 00000000..aa9768cc
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/systemz.h
@@ -0,0 +1,830 @@
+#ifndef CAPSTONE_SYSTEMZ_H
+#define CAPSTONE_SYSTEMZ_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2014-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Enums corresponding to SystemZ condition codes
+typedef enum sysz_cc {
+ SYSZ_CC_INVALID = 0, ///< invalid CC (default)
+
+ SYSZ_CC_O,
+ SYSZ_CC_H,
+ SYSZ_CC_NLE,
+ SYSZ_CC_L,
+ SYSZ_CC_NHE,
+ SYSZ_CC_LH,
+ SYSZ_CC_NE,
+ SYSZ_CC_E,
+ SYSZ_CC_NLH,
+ SYSZ_CC_HE,
+ SYSZ_CC_NL,
+ SYSZ_CC_LE,
+ SYSZ_CC_NH,
+ SYSZ_CC_NO,
+} sysz_cc;
+
+/// Operand type for instruction's operands
+typedef enum sysz_op_type {
+ SYSZ_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ SYSZ_OP_REG, ///< = CS_OP_REG (Register operand).
+ SYSZ_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ SYSZ_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+ SYSZ_OP_ACREG = 64, ///< Access register operand.
+} sysz_op_type;
+
+/// SystemZ registers
+typedef enum sysz_reg {
+ SYSZ_REG_INVALID = 0,
+
+ SYSZ_REG_0,
+ SYSZ_REG_1,
+ SYSZ_REG_2,
+ SYSZ_REG_3,
+ SYSZ_REG_4,
+ SYSZ_REG_5,
+ SYSZ_REG_6,
+ SYSZ_REG_7,
+ SYSZ_REG_8,
+ SYSZ_REG_9,
+ SYSZ_REG_10,
+ SYSZ_REG_11,
+ SYSZ_REG_12,
+ SYSZ_REG_13,
+ SYSZ_REG_14,
+ SYSZ_REG_15,
+ SYSZ_REG_CC,
+ SYSZ_REG_F0,
+ SYSZ_REG_F1,
+ SYSZ_REG_F2,
+ SYSZ_REG_F3,
+ SYSZ_REG_F4,
+ SYSZ_REG_F5,
+ SYSZ_REG_F6,
+ SYSZ_REG_F7,
+ SYSZ_REG_F8,
+ SYSZ_REG_F9,
+ SYSZ_REG_F10,
+ SYSZ_REG_F11,
+ SYSZ_REG_F12,
+ SYSZ_REG_F13,
+ SYSZ_REG_F14,
+ SYSZ_REG_F15,
+
+ SYSZ_REG_R0L,
+
+ SYSZ_REG_ENDING,
+} sysz_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with SYSZ_OP_MEM operand type above
+typedef struct sysz_op_mem {
+ uint8_t base; ///< base register, can be safely interpreted as
+ ///< a value of type `sysz_reg`, but it is only
+ ///< one byte wide
+ uint8_t index; ///< index register, same conditions apply here
+ uint64_t length; ///< BDLAddr operand
+ int64_t disp; ///< displacement/offset value
+} sysz_op_mem;
+
+/// Instruction operand
+typedef struct cs_sysz_op {
+ sysz_op_type type; ///< operand type
+ union {
+ sysz_reg reg; ///< register value for REG operand
+ int64_t imm; ///< immediate value for IMM operand
+ sysz_op_mem mem; ///< base/disp value for MEM operand
+ };
+} cs_sysz_op;
+
+// Instruction structure
+typedef struct cs_sysz {
+ sysz_cc cc; ///< Code condition
+ /// Number of operands of this instruction,
+ /// or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_sysz_op operands[6]; ///< operands for this instruction.
+} cs_sysz;
+
+/// SystemZ instruction
+typedef enum sysz_insn {
+ SYSZ_INS_INVALID = 0,
+
+ SYSZ_INS_A,
+ SYSZ_INS_ADB,
+ SYSZ_INS_ADBR,
+ SYSZ_INS_AEB,
+ SYSZ_INS_AEBR,
+ SYSZ_INS_AFI,
+ SYSZ_INS_AG,
+ SYSZ_INS_AGF,
+ SYSZ_INS_AGFI,
+ SYSZ_INS_AGFR,
+ SYSZ_INS_AGHI,
+ SYSZ_INS_AGHIK,
+ SYSZ_INS_AGR,
+ SYSZ_INS_AGRK,
+ SYSZ_INS_AGSI,
+ SYSZ_INS_AH,
+ SYSZ_INS_AHI,
+ SYSZ_INS_AHIK,
+ SYSZ_INS_AHY,
+ SYSZ_INS_AIH,
+ SYSZ_INS_AL,
+ SYSZ_INS_ALC,
+ SYSZ_INS_ALCG,
+ SYSZ_INS_ALCGR,
+ SYSZ_INS_ALCR,
+ SYSZ_INS_ALFI,
+ SYSZ_INS_ALG,
+ SYSZ_INS_ALGF,
+ SYSZ_INS_ALGFI,
+ SYSZ_INS_ALGFR,
+ SYSZ_INS_ALGHSIK,
+ SYSZ_INS_ALGR,
+ SYSZ_INS_ALGRK,
+ SYSZ_INS_ALHSIK,
+ SYSZ_INS_ALR,
+ SYSZ_INS_ALRK,
+ SYSZ_INS_ALY,
+ SYSZ_INS_AR,
+ SYSZ_INS_ARK,
+ SYSZ_INS_ASI,
+ SYSZ_INS_AXBR,
+ SYSZ_INS_AY,
+ SYSZ_INS_BCR,
+ SYSZ_INS_BRC,
+ SYSZ_INS_BRCL,
+ SYSZ_INS_CGIJ,
+ SYSZ_INS_CGRJ,
+ SYSZ_INS_CIJ,
+ SYSZ_INS_CLGIJ,
+ SYSZ_INS_CLGRJ,
+ SYSZ_INS_CLIJ,
+ SYSZ_INS_CLRJ,
+ SYSZ_INS_CRJ,
+ SYSZ_INS_BER,
+ SYSZ_INS_JE,
+ SYSZ_INS_JGE,
+ SYSZ_INS_LOCE,
+ SYSZ_INS_LOCGE,
+ SYSZ_INS_LOCGRE,
+ SYSZ_INS_LOCRE,
+ SYSZ_INS_STOCE,
+ SYSZ_INS_STOCGE,
+ SYSZ_INS_BHR,
+ SYSZ_INS_BHER,
+ SYSZ_INS_JHE,
+ SYSZ_INS_JGHE,
+ SYSZ_INS_LOCHE,
+ SYSZ_INS_LOCGHE,
+ SYSZ_INS_LOCGRHE,
+ SYSZ_INS_LOCRHE,
+ SYSZ_INS_STOCHE,
+ SYSZ_INS_STOCGHE,
+ SYSZ_INS_JH,
+ SYSZ_INS_JGH,
+ SYSZ_INS_LOCH,
+ SYSZ_INS_LOCGH,
+ SYSZ_INS_LOCGRH,
+ SYSZ_INS_LOCRH,
+ SYSZ_INS_STOCH,
+ SYSZ_INS_STOCGH,
+ SYSZ_INS_CGIJNLH,
+ SYSZ_INS_CGRJNLH,
+ SYSZ_INS_CIJNLH,
+ SYSZ_INS_CLGIJNLH,
+ SYSZ_INS_CLGRJNLH,
+ SYSZ_INS_CLIJNLH,
+ SYSZ_INS_CLRJNLH,
+ SYSZ_INS_CRJNLH,
+ SYSZ_INS_CGIJE,
+ SYSZ_INS_CGRJE,
+ SYSZ_INS_CIJE,
+ SYSZ_INS_CLGIJE,
+ SYSZ_INS_CLGRJE,
+ SYSZ_INS_CLIJE,
+ SYSZ_INS_CLRJE,
+ SYSZ_INS_CRJE,
+ SYSZ_INS_CGIJNLE,
+ SYSZ_INS_CGRJNLE,
+ SYSZ_INS_CIJNLE,
+ SYSZ_INS_CLGIJNLE,
+ SYSZ_INS_CLGRJNLE,
+ SYSZ_INS_CLIJNLE,
+ SYSZ_INS_CLRJNLE,
+ SYSZ_INS_CRJNLE,
+ SYSZ_INS_CGIJH,
+ SYSZ_INS_CGRJH,
+ SYSZ_INS_CIJH,
+ SYSZ_INS_CLGIJH,
+ SYSZ_INS_CLGRJH,
+ SYSZ_INS_CLIJH,
+ SYSZ_INS_CLRJH,
+ SYSZ_INS_CRJH,
+ SYSZ_INS_CGIJNL,
+ SYSZ_INS_CGRJNL,
+ SYSZ_INS_CIJNL,
+ SYSZ_INS_CLGIJNL,
+ SYSZ_INS_CLGRJNL,
+ SYSZ_INS_CLIJNL,
+ SYSZ_INS_CLRJNL,
+ SYSZ_INS_CRJNL,
+ SYSZ_INS_CGIJHE,
+ SYSZ_INS_CGRJHE,
+ SYSZ_INS_CIJHE,
+ SYSZ_INS_CLGIJHE,
+ SYSZ_INS_CLGRJHE,
+ SYSZ_INS_CLIJHE,
+ SYSZ_INS_CLRJHE,
+ SYSZ_INS_CRJHE,
+ SYSZ_INS_CGIJNHE,
+ SYSZ_INS_CGRJNHE,
+ SYSZ_INS_CIJNHE,
+ SYSZ_INS_CLGIJNHE,
+ SYSZ_INS_CLGRJNHE,
+ SYSZ_INS_CLIJNHE,
+ SYSZ_INS_CLRJNHE,
+ SYSZ_INS_CRJNHE,
+ SYSZ_INS_CGIJL,
+ SYSZ_INS_CGRJL,
+ SYSZ_INS_CIJL,
+ SYSZ_INS_CLGIJL,
+ SYSZ_INS_CLGRJL,
+ SYSZ_INS_CLIJL,
+ SYSZ_INS_CLRJL,
+ SYSZ_INS_CRJL,
+ SYSZ_INS_CGIJNH,
+ SYSZ_INS_CGRJNH,
+ SYSZ_INS_CIJNH,
+ SYSZ_INS_CLGIJNH,
+ SYSZ_INS_CLGRJNH,
+ SYSZ_INS_CLIJNH,
+ SYSZ_INS_CLRJNH,
+ SYSZ_INS_CRJNH,
+ SYSZ_INS_CGIJLE,
+ SYSZ_INS_CGRJLE,
+ SYSZ_INS_CIJLE,
+ SYSZ_INS_CLGIJLE,
+ SYSZ_INS_CLGRJLE,
+ SYSZ_INS_CLIJLE,
+ SYSZ_INS_CLRJLE,
+ SYSZ_INS_CRJLE,
+ SYSZ_INS_CGIJNE,
+ SYSZ_INS_CGRJNE,
+ SYSZ_INS_CIJNE,
+ SYSZ_INS_CLGIJNE,
+ SYSZ_INS_CLGRJNE,
+ SYSZ_INS_CLIJNE,
+ SYSZ_INS_CLRJNE,
+ SYSZ_INS_CRJNE,
+ SYSZ_INS_CGIJLH,
+ SYSZ_INS_CGRJLH,
+ SYSZ_INS_CIJLH,
+ SYSZ_INS_CLGIJLH,
+ SYSZ_INS_CLGRJLH,
+ SYSZ_INS_CLIJLH,
+ SYSZ_INS_CLRJLH,
+ SYSZ_INS_CRJLH,
+ SYSZ_INS_BLR,
+ SYSZ_INS_BLER,
+ SYSZ_INS_JLE,
+ SYSZ_INS_JGLE,
+ SYSZ_INS_LOCLE,
+ SYSZ_INS_LOCGLE,
+ SYSZ_INS_LOCGRLE,
+ SYSZ_INS_LOCRLE,
+ SYSZ_INS_STOCLE,
+ SYSZ_INS_STOCGLE,
+ SYSZ_INS_BLHR,
+ SYSZ_INS_JLH,
+ SYSZ_INS_JGLH,
+ SYSZ_INS_LOCLH,
+ SYSZ_INS_LOCGLH,
+ SYSZ_INS_LOCGRLH,
+ SYSZ_INS_LOCRLH,
+ SYSZ_INS_STOCLH,
+ SYSZ_INS_STOCGLH,
+ SYSZ_INS_JL,
+ SYSZ_INS_JGL,
+ SYSZ_INS_LOCL,
+ SYSZ_INS_LOCGL,
+ SYSZ_INS_LOCGRL,
+ SYSZ_INS_LOCRL,
+ SYSZ_INS_LOC,
+ SYSZ_INS_LOCG,
+ SYSZ_INS_LOCGR,
+ SYSZ_INS_LOCR,
+ SYSZ_INS_STOCL,
+ SYSZ_INS_STOCGL,
+ SYSZ_INS_BNER,
+ SYSZ_INS_JNE,
+ SYSZ_INS_JGNE,
+ SYSZ_INS_LOCNE,
+ SYSZ_INS_LOCGNE,
+ SYSZ_INS_LOCGRNE,
+ SYSZ_INS_LOCRNE,
+ SYSZ_INS_STOCNE,
+ SYSZ_INS_STOCGNE,
+ SYSZ_INS_BNHR,
+ SYSZ_INS_BNHER,
+ SYSZ_INS_JNHE,
+ SYSZ_INS_JGNHE,
+ SYSZ_INS_LOCNHE,
+ SYSZ_INS_LOCGNHE,
+ SYSZ_INS_LOCGRNHE,
+ SYSZ_INS_LOCRNHE,
+ SYSZ_INS_STOCNHE,
+ SYSZ_INS_STOCGNHE,
+ SYSZ_INS_JNH,
+ SYSZ_INS_JGNH,
+ SYSZ_INS_LOCNH,
+ SYSZ_INS_LOCGNH,
+ SYSZ_INS_LOCGRNH,
+ SYSZ_INS_LOCRNH,
+ SYSZ_INS_STOCNH,
+ SYSZ_INS_STOCGNH,
+ SYSZ_INS_BNLR,
+ SYSZ_INS_BNLER,
+ SYSZ_INS_JNLE,
+ SYSZ_INS_JGNLE,
+ SYSZ_INS_LOCNLE,
+ SYSZ_INS_LOCGNLE,
+ SYSZ_INS_LOCGRNLE,
+ SYSZ_INS_LOCRNLE,
+ SYSZ_INS_STOCNLE,
+ SYSZ_INS_STOCGNLE,
+ SYSZ_INS_BNLHR,
+ SYSZ_INS_JNLH,
+ SYSZ_INS_JGNLH,
+ SYSZ_INS_LOCNLH,
+ SYSZ_INS_LOCGNLH,
+ SYSZ_INS_LOCGRNLH,
+ SYSZ_INS_LOCRNLH,
+ SYSZ_INS_STOCNLH,
+ SYSZ_INS_STOCGNLH,
+ SYSZ_INS_JNL,
+ SYSZ_INS_JGNL,
+ SYSZ_INS_LOCNL,
+ SYSZ_INS_LOCGNL,
+ SYSZ_INS_LOCGRNL,
+ SYSZ_INS_LOCRNL,
+ SYSZ_INS_STOCNL,
+ SYSZ_INS_STOCGNL,
+ SYSZ_INS_BNOR,
+ SYSZ_INS_JNO,
+ SYSZ_INS_JGNO,
+ SYSZ_INS_LOCNO,
+ SYSZ_INS_LOCGNO,
+ SYSZ_INS_LOCGRNO,
+ SYSZ_INS_LOCRNO,
+ SYSZ_INS_STOCNO,
+ SYSZ_INS_STOCGNO,
+ SYSZ_INS_BOR,
+ SYSZ_INS_JO,
+ SYSZ_INS_JGO,
+ SYSZ_INS_LOCO,
+ SYSZ_INS_LOCGO,
+ SYSZ_INS_LOCGRO,
+ SYSZ_INS_LOCRO,
+ SYSZ_INS_STOCO,
+ SYSZ_INS_STOCGO,
+ SYSZ_INS_STOC,
+ SYSZ_INS_STOCG,
+ SYSZ_INS_BASR,
+ SYSZ_INS_BR,
+ SYSZ_INS_BRAS,
+ SYSZ_INS_BRASL,
+ SYSZ_INS_J,
+ SYSZ_INS_JG,
+ SYSZ_INS_BRCT,
+ SYSZ_INS_BRCTG,
+ SYSZ_INS_C,
+ SYSZ_INS_CDB,
+ SYSZ_INS_CDBR,
+ SYSZ_INS_CDFBR,
+ SYSZ_INS_CDGBR,
+ SYSZ_INS_CDLFBR,
+ SYSZ_INS_CDLGBR,
+ SYSZ_INS_CEB,
+ SYSZ_INS_CEBR,
+ SYSZ_INS_CEFBR,
+ SYSZ_INS_CEGBR,
+ SYSZ_INS_CELFBR,
+ SYSZ_INS_CELGBR,
+ SYSZ_INS_CFDBR,
+ SYSZ_INS_CFEBR,
+ SYSZ_INS_CFI,
+ SYSZ_INS_CFXBR,
+ SYSZ_INS_CG,
+ SYSZ_INS_CGDBR,
+ SYSZ_INS_CGEBR,
+ SYSZ_INS_CGF,
+ SYSZ_INS_CGFI,
+ SYSZ_INS_CGFR,
+ SYSZ_INS_CGFRL,
+ SYSZ_INS_CGH,
+ SYSZ_INS_CGHI,
+ SYSZ_INS_CGHRL,
+ SYSZ_INS_CGHSI,
+ SYSZ_INS_CGR,
+ SYSZ_INS_CGRL,
+ SYSZ_INS_CGXBR,
+ SYSZ_INS_CH,
+ SYSZ_INS_CHF,
+ SYSZ_INS_CHHSI,
+ SYSZ_INS_CHI,
+ SYSZ_INS_CHRL,
+ SYSZ_INS_CHSI,
+ SYSZ_INS_CHY,
+ SYSZ_INS_CIH,
+ SYSZ_INS_CL,
+ SYSZ_INS_CLC,
+ SYSZ_INS_CLFDBR,
+ SYSZ_INS_CLFEBR,
+ SYSZ_INS_CLFHSI,
+ SYSZ_INS_CLFI,
+ SYSZ_INS_CLFXBR,
+ SYSZ_INS_CLG,
+ SYSZ_INS_CLGDBR,
+ SYSZ_INS_CLGEBR,
+ SYSZ_INS_CLGF,
+ SYSZ_INS_CLGFI,
+ SYSZ_INS_CLGFR,
+ SYSZ_INS_CLGFRL,
+ SYSZ_INS_CLGHRL,
+ SYSZ_INS_CLGHSI,
+ SYSZ_INS_CLGR,
+ SYSZ_INS_CLGRL,
+ SYSZ_INS_CLGXBR,
+ SYSZ_INS_CLHF,
+ SYSZ_INS_CLHHSI,
+ SYSZ_INS_CLHRL,
+ SYSZ_INS_CLI,
+ SYSZ_INS_CLIH,
+ SYSZ_INS_CLIY,
+ SYSZ_INS_CLR,
+ SYSZ_INS_CLRL,
+ SYSZ_INS_CLST,
+ SYSZ_INS_CLY,
+ SYSZ_INS_CPSDR,
+ SYSZ_INS_CR,
+ SYSZ_INS_CRL,
+ SYSZ_INS_CS,
+ SYSZ_INS_CSG,
+ SYSZ_INS_CSY,
+ SYSZ_INS_CXBR,
+ SYSZ_INS_CXFBR,
+ SYSZ_INS_CXGBR,
+ SYSZ_INS_CXLFBR,
+ SYSZ_INS_CXLGBR,
+ SYSZ_INS_CY,
+ SYSZ_INS_DDB,
+ SYSZ_INS_DDBR,
+ SYSZ_INS_DEB,
+ SYSZ_INS_DEBR,
+ SYSZ_INS_DL,
+ SYSZ_INS_DLG,
+ SYSZ_INS_DLGR,
+ SYSZ_INS_DLR,
+ SYSZ_INS_DSG,
+ SYSZ_INS_DSGF,
+ SYSZ_INS_DSGFR,
+ SYSZ_INS_DSGR,
+ SYSZ_INS_DXBR,
+ SYSZ_INS_EAR,
+ SYSZ_INS_FIDBR,
+ SYSZ_INS_FIDBRA,
+ SYSZ_INS_FIEBR,
+ SYSZ_INS_FIEBRA,
+ SYSZ_INS_FIXBR,
+ SYSZ_INS_FIXBRA,
+ SYSZ_INS_FLOGR,
+ SYSZ_INS_IC,
+ SYSZ_INS_ICY,
+ SYSZ_INS_IIHF,
+ SYSZ_INS_IIHH,
+ SYSZ_INS_IIHL,
+ SYSZ_INS_IILF,
+ SYSZ_INS_IILH,
+ SYSZ_INS_IILL,
+ SYSZ_INS_IPM,
+ SYSZ_INS_L,
+ SYSZ_INS_LA,
+ SYSZ_INS_LAA,
+ SYSZ_INS_LAAG,
+ SYSZ_INS_LAAL,
+ SYSZ_INS_LAALG,
+ SYSZ_INS_LAN,
+ SYSZ_INS_LANG,
+ SYSZ_INS_LAO,
+ SYSZ_INS_LAOG,
+ SYSZ_INS_LARL,
+ SYSZ_INS_LAX,
+ SYSZ_INS_LAXG,
+ SYSZ_INS_LAY,
+ SYSZ_INS_LB,
+ SYSZ_INS_LBH,
+ SYSZ_INS_LBR,
+ SYSZ_INS_LCDBR,
+ SYSZ_INS_LCEBR,
+ SYSZ_INS_LCGFR,
+ SYSZ_INS_LCGR,
+ SYSZ_INS_LCR,
+ SYSZ_INS_LCXBR,
+ SYSZ_INS_LD,
+ SYSZ_INS_LDEB,
+ SYSZ_INS_LDEBR,
+ SYSZ_INS_LDGR,
+ SYSZ_INS_LDR,
+ SYSZ_INS_LDXBR,
+ SYSZ_INS_LDXBRA,
+ SYSZ_INS_LDY,
+ SYSZ_INS_LE,
+ SYSZ_INS_LEDBR,
+ SYSZ_INS_LEDBRA,
+ SYSZ_INS_LER,
+ SYSZ_INS_LEXBR,
+ SYSZ_INS_LEXBRA,
+ SYSZ_INS_LEY,
+ SYSZ_INS_LFH,
+ SYSZ_INS_LG,
+ SYSZ_INS_LGB,
+ SYSZ_INS_LGBR,
+ SYSZ_INS_LGDR,
+ SYSZ_INS_LGF,
+ SYSZ_INS_LGFI,
+ SYSZ_INS_LGFR,
+ SYSZ_INS_LGFRL,
+ SYSZ_INS_LGH,
+ SYSZ_INS_LGHI,
+ SYSZ_INS_LGHR,
+ SYSZ_INS_LGHRL,
+ SYSZ_INS_LGR,
+ SYSZ_INS_LGRL,
+ SYSZ_INS_LH,
+ SYSZ_INS_LHH,
+ SYSZ_INS_LHI,
+ SYSZ_INS_LHR,
+ SYSZ_INS_LHRL,
+ SYSZ_INS_LHY,
+ SYSZ_INS_LLC,
+ SYSZ_INS_LLCH,
+ SYSZ_INS_LLCR,
+ SYSZ_INS_LLGC,
+ SYSZ_INS_LLGCR,
+ SYSZ_INS_LLGF,
+ SYSZ_INS_LLGFR,
+ SYSZ_INS_LLGFRL,
+ SYSZ_INS_LLGH,
+ SYSZ_INS_LLGHR,
+ SYSZ_INS_LLGHRL,
+ SYSZ_INS_LLH,
+ SYSZ_INS_LLHH,
+ SYSZ_INS_LLHR,
+ SYSZ_INS_LLHRL,
+ SYSZ_INS_LLIHF,
+ SYSZ_INS_LLIHH,
+ SYSZ_INS_LLIHL,
+ SYSZ_INS_LLILF,
+ SYSZ_INS_LLILH,
+ SYSZ_INS_LLILL,
+ SYSZ_INS_LMG,
+ SYSZ_INS_LNDBR,
+ SYSZ_INS_LNEBR,
+ SYSZ_INS_LNGFR,
+ SYSZ_INS_LNGR,
+ SYSZ_INS_LNR,
+ SYSZ_INS_LNXBR,
+ SYSZ_INS_LPDBR,
+ SYSZ_INS_LPEBR,
+ SYSZ_INS_LPGFR,
+ SYSZ_INS_LPGR,
+ SYSZ_INS_LPR,
+ SYSZ_INS_LPXBR,
+ SYSZ_INS_LR,
+ SYSZ_INS_LRL,
+ SYSZ_INS_LRV,
+ SYSZ_INS_LRVG,
+ SYSZ_INS_LRVGR,
+ SYSZ_INS_LRVR,
+ SYSZ_INS_LT,
+ SYSZ_INS_LTDBR,
+ SYSZ_INS_LTEBR,
+ SYSZ_INS_LTG,
+ SYSZ_INS_LTGF,
+ SYSZ_INS_LTGFR,
+ SYSZ_INS_LTGR,
+ SYSZ_INS_LTR,
+ SYSZ_INS_LTXBR,
+ SYSZ_INS_LXDB,
+ SYSZ_INS_LXDBR,
+ SYSZ_INS_LXEB,
+ SYSZ_INS_LXEBR,
+ SYSZ_INS_LXR,
+ SYSZ_INS_LY,
+ SYSZ_INS_LZDR,
+ SYSZ_INS_LZER,
+ SYSZ_INS_LZXR,
+ SYSZ_INS_MADB,
+ SYSZ_INS_MADBR,
+ SYSZ_INS_MAEB,
+ SYSZ_INS_MAEBR,
+ SYSZ_INS_MDB,
+ SYSZ_INS_MDBR,
+ SYSZ_INS_MDEB,
+ SYSZ_INS_MDEBR,
+ SYSZ_INS_MEEB,
+ SYSZ_INS_MEEBR,
+ SYSZ_INS_MGHI,
+ SYSZ_INS_MH,
+ SYSZ_INS_MHI,
+ SYSZ_INS_MHY,
+ SYSZ_INS_MLG,
+ SYSZ_INS_MLGR,
+ SYSZ_INS_MS,
+ SYSZ_INS_MSDB,
+ SYSZ_INS_MSDBR,
+ SYSZ_INS_MSEB,
+ SYSZ_INS_MSEBR,
+ SYSZ_INS_MSFI,
+ SYSZ_INS_MSG,
+ SYSZ_INS_MSGF,
+ SYSZ_INS_MSGFI,
+ SYSZ_INS_MSGFR,
+ SYSZ_INS_MSGR,
+ SYSZ_INS_MSR,
+ SYSZ_INS_MSY,
+ SYSZ_INS_MVC,
+ SYSZ_INS_MVGHI,
+ SYSZ_INS_MVHHI,
+ SYSZ_INS_MVHI,
+ SYSZ_INS_MVI,
+ SYSZ_INS_MVIY,
+ SYSZ_INS_MVST,
+ SYSZ_INS_MXBR,
+ SYSZ_INS_MXDB,
+ SYSZ_INS_MXDBR,
+ SYSZ_INS_N,
+ SYSZ_INS_NC,
+ SYSZ_INS_NG,
+ SYSZ_INS_NGR,
+ SYSZ_INS_NGRK,
+ SYSZ_INS_NI,
+ SYSZ_INS_NIHF,
+ SYSZ_INS_NIHH,
+ SYSZ_INS_NIHL,
+ SYSZ_INS_NILF,
+ SYSZ_INS_NILH,
+ SYSZ_INS_NILL,
+ SYSZ_INS_NIY,
+ SYSZ_INS_NR,
+ SYSZ_INS_NRK,
+ SYSZ_INS_NY,
+ SYSZ_INS_O,
+ SYSZ_INS_OC,
+ SYSZ_INS_OG,
+ SYSZ_INS_OGR,
+ SYSZ_INS_OGRK,
+ SYSZ_INS_OI,
+ SYSZ_INS_OIHF,
+ SYSZ_INS_OIHH,
+ SYSZ_INS_OIHL,
+ SYSZ_INS_OILF,
+ SYSZ_INS_OILH,
+ SYSZ_INS_OILL,
+ SYSZ_INS_OIY,
+ SYSZ_INS_OR,
+ SYSZ_INS_ORK,
+ SYSZ_INS_OY,
+ SYSZ_INS_PFD,
+ SYSZ_INS_PFDRL,
+ SYSZ_INS_RISBG,
+ SYSZ_INS_RISBHG,
+ SYSZ_INS_RISBLG,
+ SYSZ_INS_RLL,
+ SYSZ_INS_RLLG,
+ SYSZ_INS_RNSBG,
+ SYSZ_INS_ROSBG,
+ SYSZ_INS_RXSBG,
+ SYSZ_INS_S,
+ SYSZ_INS_SDB,
+ SYSZ_INS_SDBR,
+ SYSZ_INS_SEB,
+ SYSZ_INS_SEBR,
+ SYSZ_INS_SG,
+ SYSZ_INS_SGF,
+ SYSZ_INS_SGFR,
+ SYSZ_INS_SGR,
+ SYSZ_INS_SGRK,
+ SYSZ_INS_SH,
+ SYSZ_INS_SHY,
+ SYSZ_INS_SL,
+ SYSZ_INS_SLB,
+ SYSZ_INS_SLBG,
+ SYSZ_INS_SLBR,
+ SYSZ_INS_SLFI,
+ SYSZ_INS_SLG,
+ SYSZ_INS_SLBGR,
+ SYSZ_INS_SLGF,
+ SYSZ_INS_SLGFI,
+ SYSZ_INS_SLGFR,
+ SYSZ_INS_SLGR,
+ SYSZ_INS_SLGRK,
+ SYSZ_INS_SLL,
+ SYSZ_INS_SLLG,
+ SYSZ_INS_SLLK,
+ SYSZ_INS_SLR,
+ SYSZ_INS_SLRK,
+ SYSZ_INS_SLY,
+ SYSZ_INS_SQDB,
+ SYSZ_INS_SQDBR,
+ SYSZ_INS_SQEB,
+ SYSZ_INS_SQEBR,
+ SYSZ_INS_SQXBR,
+ SYSZ_INS_SR,
+ SYSZ_INS_SRA,
+ SYSZ_INS_SRAG,
+ SYSZ_INS_SRAK,
+ SYSZ_INS_SRK,
+ SYSZ_INS_SRL,
+ SYSZ_INS_SRLG,
+ SYSZ_INS_SRLK,
+ SYSZ_INS_SRST,
+ SYSZ_INS_ST,
+ SYSZ_INS_STC,
+ SYSZ_INS_STCH,
+ SYSZ_INS_STCY,
+ SYSZ_INS_STD,
+ SYSZ_INS_STDY,
+ SYSZ_INS_STE,
+ SYSZ_INS_STEY,
+ SYSZ_INS_STFH,
+ SYSZ_INS_STG,
+ SYSZ_INS_STGRL,
+ SYSZ_INS_STH,
+ SYSZ_INS_STHH,
+ SYSZ_INS_STHRL,
+ SYSZ_INS_STHY,
+ SYSZ_INS_STMG,
+ SYSZ_INS_STRL,
+ SYSZ_INS_STRV,
+ SYSZ_INS_STRVG,
+ SYSZ_INS_STY,
+ SYSZ_INS_SXBR,
+ SYSZ_INS_SY,
+ SYSZ_INS_TM,
+ SYSZ_INS_TMHH,
+ SYSZ_INS_TMHL,
+ SYSZ_INS_TMLH,
+ SYSZ_INS_TMLL,
+ SYSZ_INS_TMY,
+ SYSZ_INS_X,
+ SYSZ_INS_XC,
+ SYSZ_INS_XG,
+ SYSZ_INS_XGR,
+ SYSZ_INS_XGRK,
+ SYSZ_INS_XI,
+ SYSZ_INS_XIHF,
+ SYSZ_INS_XILF,
+ SYSZ_INS_XIY,
+ SYSZ_INS_XR,
+ SYSZ_INS_XRK,
+ SYSZ_INS_XY,
+
+ SYSZ_INS_ENDING, // <-- mark the end of the list of instructions
+} sysz_insn;
+
+/// Group of SystemZ instructions
+typedef enum sysz_insn_group {
+ SYSZ_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ SYSZ_GRP_JUMP, ///< = CS_GRP_JUMP
+
+ // Architecture-specific groups
+ SYSZ_GRP_DISTINCTOPS = 128,
+ SYSZ_GRP_FPEXTENSION,
+ SYSZ_GRP_HIGHWORD,
+ SYSZ_GRP_INTERLOCKEDACCESS1,
+ SYSZ_GRP_LOADSTOREONCOND,
+
+ SYSZ_GRP_ENDING, // <-- mark the end of the list of groups
+} sysz_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/tms320c64x.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/tms320c64x.h
new file mode 100644
index 00000000..5e7f1b3b
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/tms320c64x.h
@@ -0,0 +1,359 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos 2016 */
+
+#ifndef CAPSTONE_TMS320C64X_H
+#define CAPSTONE_TMS320C64X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+typedef enum tms320c64x_op_type {
+ TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand).
+ TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+ TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops
+} tms320c64x_op_type;
+
+typedef enum tms320c64x_mem_disp {
+ TMS320C64X_MEM_DISP_INVALID = 0,
+ TMS320C64X_MEM_DISP_CONSTANT,
+ TMS320C64X_MEM_DISP_REGISTER,
+} tms320c64x_mem_disp;
+
+typedef enum tms320c64x_mem_dir {
+ TMS320C64X_MEM_DIR_INVALID = 0,
+ TMS320C64X_MEM_DIR_FW,
+ TMS320C64X_MEM_DIR_BW,
+} tms320c64x_mem_dir;
+
+typedef enum tms320c64x_mem_mod {
+ TMS320C64X_MEM_MOD_INVALID = 0,
+ TMS320C64X_MEM_MOD_NO,
+ TMS320C64X_MEM_MOD_PRE,
+ TMS320C64X_MEM_MOD_POST,
+} tms320c64x_mem_mod;
+
+typedef struct tms320c64x_op_mem {
+ unsigned int base; ///< base register
+ unsigned int disp; ///< displacement/offset value
+ unsigned int unit; ///< unit of base and offset register
+ unsigned int scaled; ///< offset scaled
+ unsigned int disptype; ///< displacement type
+ unsigned int direction; ///< direction
+ unsigned int modify; ///< modification
+} tms320c64x_op_mem;
+
+typedef struct cs_tms320c64x_op {
+ tms320c64x_op_type type; ///< operand type
+ union {
+ unsigned int reg; ///< register value for REG operand or first register for REGPAIR operand
+ int32_t imm; ///< immediate value for IMM operand
+ tms320c64x_op_mem mem; ///< base/disp value for MEM operand
+ };
+} cs_tms320c64x_op;
+
+typedef struct cs_tms320c64x {
+ uint8_t op_count;
+ cs_tms320c64x_op operands[8]; ///< operands for this instruction.
+ struct {
+ unsigned int reg;
+ unsigned int zero;
+ } condition;
+ struct {
+ unsigned int unit;
+ unsigned int side;
+ unsigned int crosspath;
+ } funit;
+ unsigned int parallel;
+} cs_tms320c64x;
+
+typedef enum tms320c64x_reg {
+ TMS320C64X_REG_INVALID = 0,
+
+ TMS320C64X_REG_AMR,
+ TMS320C64X_REG_CSR,
+ TMS320C64X_REG_DIER,
+ TMS320C64X_REG_DNUM,
+ TMS320C64X_REG_ECR,
+ TMS320C64X_REG_GFPGFR,
+ TMS320C64X_REG_GPLYA,
+ TMS320C64X_REG_GPLYB,
+ TMS320C64X_REG_ICR,
+ TMS320C64X_REG_IER,
+ TMS320C64X_REG_IERR,
+ TMS320C64X_REG_ILC,
+ TMS320C64X_REG_IRP,
+ TMS320C64X_REG_ISR,
+ TMS320C64X_REG_ISTP,
+ TMS320C64X_REG_ITSR,
+ TMS320C64X_REG_NRP,
+ TMS320C64X_REG_NTSR,
+ TMS320C64X_REG_REP,
+ TMS320C64X_REG_RILC,
+ TMS320C64X_REG_SSR,
+ TMS320C64X_REG_TSCH,
+ TMS320C64X_REG_TSCL,
+ TMS320C64X_REG_TSR,
+ TMS320C64X_REG_A0,
+ TMS320C64X_REG_A1,
+ TMS320C64X_REG_A2,
+ TMS320C64X_REG_A3,
+ TMS320C64X_REG_A4,
+ TMS320C64X_REG_A5,
+ TMS320C64X_REG_A6,
+ TMS320C64X_REG_A7,
+ TMS320C64X_REG_A8,
+ TMS320C64X_REG_A9,
+ TMS320C64X_REG_A10,
+ TMS320C64X_REG_A11,
+ TMS320C64X_REG_A12,
+ TMS320C64X_REG_A13,
+ TMS320C64X_REG_A14,
+ TMS320C64X_REG_A15,
+ TMS320C64X_REG_A16,
+ TMS320C64X_REG_A17,
+ TMS320C64X_REG_A18,
+ TMS320C64X_REG_A19,
+ TMS320C64X_REG_A20,
+ TMS320C64X_REG_A21,
+ TMS320C64X_REG_A22,
+ TMS320C64X_REG_A23,
+ TMS320C64X_REG_A24,
+ TMS320C64X_REG_A25,
+ TMS320C64X_REG_A26,
+ TMS320C64X_REG_A27,
+ TMS320C64X_REG_A28,
+ TMS320C64X_REG_A29,
+ TMS320C64X_REG_A30,
+ TMS320C64X_REG_A31,
+ TMS320C64X_REG_B0,
+ TMS320C64X_REG_B1,
+ TMS320C64X_REG_B2,
+ TMS320C64X_REG_B3,
+ TMS320C64X_REG_B4,
+ TMS320C64X_REG_B5,
+ TMS320C64X_REG_B6,
+ TMS320C64X_REG_B7,
+ TMS320C64X_REG_B8,
+ TMS320C64X_REG_B9,
+ TMS320C64X_REG_B10,
+ TMS320C64X_REG_B11,
+ TMS320C64X_REG_B12,
+ TMS320C64X_REG_B13,
+ TMS320C64X_REG_B14,
+ TMS320C64X_REG_B15,
+ TMS320C64X_REG_B16,
+ TMS320C64X_REG_B17,
+ TMS320C64X_REG_B18,
+ TMS320C64X_REG_B19,
+ TMS320C64X_REG_B20,
+ TMS320C64X_REG_B21,
+ TMS320C64X_REG_B22,
+ TMS320C64X_REG_B23,
+ TMS320C64X_REG_B24,
+ TMS320C64X_REG_B25,
+ TMS320C64X_REG_B26,
+ TMS320C64X_REG_B27,
+ TMS320C64X_REG_B28,
+ TMS320C64X_REG_B29,
+ TMS320C64X_REG_B30,
+ TMS320C64X_REG_B31,
+ TMS320C64X_REG_PCE1,
+
+ TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers
+
+ // Alias registers
+ TMS320C64X_REG_EFR = TMS320C64X_REG_ECR,
+ TMS320C64X_REG_IFR = TMS320C64X_REG_ISR,
+} tms320c64x_reg;
+
+typedef enum tms320c64x_insn {
+ TMS320C64X_INS_INVALID = 0,
+
+ TMS320C64X_INS_ABS,
+ TMS320C64X_INS_ABS2,
+ TMS320C64X_INS_ADD,
+ TMS320C64X_INS_ADD2,
+ TMS320C64X_INS_ADD4,
+ TMS320C64X_INS_ADDAB,
+ TMS320C64X_INS_ADDAD,
+ TMS320C64X_INS_ADDAH,
+ TMS320C64X_INS_ADDAW,
+ TMS320C64X_INS_ADDK,
+ TMS320C64X_INS_ADDKPC,
+ TMS320C64X_INS_ADDU,
+ TMS320C64X_INS_AND,
+ TMS320C64X_INS_ANDN,
+ TMS320C64X_INS_AVG2,
+ TMS320C64X_INS_AVGU4,
+ TMS320C64X_INS_B,
+ TMS320C64X_INS_BDEC,
+ TMS320C64X_INS_BITC4,
+ TMS320C64X_INS_BNOP,
+ TMS320C64X_INS_BPOS,
+ TMS320C64X_INS_CLR,
+ TMS320C64X_INS_CMPEQ,
+ TMS320C64X_INS_CMPEQ2,
+ TMS320C64X_INS_CMPEQ4,
+ TMS320C64X_INS_CMPGT,
+ TMS320C64X_INS_CMPGT2,
+ TMS320C64X_INS_CMPGTU4,
+ TMS320C64X_INS_CMPLT,
+ TMS320C64X_INS_CMPLTU,
+ TMS320C64X_INS_DEAL,
+ TMS320C64X_INS_DOTP2,
+ TMS320C64X_INS_DOTPN2,
+ TMS320C64X_INS_DOTPNRSU2,
+ TMS320C64X_INS_DOTPRSU2,
+ TMS320C64X_INS_DOTPSU4,
+ TMS320C64X_INS_DOTPU4,
+ TMS320C64X_INS_EXT,
+ TMS320C64X_INS_EXTU,
+ TMS320C64X_INS_GMPGTU,
+ TMS320C64X_INS_GMPY4,
+ TMS320C64X_INS_LDB,
+ TMS320C64X_INS_LDBU,
+ TMS320C64X_INS_LDDW,
+ TMS320C64X_INS_LDH,
+ TMS320C64X_INS_LDHU,
+ TMS320C64X_INS_LDNDW,
+ TMS320C64X_INS_LDNW,
+ TMS320C64X_INS_LDW,
+ TMS320C64X_INS_LMBD,
+ TMS320C64X_INS_MAX2,
+ TMS320C64X_INS_MAXU4,
+ TMS320C64X_INS_MIN2,
+ TMS320C64X_INS_MINU4,
+ TMS320C64X_INS_MPY,
+ TMS320C64X_INS_MPY2,
+ TMS320C64X_INS_MPYH,
+ TMS320C64X_INS_MPYHI,
+ TMS320C64X_INS_MPYHIR,
+ TMS320C64X_INS_MPYHL,
+ TMS320C64X_INS_MPYHLU,
+ TMS320C64X_INS_MPYHSLU,
+ TMS320C64X_INS_MPYHSU,
+ TMS320C64X_INS_MPYHU,
+ TMS320C64X_INS_MPYHULS,
+ TMS320C64X_INS_MPYHUS,
+ TMS320C64X_INS_MPYLH,
+ TMS320C64X_INS_MPYLHU,
+ TMS320C64X_INS_MPYLI,
+ TMS320C64X_INS_MPYLIR,
+ TMS320C64X_INS_MPYLSHU,
+ TMS320C64X_INS_MPYLUHS,
+ TMS320C64X_INS_MPYSU,
+ TMS320C64X_INS_MPYSU4,
+ TMS320C64X_INS_MPYU,
+ TMS320C64X_INS_MPYU4,
+ TMS320C64X_INS_MPYUS,
+ TMS320C64X_INS_MVC,
+ TMS320C64X_INS_MVD,
+ TMS320C64X_INS_MVK,
+ TMS320C64X_INS_MVKL,
+ TMS320C64X_INS_MVKLH,
+ TMS320C64X_INS_NOP,
+ TMS320C64X_INS_NORM,
+ TMS320C64X_INS_OR,
+ TMS320C64X_INS_PACK2,
+ TMS320C64X_INS_PACKH2,
+ TMS320C64X_INS_PACKH4,
+ TMS320C64X_INS_PACKHL2,
+ TMS320C64X_INS_PACKL4,
+ TMS320C64X_INS_PACKLH2,
+ TMS320C64X_INS_ROTL,
+ TMS320C64X_INS_SADD,
+ TMS320C64X_INS_SADD2,
+ TMS320C64X_INS_SADDU4,
+ TMS320C64X_INS_SADDUS2,
+ TMS320C64X_INS_SAT,
+ TMS320C64X_INS_SET,
+ TMS320C64X_INS_SHFL,
+ TMS320C64X_INS_SHL,
+ TMS320C64X_INS_SHLMB,
+ TMS320C64X_INS_SHR,
+ TMS320C64X_INS_SHR2,
+ TMS320C64X_INS_SHRMB,
+ TMS320C64X_INS_SHRU,
+ TMS320C64X_INS_SHRU2,
+ TMS320C64X_INS_SMPY,
+ TMS320C64X_INS_SMPY2,
+ TMS320C64X_INS_SMPYH,
+ TMS320C64X_INS_SMPYHL,
+ TMS320C64X_INS_SMPYLH,
+ TMS320C64X_INS_SPACK2,
+ TMS320C64X_INS_SPACKU4,
+ TMS320C64X_INS_SSHL,
+ TMS320C64X_INS_SSHVL,
+ TMS320C64X_INS_SSHVR,
+ TMS320C64X_INS_SSUB,
+ TMS320C64X_INS_STB,
+ TMS320C64X_INS_STDW,
+ TMS320C64X_INS_STH,
+ TMS320C64X_INS_STNDW,
+ TMS320C64X_INS_STNW,
+ TMS320C64X_INS_STW,
+ TMS320C64X_INS_SUB,
+ TMS320C64X_INS_SUB2,
+ TMS320C64X_INS_SUB4,
+ TMS320C64X_INS_SUBAB,
+ TMS320C64X_INS_SUBABS4,
+ TMS320C64X_INS_SUBAH,
+ TMS320C64X_INS_SUBAW,
+ TMS320C64X_INS_SUBC,
+ TMS320C64X_INS_SUBU,
+ TMS320C64X_INS_SWAP4,
+ TMS320C64X_INS_UNPKHU4,
+ TMS320C64X_INS_UNPKLU4,
+ TMS320C64X_INS_XOR,
+ TMS320C64X_INS_XPND2,
+ TMS320C64X_INS_XPND4,
+ // Aliases
+ TMS320C64X_INS_IDLE,
+ TMS320C64X_INS_MV,
+ TMS320C64X_INS_NEG,
+ TMS320C64X_INS_NOT,
+ TMS320C64X_INS_SWAP2,
+ TMS320C64X_INS_ZERO,
+
+ TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions
+} tms320c64x_insn;
+
+typedef enum tms320c64x_insn_group {
+ TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ TMS320C64X_GRP_JUMP, ///< = CS_GRP_JUMP
+
+ TMS320C64X_GRP_FUNIT_D = 128,
+ TMS320C64X_GRP_FUNIT_L,
+ TMS320C64X_GRP_FUNIT_M,
+ TMS320C64X_GRP_FUNIT_S,
+ TMS320C64X_GRP_FUNIT_NO,
+
+ TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups
+} tms320c64x_insn_group;
+
+typedef enum tms320c64x_funit {
+ TMS320C64X_FUNIT_INVALID = 0,
+ TMS320C64X_FUNIT_D,
+ TMS320C64X_FUNIT_L,
+ TMS320C64X_FUNIT_M,
+ TMS320C64X_FUNIT_S,
+ TMS320C64X_FUNIT_NO
+} tms320c64x_funit;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/x86.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/x86.h
new file mode 100644
index 00000000..f8fc09e5
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/x86.h
@@ -0,0 +1,1972 @@
+#ifndef CAPSTONE_X86_H
+#define CAPSTONE_X86_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2013-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+/// Calculate relative address for X86-64, given cs_insn structure
+#define X86_REL_ADDR(insn) (((insn).detail->x86.operands[0].type == X86_OP_IMM) \
+ ? (uint64_t)((insn).detail->x86.operands[0].imm) \
+ : (((insn).address + (insn).size) + (uint64_t)(insn).detail->x86.disp))
+
+/// X86 registers
+typedef enum x86_reg {
+ X86_REG_INVALID = 0,
+ X86_REG_AH, X86_REG_AL, X86_REG_AX, X86_REG_BH, X86_REG_BL,
+ X86_REG_BP, X86_REG_BPL, X86_REG_BX, X86_REG_CH, X86_REG_CL,
+ X86_REG_CS, X86_REG_CX, X86_REG_DH, X86_REG_DI, X86_REG_DIL,
+ X86_REG_DL, X86_REG_DS, X86_REG_DX, X86_REG_EAX, X86_REG_EBP,
+ X86_REG_EBX, X86_REG_ECX, X86_REG_EDI, X86_REG_EDX, X86_REG_EFLAGS,
+ X86_REG_EIP, X86_REG_EIZ, X86_REG_ES, X86_REG_ESI, X86_REG_ESP,
+ X86_REG_FPSW, X86_REG_FS, X86_REG_GS, X86_REG_IP, X86_REG_RAX,
+ X86_REG_RBP, X86_REG_RBX, X86_REG_RCX, X86_REG_RDI, X86_REG_RDX,
+ X86_REG_RIP, X86_REG_RIZ, X86_REG_RSI, X86_REG_RSP, X86_REG_SI,
+ X86_REG_SIL, X86_REG_SP, X86_REG_SPL, X86_REG_SS, X86_REG_CR0,
+ X86_REG_CR1, X86_REG_CR2, X86_REG_CR3, X86_REG_CR4, X86_REG_CR5,
+ X86_REG_CR6, X86_REG_CR7, X86_REG_CR8, X86_REG_CR9, X86_REG_CR10,
+ X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15,
+ X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4,
+ X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_DR8, X86_REG_DR9,
+ X86_REG_DR10, X86_REG_DR11, X86_REG_DR12, X86_REG_DR13, X86_REG_DR14,
+ X86_REG_DR15, X86_REG_FP0, X86_REG_FP1, X86_REG_FP2, X86_REG_FP3,
+ X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7,
+ X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4,
+ X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1,
+ X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6,
+ X86_REG_MM7, X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
+ X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
+ X86_REG_ST0, X86_REG_ST1, X86_REG_ST2, X86_REG_ST3,
+ X86_REG_ST4, X86_REG_ST5, X86_REG_ST6, X86_REG_ST7,
+ X86_REG_XMM0, X86_REG_XMM1, X86_REG_XMM2, X86_REG_XMM3, X86_REG_XMM4,
+ X86_REG_XMM5, X86_REG_XMM6, X86_REG_XMM7, X86_REG_XMM8, X86_REG_XMM9,
+ X86_REG_XMM10, X86_REG_XMM11, X86_REG_XMM12, X86_REG_XMM13, X86_REG_XMM14,
+ X86_REG_XMM15, X86_REG_XMM16, X86_REG_XMM17, X86_REG_XMM18, X86_REG_XMM19,
+ X86_REG_XMM20, X86_REG_XMM21, X86_REG_XMM22, X86_REG_XMM23, X86_REG_XMM24,
+ X86_REG_XMM25, X86_REG_XMM26, X86_REG_XMM27, X86_REG_XMM28, X86_REG_XMM29,
+ X86_REG_XMM30, X86_REG_XMM31, X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2,
+ X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7,
+ X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12,
+ X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, X86_REG_YMM16, X86_REG_YMM17,
+ X86_REG_YMM18, X86_REG_YMM19, X86_REG_YMM20, X86_REG_YMM21, X86_REG_YMM22,
+ X86_REG_YMM23, X86_REG_YMM24, X86_REG_YMM25, X86_REG_YMM26, X86_REG_YMM27,
+ X86_REG_YMM28, X86_REG_YMM29, X86_REG_YMM30, X86_REG_YMM31, X86_REG_ZMM0,
+ X86_REG_ZMM1, X86_REG_ZMM2, X86_REG_ZMM3, X86_REG_ZMM4, X86_REG_ZMM5,
+ X86_REG_ZMM6, X86_REG_ZMM7, X86_REG_ZMM8, X86_REG_ZMM9, X86_REG_ZMM10,
+ X86_REG_ZMM11, X86_REG_ZMM12, X86_REG_ZMM13, X86_REG_ZMM14, X86_REG_ZMM15,
+ X86_REG_ZMM16, X86_REG_ZMM17, X86_REG_ZMM18, X86_REG_ZMM19, X86_REG_ZMM20,
+ X86_REG_ZMM21, X86_REG_ZMM22, X86_REG_ZMM23, X86_REG_ZMM24, X86_REG_ZMM25,
+ X86_REG_ZMM26, X86_REG_ZMM27, X86_REG_ZMM28, X86_REG_ZMM29, X86_REG_ZMM30,
+ X86_REG_ZMM31, X86_REG_R8B, X86_REG_R9B, X86_REG_R10B, X86_REG_R11B,
+ X86_REG_R12B, X86_REG_R13B, X86_REG_R14B, X86_REG_R15B, X86_REG_R8D,
+ X86_REG_R9D, X86_REG_R10D, X86_REG_R11D, X86_REG_R12D, X86_REG_R13D,
+ X86_REG_R14D, X86_REG_R15D, X86_REG_R8W, X86_REG_R9W, X86_REG_R10W,
+ X86_REG_R11W, X86_REG_R12W, X86_REG_R13W, X86_REG_R14W, X86_REG_R15W,
+
+ X86_REG_ENDING // <-- mark the end of the list of registers
+} x86_reg;
+
+// Sub-flags of EFLAGS
+#define X86_EFLAGS_MODIFY_AF (1ULL << 0)
+#define X86_EFLAGS_MODIFY_CF (1ULL << 1)
+#define X86_EFLAGS_MODIFY_SF (1ULL << 2)
+#define X86_EFLAGS_MODIFY_ZF (1ULL << 3)
+#define X86_EFLAGS_MODIFY_PF (1ULL << 4)
+#define X86_EFLAGS_MODIFY_OF (1ULL << 5)
+#define X86_EFLAGS_MODIFY_TF (1ULL << 6)
+#define X86_EFLAGS_MODIFY_IF (1ULL << 7)
+#define X86_EFLAGS_MODIFY_DF (1ULL << 8)
+#define X86_EFLAGS_MODIFY_NT (1ULL << 9)
+#define X86_EFLAGS_MODIFY_RF (1ULL << 10)
+#define X86_EFLAGS_PRIOR_OF (1ULL << 11)
+#define X86_EFLAGS_PRIOR_SF (1ULL << 12)
+#define X86_EFLAGS_PRIOR_ZF (1ULL << 13)
+#define X86_EFLAGS_PRIOR_AF (1ULL << 14)
+#define X86_EFLAGS_PRIOR_PF (1ULL << 15)
+#define X86_EFLAGS_PRIOR_CF (1ULL << 16)
+#define X86_EFLAGS_PRIOR_TF (1ULL << 17)
+#define X86_EFLAGS_PRIOR_IF (1ULL << 18)
+#define X86_EFLAGS_PRIOR_DF (1ULL << 19)
+#define X86_EFLAGS_PRIOR_NT (1ULL << 20)
+#define X86_EFLAGS_RESET_OF (1ULL << 21)
+#define X86_EFLAGS_RESET_CF (1ULL << 22)
+#define X86_EFLAGS_RESET_DF (1ULL << 23)
+#define X86_EFLAGS_RESET_IF (1ULL << 24)
+#define X86_EFLAGS_RESET_SF (1ULL << 25)
+#define X86_EFLAGS_RESET_AF (1ULL << 26)
+#define X86_EFLAGS_RESET_TF (1ULL << 27)
+#define X86_EFLAGS_RESET_NT (1ULL << 28)
+#define X86_EFLAGS_RESET_PF (1ULL << 29)
+#define X86_EFLAGS_SET_CF (1ULL << 30)
+#define X86_EFLAGS_SET_DF (1ULL << 31)
+#define X86_EFLAGS_SET_IF (1ULL << 32)
+#define X86_EFLAGS_TEST_OF (1ULL << 33)
+#define X86_EFLAGS_TEST_SF (1ULL << 34)
+#define X86_EFLAGS_TEST_ZF (1ULL << 35)
+#define X86_EFLAGS_TEST_PF (1ULL << 36)
+#define X86_EFLAGS_TEST_CF (1ULL << 37)
+#define X86_EFLAGS_TEST_NT (1ULL << 38)
+#define X86_EFLAGS_TEST_DF (1ULL << 39)
+#define X86_EFLAGS_UNDEFINED_OF (1ULL << 40)
+#define X86_EFLAGS_UNDEFINED_SF (1ULL << 41)
+#define X86_EFLAGS_UNDEFINED_ZF (1ULL << 42)
+#define X86_EFLAGS_UNDEFINED_PF (1ULL << 43)
+#define X86_EFLAGS_UNDEFINED_AF (1ULL << 44)
+#define X86_EFLAGS_UNDEFINED_CF (1ULL << 45)
+#define X86_EFLAGS_RESET_RF (1ULL << 46)
+#define X86_EFLAGS_TEST_RF (1ULL << 47)
+#define X86_EFLAGS_TEST_IF (1ULL << 48)
+#define X86_EFLAGS_TEST_TF (1ULL << 49)
+#define X86_EFLAGS_TEST_AF (1ULL << 50)
+#define X86_EFLAGS_RESET_ZF (1ULL << 51)
+#define X86_EFLAGS_SET_OF (1ULL << 52)
+#define X86_EFLAGS_SET_SF (1ULL << 53)
+#define X86_EFLAGS_SET_ZF (1ULL << 54)
+#define X86_EFLAGS_SET_AF (1ULL << 55)
+#define X86_EFLAGS_SET_PF (1ULL << 56)
+#define X86_EFLAGS_RESET_0F (1ULL << 57)
+#define X86_EFLAGS_RESET_AC (1ULL << 58)
+
+#define X86_FPU_FLAGS_MODIFY_C0 (1ULL << 0)
+#define X86_FPU_FLAGS_MODIFY_C1 (1ULL << 1)
+#define X86_FPU_FLAGS_MODIFY_C2 (1ULL << 2)
+#define X86_FPU_FLAGS_MODIFY_C3 (1ULL << 3)
+#define X86_FPU_FLAGS_RESET_C0 (1ULL << 4)
+#define X86_FPU_FLAGS_RESET_C1 (1ULL << 5)
+#define X86_FPU_FLAGS_RESET_C2 (1ULL << 6)
+#define X86_FPU_FLAGS_RESET_C3 (1ULL << 7)
+#define X86_FPU_FLAGS_SET_C0 (1ULL << 8)
+#define X86_FPU_FLAGS_SET_C1 (1ULL << 9)
+#define X86_FPU_FLAGS_SET_C2 (1ULL << 10)
+#define X86_FPU_FLAGS_SET_C3 (1ULL << 11)
+#define X86_FPU_FLAGS_UNDEFINED_C0 (1ULL << 12)
+#define X86_FPU_FLAGS_UNDEFINED_C1 (1ULL << 13)
+#define X86_FPU_FLAGS_UNDEFINED_C2 (1ULL << 14)
+#define X86_FPU_FLAGS_UNDEFINED_C3 (1ULL << 15)
+#define X86_FPU_FLAGS_TEST_C0 (1ULL << 16)
+#define X86_FPU_FLAGS_TEST_C1 (1ULL << 17)
+#define X86_FPU_FLAGS_TEST_C2 (1ULL << 18)
+#define X86_FPU_FLAGS_TEST_C3 (1ULL << 19)
+
+
+/// Operand type for instruction's operands
+typedef enum x86_op_type {
+ X86_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ X86_OP_REG, ///< = CS_OP_REG (Register operand).
+ X86_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ X86_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} x86_op_type;
+
+/// XOP Code Condition type
+typedef enum x86_xop_cc {
+ X86_XOP_CC_INVALID = 0, ///< Uninitialized.
+ X86_XOP_CC_LT,
+ X86_XOP_CC_LE,
+ X86_XOP_CC_GT,
+ X86_XOP_CC_GE,
+ X86_XOP_CC_EQ,
+ X86_XOP_CC_NEQ,
+ X86_XOP_CC_FALSE,
+ X86_XOP_CC_TRUE,
+} x86_xop_cc;
+
+/// AVX broadcast type
+typedef enum x86_avx_bcast {
+ X86_AVX_BCAST_INVALID = 0, ///< Uninitialized.
+ X86_AVX_BCAST_2, ///< AVX512 broadcast type {1to2}
+ X86_AVX_BCAST_4, ///< AVX512 broadcast type {1to4}
+ X86_AVX_BCAST_8, ///< AVX512 broadcast type {1to8}
+ X86_AVX_BCAST_16, ///< AVX512 broadcast type {1to16}
+} x86_avx_bcast;
+
+/// SSE Code Condition type
+typedef enum x86_sse_cc {
+ X86_SSE_CC_INVALID = 0, ///< Uninitialized.
+ X86_SSE_CC_EQ,
+ X86_SSE_CC_LT,
+ X86_SSE_CC_LE,
+ X86_SSE_CC_UNORD,
+ X86_SSE_CC_NEQ,
+ X86_SSE_CC_NLT,
+ X86_SSE_CC_NLE,
+ X86_SSE_CC_ORD,
+} x86_sse_cc;
+
+/// AVX Code Condition type
+typedef enum x86_avx_cc {
+ X86_AVX_CC_INVALID = 0, ///< Uninitialized.
+ X86_AVX_CC_EQ,
+ X86_AVX_CC_LT,
+ X86_AVX_CC_LE,
+ X86_AVX_CC_UNORD,
+ X86_AVX_CC_NEQ,
+ X86_AVX_CC_NLT,
+ X86_AVX_CC_NLE,
+ X86_AVX_CC_ORD,
+ X86_AVX_CC_EQ_UQ,
+ X86_AVX_CC_NGE,
+ X86_AVX_CC_NGT,
+ X86_AVX_CC_FALSE,
+ X86_AVX_CC_NEQ_OQ,
+ X86_AVX_CC_GE,
+ X86_AVX_CC_GT,
+ X86_AVX_CC_TRUE,
+ X86_AVX_CC_EQ_OS,
+ X86_AVX_CC_LT_OQ,
+ X86_AVX_CC_LE_OQ,
+ X86_AVX_CC_UNORD_S,
+ X86_AVX_CC_NEQ_US,
+ X86_AVX_CC_NLT_UQ,
+ X86_AVX_CC_NLE_UQ,
+ X86_AVX_CC_ORD_S,
+ X86_AVX_CC_EQ_US,
+ X86_AVX_CC_NGE_UQ,
+ X86_AVX_CC_NGT_UQ,
+ X86_AVX_CC_FALSE_OS,
+ X86_AVX_CC_NEQ_OS,
+ X86_AVX_CC_GE_OQ,
+ X86_AVX_CC_GT_OQ,
+ X86_AVX_CC_TRUE_US,
+} x86_avx_cc;
+
+/// AVX static rounding mode type
+typedef enum x86_avx_rm {
+ X86_AVX_RM_INVALID = 0, ///< Uninitialized.
+ X86_AVX_RM_RN, ///< Round to nearest
+ X86_AVX_RM_RD, ///< Round down
+ X86_AVX_RM_RU, ///< Round up
+ X86_AVX_RM_RZ, ///< Round toward zero
+} x86_avx_rm;
+
+/// Instruction prefixes - to be used in cs_x86.prefix[]
+typedef enum x86_prefix {
+ X86_PREFIX_LOCK = 0xf0, ///< lock (cs_x86.prefix[0]
+ X86_PREFIX_REP = 0xf3, ///< rep (cs_x86.prefix[0]
+ X86_PREFIX_REPE = 0xf3, ///< repe/repz (cs_x86.prefix[0]
+ X86_PREFIX_REPNE = 0xf2, ///< repne/repnz (cs_x86.prefix[0]
+
+ X86_PREFIX_CS = 0x2e, ///< segment override CS (cs_x86.prefix[1]
+ X86_PREFIX_SS = 0x36, ///< segment override SS (cs_x86.prefix[1]
+ X86_PREFIX_DS = 0x3e, ///< segment override DS (cs_x86.prefix[1]
+ X86_PREFIX_ES = 0x26, ///< segment override ES (cs_x86.prefix[1]
+ X86_PREFIX_FS = 0x64, ///< segment override FS (cs_x86.prefix[1]
+ X86_PREFIX_GS = 0x65, ///< segment override GS (cs_x86.prefix[1]
+
+ X86_PREFIX_OPSIZE = 0x66, ///< operand-size override (cs_x86.prefix[2]
+ X86_PREFIX_ADDRSIZE = 0x67, ///< address-size override (cs_x86.prefix[3]
+} x86_prefix;
+
+/// Instruction's operand referring to memory
+/// This is associated with X86_OP_MEM operand type above
+typedef struct x86_op_mem {
+ x86_reg segment; ///< segment register (or X86_REG_INVALID if irrelevant)
+ x86_reg base; ///< base register (or X86_REG_INVALID if irrelevant)
+ x86_reg index; ///< index register (or X86_REG_INVALID if irrelevant)
+ int scale; ///< scale for index register
+ int64_t disp; ///< displacement value
+} x86_op_mem;
+
+/// Instruction operand
+typedef struct cs_x86_op {
+ x86_op_type type; ///< operand type
+ union {
+ x86_reg reg; ///< register value for REG operand
+ int64_t imm; ///< immediate value for IMM operand
+ x86_op_mem mem; ///< base/index/scale/disp value for MEM operand
+ };
+
+ /// size of this operand (in bytes).
+ uint8_t size;
+
+ /// How is this operand accessed? (READ, WRITE or READ|WRITE)
+ /// This field is combined of cs_ac_type.
+ /// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+ uint8_t access;
+
+ /// AVX broadcast type, or 0 if irrelevant
+ x86_avx_bcast avx_bcast;
+
+ /// AVX zero opmask {z}
+ bool avx_zero_opmask;
+} cs_x86_op;
+
+typedef struct cs_x86_encoding {
+ /// ModR/M offset, or 0 when irrelevant
+ uint8_t modrm_offset;
+
+ /// Displacement offset, or 0 when irrelevant.
+ uint8_t disp_offset;
+ uint8_t disp_size;
+
+ /// Immediate offset, or 0 when irrelevant.
+ uint8_t imm_offset;
+ uint8_t imm_size;
+} cs_x86_encoding;
+
+/// Instruction structure
+typedef struct cs_x86 {
+ /// Instruction prefix, which can be up to 4 bytes.
+ /// A prefix byte gets value 0 when irrelevant.
+ /// prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)
+ /// prefix[1] indicates segment override (irrelevant for x86_64):
+ /// See X86_PREFIX_CS/SS/DS/ES/FS/GS above.
+ /// prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)
+ /// prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)
+ uint8_t prefix[4];
+
+ /// Instruction opcode, which can be from 1 to 4 bytes in size.
+ /// This contains VEX opcode as well.
+ /// An trailing opcode byte gets value 0 when irrelevant.
+ uint8_t opcode[4];
+
+ /// REX prefix: only a non-zero value is relevant for x86_64
+ uint8_t rex;
+
+ /// Address size, which can be overridden with above prefix[5].
+ uint8_t addr_size;
+
+ /// ModR/M byte
+ uint8_t modrm;
+
+ /// SIB value, or 0 when irrelevant.
+ uint8_t sib;
+
+ /// Displacement value, valid if encoding.disp_offset != 0
+ int64_t disp;
+
+ /// SIB index register, or X86_REG_INVALID when irrelevant.
+ x86_reg sib_index;
+ /// SIB scale, only applicable if sib_index is valid.
+ int8_t sib_scale;
+ /// SIB base register, or X86_REG_INVALID when irrelevant.
+ x86_reg sib_base;
+
+ /// XOP Code Condition
+ x86_xop_cc xop_cc;
+
+ /// SSE Code Condition
+ x86_sse_cc sse_cc;
+
+ /// AVX Code Condition
+ x86_avx_cc avx_cc;
+
+ /// AVX Suppress all Exception
+ bool avx_sae;
+
+ /// AVX static rounding mode
+ x86_avx_rm avx_rm;
+
+
+ union {
+ /// EFLAGS updated by this instruction.
+ /// This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h
+ uint64_t eflags;
+ /// FPU_FLAGS updated by this instruction.
+ /// This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h
+ uint64_t fpu_flags;
+ };
+
+ /// Number of operands of this instruction,
+ /// or 0 when instruction has no operand.
+ uint8_t op_count;
+
+ cs_x86_op operands[8]; ///< operands for this instruction.
+
+ cs_x86_encoding encoding; ///< encoding information
+} cs_x86;
+
+/// X86 instructions
+typedef enum x86_insn {
+ X86_INS_INVALID = 0,
+
+ X86_INS_AAA,
+ X86_INS_AAD,
+ X86_INS_AAM,
+ X86_INS_AAS,
+ X86_INS_FABS,
+ X86_INS_ADC,
+ X86_INS_ADCX,
+ X86_INS_ADD,
+ X86_INS_ADDPD,
+ X86_INS_ADDPS,
+ X86_INS_ADDSD,
+ X86_INS_ADDSS,
+ X86_INS_ADDSUBPD,
+ X86_INS_ADDSUBPS,
+ X86_INS_FADD,
+ X86_INS_FIADD,
+ X86_INS_FADDP,
+ X86_INS_ADOX,
+ X86_INS_AESDECLAST,
+ X86_INS_AESDEC,
+ X86_INS_AESENCLAST,
+ X86_INS_AESENC,
+ X86_INS_AESIMC,
+ X86_INS_AESKEYGENASSIST,
+ X86_INS_AND,
+ X86_INS_ANDN,
+ X86_INS_ANDNPD,
+ X86_INS_ANDNPS,
+ X86_INS_ANDPD,
+ X86_INS_ANDPS,
+ X86_INS_ARPL,
+ X86_INS_BEXTR,
+ X86_INS_BLCFILL,
+ X86_INS_BLCI,
+ X86_INS_BLCIC,
+ X86_INS_BLCMSK,
+ X86_INS_BLCS,
+ X86_INS_BLENDPD,
+ X86_INS_BLENDPS,
+ X86_INS_BLENDVPD,
+ X86_INS_BLENDVPS,
+ X86_INS_BLSFILL,
+ X86_INS_BLSI,
+ X86_INS_BLSIC,
+ X86_INS_BLSMSK,
+ X86_INS_BLSR,
+ X86_INS_BOUND,
+ X86_INS_BSF,
+ X86_INS_BSR,
+ X86_INS_BSWAP,
+ X86_INS_BT,
+ X86_INS_BTC,
+ X86_INS_BTR,
+ X86_INS_BTS,
+ X86_INS_BZHI,
+ X86_INS_CALL,
+ X86_INS_CBW,
+ X86_INS_CDQ,
+ X86_INS_CDQE,
+ X86_INS_FCHS,
+ X86_INS_CLAC,
+ X86_INS_CLC,
+ X86_INS_CLD,
+ X86_INS_CLFLUSH,
+ X86_INS_CLFLUSHOPT,
+ X86_INS_CLGI,
+ X86_INS_CLI,
+ X86_INS_CLTS,
+ X86_INS_CLWB,
+ X86_INS_CMC,
+ X86_INS_CMOVA,
+ X86_INS_CMOVAE,
+ X86_INS_CMOVB,
+ X86_INS_CMOVBE,
+ X86_INS_FCMOVBE,
+ X86_INS_FCMOVB,
+ X86_INS_CMOVE,
+ X86_INS_FCMOVE,
+ X86_INS_CMOVG,
+ X86_INS_CMOVGE,
+ X86_INS_CMOVL,
+ X86_INS_CMOVLE,
+ X86_INS_FCMOVNBE,
+ X86_INS_FCMOVNB,
+ X86_INS_CMOVNE,
+ X86_INS_FCMOVNE,
+ X86_INS_CMOVNO,
+ X86_INS_CMOVNP,
+ X86_INS_FCMOVNU,
+ X86_INS_CMOVNS,
+ X86_INS_CMOVO,
+ X86_INS_CMOVP,
+ X86_INS_FCMOVU,
+ X86_INS_CMOVS,
+ X86_INS_CMP,
+ X86_INS_CMPSB,
+ X86_INS_CMPSQ,
+ X86_INS_CMPSW,
+ X86_INS_CMPXCHG16B,
+ X86_INS_CMPXCHG,
+ X86_INS_CMPXCHG8B,
+ X86_INS_COMISD,
+ X86_INS_COMISS,
+ X86_INS_FCOMP,
+ X86_INS_FCOMIP,
+ X86_INS_FCOMI,
+ X86_INS_FCOM,
+ X86_INS_FCOS,
+ X86_INS_CPUID,
+ X86_INS_CQO,
+ X86_INS_CRC32,
+ X86_INS_CVTDQ2PD,
+ X86_INS_CVTDQ2PS,
+ X86_INS_CVTPD2DQ,
+ X86_INS_CVTPD2PS,
+ X86_INS_CVTPS2DQ,
+ X86_INS_CVTPS2PD,
+ X86_INS_CVTSD2SI,
+ X86_INS_CVTSD2SS,
+ X86_INS_CVTSI2SD,
+ X86_INS_CVTSI2SS,
+ X86_INS_CVTSS2SD,
+ X86_INS_CVTSS2SI,
+ X86_INS_CVTTPD2DQ,
+ X86_INS_CVTTPS2DQ,
+ X86_INS_CVTTSD2SI,
+ X86_INS_CVTTSS2SI,
+ X86_INS_CWD,
+ X86_INS_CWDE,
+ X86_INS_DAA,
+ X86_INS_DAS,
+ X86_INS_DATA16,
+ X86_INS_DEC,
+ X86_INS_DIV,
+ X86_INS_DIVPD,
+ X86_INS_DIVPS,
+ X86_INS_FDIVR,
+ X86_INS_FIDIVR,
+ X86_INS_FDIVRP,
+ X86_INS_DIVSD,
+ X86_INS_DIVSS,
+ X86_INS_FDIV,
+ X86_INS_FIDIV,
+ X86_INS_FDIVP,
+ X86_INS_DPPD,
+ X86_INS_DPPS,
+ X86_INS_RET,
+ X86_INS_ENCLS,
+ X86_INS_ENCLU,
+ X86_INS_ENTER,
+ X86_INS_EXTRACTPS,
+ X86_INS_EXTRQ,
+ X86_INS_F2XM1,
+ X86_INS_LCALL,
+ X86_INS_LJMP,
+ X86_INS_FBLD,
+ X86_INS_FBSTP,
+ X86_INS_FCOMPP,
+ X86_INS_FDECSTP,
+ X86_INS_FEMMS,
+ X86_INS_FFREE,
+ X86_INS_FICOM,
+ X86_INS_FICOMP,
+ X86_INS_FINCSTP,
+ X86_INS_FLDCW,
+ X86_INS_FLDENV,
+ X86_INS_FLDL2E,
+ X86_INS_FLDL2T,
+ X86_INS_FLDLG2,
+ X86_INS_FLDLN2,
+ X86_INS_FLDPI,
+ X86_INS_FNCLEX,
+ X86_INS_FNINIT,
+ X86_INS_FNOP,
+ X86_INS_FNSTCW,
+ X86_INS_FNSTSW,
+ X86_INS_FPATAN,
+ X86_INS_FPREM,
+ X86_INS_FPREM1,
+ X86_INS_FPTAN,
+ X86_INS_FFREEP,
+ X86_INS_FRNDINT,
+ X86_INS_FRSTOR,
+ X86_INS_FNSAVE,
+ X86_INS_FSCALE,
+ X86_INS_FSETPM,
+ X86_INS_FSINCOS,
+ X86_INS_FNSTENV,
+ X86_INS_FXAM,
+ X86_INS_FXRSTOR,
+ X86_INS_FXRSTOR64,
+ X86_INS_FXSAVE,
+ X86_INS_FXSAVE64,
+ X86_INS_FXTRACT,
+ X86_INS_FYL2X,
+ X86_INS_FYL2XP1,
+ X86_INS_MOVAPD,
+ X86_INS_MOVAPS,
+ X86_INS_ORPD,
+ X86_INS_ORPS,
+ X86_INS_VMOVAPD,
+ X86_INS_VMOVAPS,
+ X86_INS_XORPD,
+ X86_INS_XORPS,
+ X86_INS_GETSEC,
+ X86_INS_HADDPD,
+ X86_INS_HADDPS,
+ X86_INS_HLT,
+ X86_INS_HSUBPD,
+ X86_INS_HSUBPS,
+ X86_INS_IDIV,
+ X86_INS_FILD,
+ X86_INS_IMUL,
+ X86_INS_IN,
+ X86_INS_INC,
+ X86_INS_INSB,
+ X86_INS_INSERTPS,
+ X86_INS_INSERTQ,
+ X86_INS_INSD,
+ X86_INS_INSW,
+ X86_INS_INT,
+ X86_INS_INT1,
+ X86_INS_INT3,
+ X86_INS_INTO,
+ X86_INS_INVD,
+ X86_INS_INVEPT,
+ X86_INS_INVLPG,
+ X86_INS_INVLPGA,
+ X86_INS_INVPCID,
+ X86_INS_INVVPID,
+ X86_INS_IRET,
+ X86_INS_IRETD,
+ X86_INS_IRETQ,
+ X86_INS_FISTTP,
+ X86_INS_FIST,
+ X86_INS_FISTP,
+ X86_INS_UCOMISD,
+ X86_INS_UCOMISS,
+ X86_INS_VCOMISD,
+ X86_INS_VCOMISS,
+ X86_INS_VCVTSD2SS,
+ X86_INS_VCVTSI2SD,
+ X86_INS_VCVTSI2SS,
+ X86_INS_VCVTSS2SD,
+ X86_INS_VCVTTSD2SI,
+ X86_INS_VCVTTSD2USI,
+ X86_INS_VCVTTSS2SI,
+ X86_INS_VCVTTSS2USI,
+ X86_INS_VCVTUSI2SD,
+ X86_INS_VCVTUSI2SS,
+ X86_INS_VUCOMISD,
+ X86_INS_VUCOMISS,
+ X86_INS_JAE,
+ X86_INS_JA,
+ X86_INS_JBE,
+ X86_INS_JB,
+ X86_INS_JCXZ,
+ X86_INS_JECXZ,
+ X86_INS_JE,
+ X86_INS_JGE,
+ X86_INS_JG,
+ X86_INS_JLE,
+ X86_INS_JL,
+ X86_INS_JMP,
+ X86_INS_JNE,
+ X86_INS_JNO,
+ X86_INS_JNP,
+ X86_INS_JNS,
+ X86_INS_JO,
+ X86_INS_JP,
+ X86_INS_JRCXZ,
+ X86_INS_JS,
+ X86_INS_KANDB,
+ X86_INS_KANDD,
+ X86_INS_KANDNB,
+ X86_INS_KANDND,
+ X86_INS_KANDNQ,
+ X86_INS_KANDNW,
+ X86_INS_KANDQ,
+ X86_INS_KANDW,
+ X86_INS_KMOVB,
+ X86_INS_KMOVD,
+ X86_INS_KMOVQ,
+ X86_INS_KMOVW,
+ X86_INS_KNOTB,
+ X86_INS_KNOTD,
+ X86_INS_KNOTQ,
+ X86_INS_KNOTW,
+ X86_INS_KORB,
+ X86_INS_KORD,
+ X86_INS_KORQ,
+ X86_INS_KORTESTB,
+ X86_INS_KORTESTD,
+ X86_INS_KORTESTQ,
+ X86_INS_KORTESTW,
+ X86_INS_KORW,
+ X86_INS_KSHIFTLB,
+ X86_INS_KSHIFTLD,
+ X86_INS_KSHIFTLQ,
+ X86_INS_KSHIFTLW,
+ X86_INS_KSHIFTRB,
+ X86_INS_KSHIFTRD,
+ X86_INS_KSHIFTRQ,
+ X86_INS_KSHIFTRW,
+ X86_INS_KUNPCKBW,
+ X86_INS_KXNORB,
+ X86_INS_KXNORD,
+ X86_INS_KXNORQ,
+ X86_INS_KXNORW,
+ X86_INS_KXORB,
+ X86_INS_KXORD,
+ X86_INS_KXORQ,
+ X86_INS_KXORW,
+ X86_INS_LAHF,
+ X86_INS_LAR,
+ X86_INS_LDDQU,
+ X86_INS_LDMXCSR,
+ X86_INS_LDS,
+ X86_INS_FLDZ,
+ X86_INS_FLD1,
+ X86_INS_FLD,
+ X86_INS_LEA,
+ X86_INS_LEAVE,
+ X86_INS_LES,
+ X86_INS_LFENCE,
+ X86_INS_LFS,
+ X86_INS_LGDT,
+ X86_INS_LGS,
+ X86_INS_LIDT,
+ X86_INS_LLDT,
+ X86_INS_LMSW,
+ X86_INS_OR,
+ X86_INS_SUB,
+ X86_INS_XOR,
+ X86_INS_LODSB,
+ X86_INS_LODSD,
+ X86_INS_LODSQ,
+ X86_INS_LODSW,
+ X86_INS_LOOP,
+ X86_INS_LOOPE,
+ X86_INS_LOOPNE,
+ X86_INS_RETF,
+ X86_INS_RETFQ,
+ X86_INS_LSL,
+ X86_INS_LSS,
+ X86_INS_LTR,
+ X86_INS_XADD,
+ X86_INS_LZCNT,
+ X86_INS_MASKMOVDQU,
+ X86_INS_MAXPD,
+ X86_INS_MAXPS,
+ X86_INS_MAXSD,
+ X86_INS_MAXSS,
+ X86_INS_MFENCE,
+ X86_INS_MINPD,
+ X86_INS_MINPS,
+ X86_INS_MINSD,
+ X86_INS_MINSS,
+ X86_INS_CVTPD2PI,
+ X86_INS_CVTPI2PD,
+ X86_INS_CVTPI2PS,
+ X86_INS_CVTPS2PI,
+ X86_INS_CVTTPD2PI,
+ X86_INS_CVTTPS2PI,
+ X86_INS_EMMS,
+ X86_INS_MASKMOVQ,
+ X86_INS_MOVD,
+ X86_INS_MOVDQ2Q,
+ X86_INS_MOVNTQ,
+ X86_INS_MOVQ2DQ,
+ X86_INS_MOVQ,
+ X86_INS_PABSB,
+ X86_INS_PABSD,
+ X86_INS_PABSW,
+ X86_INS_PACKSSDW,
+ X86_INS_PACKSSWB,
+ X86_INS_PACKUSWB,
+ X86_INS_PADDB,
+ X86_INS_PADDD,
+ X86_INS_PADDQ,
+ X86_INS_PADDSB,
+ X86_INS_PADDSW,
+ X86_INS_PADDUSB,
+ X86_INS_PADDUSW,
+ X86_INS_PADDW,
+ X86_INS_PALIGNR,
+ X86_INS_PANDN,
+ X86_INS_PAND,
+ X86_INS_PAVGB,
+ X86_INS_PAVGW,
+ X86_INS_PCMPEQB,
+ X86_INS_PCMPEQD,
+ X86_INS_PCMPEQW,
+ X86_INS_PCMPGTB,
+ X86_INS_PCMPGTD,
+ X86_INS_PCMPGTW,
+ X86_INS_PEXTRW,
+ X86_INS_PHADDSW,
+ X86_INS_PHADDW,
+ X86_INS_PHADDD,
+ X86_INS_PHSUBD,
+ X86_INS_PHSUBSW,
+ X86_INS_PHSUBW,
+ X86_INS_PINSRW,
+ X86_INS_PMADDUBSW,
+ X86_INS_PMADDWD,
+ X86_INS_PMAXSW,
+ X86_INS_PMAXUB,
+ X86_INS_PMINSW,
+ X86_INS_PMINUB,
+ X86_INS_PMOVMSKB,
+ X86_INS_PMULHRSW,
+ X86_INS_PMULHUW,
+ X86_INS_PMULHW,
+ X86_INS_PMULLW,
+ X86_INS_PMULUDQ,
+ X86_INS_POR,
+ X86_INS_PSADBW,
+ X86_INS_PSHUFB,
+ X86_INS_PSHUFW,
+ X86_INS_PSIGNB,
+ X86_INS_PSIGND,
+ X86_INS_PSIGNW,
+ X86_INS_PSLLD,
+ X86_INS_PSLLQ,
+ X86_INS_PSLLW,
+ X86_INS_PSRAD,
+ X86_INS_PSRAW,
+ X86_INS_PSRLD,
+ X86_INS_PSRLQ,
+ X86_INS_PSRLW,
+ X86_INS_PSUBB,
+ X86_INS_PSUBD,
+ X86_INS_PSUBQ,
+ X86_INS_PSUBSB,
+ X86_INS_PSUBSW,
+ X86_INS_PSUBUSB,
+ X86_INS_PSUBUSW,
+ X86_INS_PSUBW,
+ X86_INS_PUNPCKHBW,
+ X86_INS_PUNPCKHDQ,
+ X86_INS_PUNPCKHWD,
+ X86_INS_PUNPCKLBW,
+ X86_INS_PUNPCKLDQ,
+ X86_INS_PUNPCKLWD,
+ X86_INS_PXOR,
+ X86_INS_MONITOR,
+ X86_INS_MONTMUL,
+ X86_INS_MOV,
+ X86_INS_MOVABS,
+ X86_INS_MOVBE,
+ X86_INS_MOVDDUP,
+ X86_INS_MOVDQA,
+ X86_INS_MOVDQU,
+ X86_INS_MOVHLPS,
+ X86_INS_MOVHPD,
+ X86_INS_MOVHPS,
+ X86_INS_MOVLHPS,
+ X86_INS_MOVLPD,
+ X86_INS_MOVLPS,
+ X86_INS_MOVMSKPD,
+ X86_INS_MOVMSKPS,
+ X86_INS_MOVNTDQA,
+ X86_INS_MOVNTDQ,
+ X86_INS_MOVNTI,
+ X86_INS_MOVNTPD,
+ X86_INS_MOVNTPS,
+ X86_INS_MOVNTSD,
+ X86_INS_MOVNTSS,
+ X86_INS_MOVSB,
+ X86_INS_MOVSD,
+ X86_INS_MOVSHDUP,
+ X86_INS_MOVSLDUP,
+ X86_INS_MOVSQ,
+ X86_INS_MOVSS,
+ X86_INS_MOVSW,
+ X86_INS_MOVSX,
+ X86_INS_MOVSXD,
+ X86_INS_MOVUPD,
+ X86_INS_MOVUPS,
+ X86_INS_MOVZX,
+ X86_INS_MPSADBW,
+ X86_INS_MUL,
+ X86_INS_MULPD,
+ X86_INS_MULPS,
+ X86_INS_MULSD,
+ X86_INS_MULSS,
+ X86_INS_MULX,
+ X86_INS_FMUL,
+ X86_INS_FIMUL,
+ X86_INS_FMULP,
+ X86_INS_MWAIT,
+ X86_INS_NEG,
+ X86_INS_NOP,
+ X86_INS_NOT,
+ X86_INS_OUT,
+ X86_INS_OUTSB,
+ X86_INS_OUTSD,
+ X86_INS_OUTSW,
+ X86_INS_PACKUSDW,
+ X86_INS_PAUSE,
+ X86_INS_PAVGUSB,
+ X86_INS_PBLENDVB,
+ X86_INS_PBLENDW,
+ X86_INS_PCLMULQDQ,
+ X86_INS_PCMPEQQ,
+ X86_INS_PCMPESTRI,
+ X86_INS_PCMPESTRM,
+ X86_INS_PCMPGTQ,
+ X86_INS_PCMPISTRI,
+ X86_INS_PCMPISTRM,
+ X86_INS_PCOMMIT,
+ X86_INS_PDEP,
+ X86_INS_PEXT,
+ X86_INS_PEXTRB,
+ X86_INS_PEXTRD,
+ X86_INS_PEXTRQ,
+ X86_INS_PF2ID,
+ X86_INS_PF2IW,
+ X86_INS_PFACC,
+ X86_INS_PFADD,
+ X86_INS_PFCMPEQ,
+ X86_INS_PFCMPGE,
+ X86_INS_PFCMPGT,
+ X86_INS_PFMAX,
+ X86_INS_PFMIN,
+ X86_INS_PFMUL,
+ X86_INS_PFNACC,
+ X86_INS_PFPNACC,
+ X86_INS_PFRCPIT1,
+ X86_INS_PFRCPIT2,
+ X86_INS_PFRCP,
+ X86_INS_PFRSQIT1,
+ X86_INS_PFRSQRT,
+ X86_INS_PFSUBR,
+ X86_INS_PFSUB,
+ X86_INS_PHMINPOSUW,
+ X86_INS_PI2FD,
+ X86_INS_PI2FW,
+ X86_INS_PINSRB,
+ X86_INS_PINSRD,
+ X86_INS_PINSRQ,
+ X86_INS_PMAXSB,
+ X86_INS_PMAXSD,
+ X86_INS_PMAXUD,
+ X86_INS_PMAXUW,
+ X86_INS_PMINSB,
+ X86_INS_PMINSD,
+ X86_INS_PMINUD,
+ X86_INS_PMINUW,
+ X86_INS_PMOVSXBD,
+ X86_INS_PMOVSXBQ,
+ X86_INS_PMOVSXBW,
+ X86_INS_PMOVSXDQ,
+ X86_INS_PMOVSXWD,
+ X86_INS_PMOVSXWQ,
+ X86_INS_PMOVZXBD,
+ X86_INS_PMOVZXBQ,
+ X86_INS_PMOVZXBW,
+ X86_INS_PMOVZXDQ,
+ X86_INS_PMOVZXWD,
+ X86_INS_PMOVZXWQ,
+ X86_INS_PMULDQ,
+ X86_INS_PMULHRW,
+ X86_INS_PMULLD,
+ X86_INS_POP,
+ X86_INS_POPAW,
+ X86_INS_POPAL,
+ X86_INS_POPCNT,
+ X86_INS_POPF,
+ X86_INS_POPFD,
+ X86_INS_POPFQ,
+ X86_INS_PREFETCH,
+ X86_INS_PREFETCHNTA,
+ X86_INS_PREFETCHT0,
+ X86_INS_PREFETCHT1,
+ X86_INS_PREFETCHT2,
+ X86_INS_PREFETCHW,
+ X86_INS_PSHUFD,
+ X86_INS_PSHUFHW,
+ X86_INS_PSHUFLW,
+ X86_INS_PSLLDQ,
+ X86_INS_PSRLDQ,
+ X86_INS_PSWAPD,
+ X86_INS_PTEST,
+ X86_INS_PUNPCKHQDQ,
+ X86_INS_PUNPCKLQDQ,
+ X86_INS_PUSH,
+ X86_INS_PUSHAW,
+ X86_INS_PUSHAL,
+ X86_INS_PUSHF,
+ X86_INS_PUSHFD,
+ X86_INS_PUSHFQ,
+ X86_INS_RCL,
+ X86_INS_RCPPS,
+ X86_INS_RCPSS,
+ X86_INS_RCR,
+ X86_INS_RDFSBASE,
+ X86_INS_RDGSBASE,
+ X86_INS_RDMSR,
+ X86_INS_RDPMC,
+ X86_INS_RDRAND,
+ X86_INS_RDSEED,
+ X86_INS_RDTSC,
+ X86_INS_RDTSCP,
+ X86_INS_ROL,
+ X86_INS_ROR,
+ X86_INS_RORX,
+ X86_INS_ROUNDPD,
+ X86_INS_ROUNDPS,
+ X86_INS_ROUNDSD,
+ X86_INS_ROUNDSS,
+ X86_INS_RSM,
+ X86_INS_RSQRTPS,
+ X86_INS_RSQRTSS,
+ X86_INS_SAHF,
+ X86_INS_SAL,
+ X86_INS_SALC,
+ X86_INS_SAR,
+ X86_INS_SARX,
+ X86_INS_SBB,
+ X86_INS_SCASB,
+ X86_INS_SCASD,
+ X86_INS_SCASQ,
+ X86_INS_SCASW,
+ X86_INS_SETAE,
+ X86_INS_SETA,
+ X86_INS_SETBE,
+ X86_INS_SETB,
+ X86_INS_SETE,
+ X86_INS_SETGE,
+ X86_INS_SETG,
+ X86_INS_SETLE,
+ X86_INS_SETL,
+ X86_INS_SETNE,
+ X86_INS_SETNO,
+ X86_INS_SETNP,
+ X86_INS_SETNS,
+ X86_INS_SETO,
+ X86_INS_SETP,
+ X86_INS_SETS,
+ X86_INS_SFENCE,
+ X86_INS_SGDT,
+ X86_INS_SHA1MSG1,
+ X86_INS_SHA1MSG2,
+ X86_INS_SHA1NEXTE,
+ X86_INS_SHA1RNDS4,
+ X86_INS_SHA256MSG1,
+ X86_INS_SHA256MSG2,
+ X86_INS_SHA256RNDS2,
+ X86_INS_SHL,
+ X86_INS_SHLD,
+ X86_INS_SHLX,
+ X86_INS_SHR,
+ X86_INS_SHRD,
+ X86_INS_SHRX,
+ X86_INS_SHUFPD,
+ X86_INS_SHUFPS,
+ X86_INS_SIDT,
+ X86_INS_FSIN,
+ X86_INS_SKINIT,
+ X86_INS_SLDT,
+ X86_INS_SMSW,
+ X86_INS_SQRTPD,
+ X86_INS_SQRTPS,
+ X86_INS_SQRTSD,
+ X86_INS_SQRTSS,
+ X86_INS_FSQRT,
+ X86_INS_STAC,
+ X86_INS_STC,
+ X86_INS_STD,
+ X86_INS_STGI,
+ X86_INS_STI,
+ X86_INS_STMXCSR,
+ X86_INS_STOSB,
+ X86_INS_STOSD,
+ X86_INS_STOSQ,
+ X86_INS_STOSW,
+ X86_INS_STR,
+ X86_INS_FST,
+ X86_INS_FSTP,
+ X86_INS_FSTPNCE,
+ X86_INS_FXCH,
+ X86_INS_SUBPD,
+ X86_INS_SUBPS,
+ X86_INS_FSUBR,
+ X86_INS_FISUBR,
+ X86_INS_FSUBRP,
+ X86_INS_SUBSD,
+ X86_INS_SUBSS,
+ X86_INS_FSUB,
+ X86_INS_FISUB,
+ X86_INS_FSUBP,
+ X86_INS_SWAPGS,
+ X86_INS_SYSCALL,
+ X86_INS_SYSENTER,
+ X86_INS_SYSEXIT,
+ X86_INS_SYSRET,
+ X86_INS_T1MSKC,
+ X86_INS_TEST,
+ X86_INS_UD2,
+ X86_INS_FTST,
+ X86_INS_TZCNT,
+ X86_INS_TZMSK,
+ X86_INS_FUCOMIP,
+ X86_INS_FUCOMI,
+ X86_INS_FUCOMPP,
+ X86_INS_FUCOMP,
+ X86_INS_FUCOM,
+ X86_INS_UD2B,
+ X86_INS_UNPCKHPD,
+ X86_INS_UNPCKHPS,
+ X86_INS_UNPCKLPD,
+ X86_INS_UNPCKLPS,
+ X86_INS_VADDPD,
+ X86_INS_VADDPS,
+ X86_INS_VADDSD,
+ X86_INS_VADDSS,
+ X86_INS_VADDSUBPD,
+ X86_INS_VADDSUBPS,
+ X86_INS_VAESDECLAST,
+ X86_INS_VAESDEC,
+ X86_INS_VAESENCLAST,
+ X86_INS_VAESENC,
+ X86_INS_VAESIMC,
+ X86_INS_VAESKEYGENASSIST,
+ X86_INS_VALIGND,
+ X86_INS_VALIGNQ,
+ X86_INS_VANDNPD,
+ X86_INS_VANDNPS,
+ X86_INS_VANDPD,
+ X86_INS_VANDPS,
+ X86_INS_VBLENDMPD,
+ X86_INS_VBLENDMPS,
+ X86_INS_VBLENDPD,
+ X86_INS_VBLENDPS,
+ X86_INS_VBLENDVPD,
+ X86_INS_VBLENDVPS,
+ X86_INS_VBROADCASTF128,
+ X86_INS_VBROADCASTI32X4,
+ X86_INS_VBROADCASTI64X4,
+ X86_INS_VBROADCASTSD,
+ X86_INS_VBROADCASTSS,
+ X86_INS_VCOMPRESSPD,
+ X86_INS_VCOMPRESSPS,
+ X86_INS_VCVTDQ2PD,
+ X86_INS_VCVTDQ2PS,
+ X86_INS_VCVTPD2DQX,
+ X86_INS_VCVTPD2DQ,
+ X86_INS_VCVTPD2PSX,
+ X86_INS_VCVTPD2PS,
+ X86_INS_VCVTPD2UDQ,
+ X86_INS_VCVTPH2PS,
+ X86_INS_VCVTPS2DQ,
+ X86_INS_VCVTPS2PD,
+ X86_INS_VCVTPS2PH,
+ X86_INS_VCVTPS2UDQ,
+ X86_INS_VCVTSD2SI,
+ X86_INS_VCVTSD2USI,
+ X86_INS_VCVTSS2SI,
+ X86_INS_VCVTSS2USI,
+ X86_INS_VCVTTPD2DQX,
+ X86_INS_VCVTTPD2DQ,
+ X86_INS_VCVTTPD2UDQ,
+ X86_INS_VCVTTPS2DQ,
+ X86_INS_VCVTTPS2UDQ,
+ X86_INS_VCVTUDQ2PD,
+ X86_INS_VCVTUDQ2PS,
+ X86_INS_VDIVPD,
+ X86_INS_VDIVPS,
+ X86_INS_VDIVSD,
+ X86_INS_VDIVSS,
+ X86_INS_VDPPD,
+ X86_INS_VDPPS,
+ X86_INS_VERR,
+ X86_INS_VERW,
+ X86_INS_VEXP2PD,
+ X86_INS_VEXP2PS,
+ X86_INS_VEXPANDPD,
+ X86_INS_VEXPANDPS,
+ X86_INS_VEXTRACTF128,
+ X86_INS_VEXTRACTF32X4,
+ X86_INS_VEXTRACTF64X4,
+ X86_INS_VEXTRACTI128,
+ X86_INS_VEXTRACTI32X4,
+ X86_INS_VEXTRACTI64X4,
+ X86_INS_VEXTRACTPS,
+ X86_INS_VFMADD132PD,
+ X86_INS_VFMADD132PS,
+ X86_INS_VFMADDPD,
+ X86_INS_VFMADD213PD,
+ X86_INS_VFMADD231PD,
+ X86_INS_VFMADDPS,
+ X86_INS_VFMADD213PS,
+ X86_INS_VFMADD231PS,
+ X86_INS_VFMADDSD,
+ X86_INS_VFMADD213SD,
+ X86_INS_VFMADD132SD,
+ X86_INS_VFMADD231SD,
+ X86_INS_VFMADDSS,
+ X86_INS_VFMADD213SS,
+ X86_INS_VFMADD132SS,
+ X86_INS_VFMADD231SS,
+ X86_INS_VFMADDSUB132PD,
+ X86_INS_VFMADDSUB132PS,
+ X86_INS_VFMADDSUBPD,
+ X86_INS_VFMADDSUB213PD,
+ X86_INS_VFMADDSUB231PD,
+ X86_INS_VFMADDSUBPS,
+ X86_INS_VFMADDSUB213PS,
+ X86_INS_VFMADDSUB231PS,
+ X86_INS_VFMSUB132PD,
+ X86_INS_VFMSUB132PS,
+ X86_INS_VFMSUBADD132PD,
+ X86_INS_VFMSUBADD132PS,
+ X86_INS_VFMSUBADDPD,
+ X86_INS_VFMSUBADD213PD,
+ X86_INS_VFMSUBADD231PD,
+ X86_INS_VFMSUBADDPS,
+ X86_INS_VFMSUBADD213PS,
+ X86_INS_VFMSUBADD231PS,
+ X86_INS_VFMSUBPD,
+ X86_INS_VFMSUB213PD,
+ X86_INS_VFMSUB231PD,
+ X86_INS_VFMSUBPS,
+ X86_INS_VFMSUB213PS,
+ X86_INS_VFMSUB231PS,
+ X86_INS_VFMSUBSD,
+ X86_INS_VFMSUB213SD,
+ X86_INS_VFMSUB132SD,
+ X86_INS_VFMSUB231SD,
+ X86_INS_VFMSUBSS,
+ X86_INS_VFMSUB213SS,
+ X86_INS_VFMSUB132SS,
+ X86_INS_VFMSUB231SS,
+ X86_INS_VFNMADD132PD,
+ X86_INS_VFNMADD132PS,
+ X86_INS_VFNMADDPD,
+ X86_INS_VFNMADD213PD,
+ X86_INS_VFNMADD231PD,
+ X86_INS_VFNMADDPS,
+ X86_INS_VFNMADD213PS,
+ X86_INS_VFNMADD231PS,
+ X86_INS_VFNMADDSD,
+ X86_INS_VFNMADD213SD,
+ X86_INS_VFNMADD132SD,
+ X86_INS_VFNMADD231SD,
+ X86_INS_VFNMADDSS,
+ X86_INS_VFNMADD213SS,
+ X86_INS_VFNMADD132SS,
+ X86_INS_VFNMADD231SS,
+ X86_INS_VFNMSUB132PD,
+ X86_INS_VFNMSUB132PS,
+ X86_INS_VFNMSUBPD,
+ X86_INS_VFNMSUB213PD,
+ X86_INS_VFNMSUB231PD,
+ X86_INS_VFNMSUBPS,
+ X86_INS_VFNMSUB213PS,
+ X86_INS_VFNMSUB231PS,
+ X86_INS_VFNMSUBSD,
+ X86_INS_VFNMSUB213SD,
+ X86_INS_VFNMSUB132SD,
+ X86_INS_VFNMSUB231SD,
+ X86_INS_VFNMSUBSS,
+ X86_INS_VFNMSUB213SS,
+ X86_INS_VFNMSUB132SS,
+ X86_INS_VFNMSUB231SS,
+ X86_INS_VFRCZPD,
+ X86_INS_VFRCZPS,
+ X86_INS_VFRCZSD,
+ X86_INS_VFRCZSS,
+ X86_INS_VORPD,
+ X86_INS_VORPS,
+ X86_INS_VXORPD,
+ X86_INS_VXORPS,
+ X86_INS_VGATHERDPD,
+ X86_INS_VGATHERDPS,
+ X86_INS_VGATHERPF0DPD,
+ X86_INS_VGATHERPF0DPS,
+ X86_INS_VGATHERPF0QPD,
+ X86_INS_VGATHERPF0QPS,
+ X86_INS_VGATHERPF1DPD,
+ X86_INS_VGATHERPF1DPS,
+ X86_INS_VGATHERPF1QPD,
+ X86_INS_VGATHERPF1QPS,
+ X86_INS_VGATHERQPD,
+ X86_INS_VGATHERQPS,
+ X86_INS_VHADDPD,
+ X86_INS_VHADDPS,
+ X86_INS_VHSUBPD,
+ X86_INS_VHSUBPS,
+ X86_INS_VINSERTF128,
+ X86_INS_VINSERTF32X4,
+ X86_INS_VINSERTF32X8,
+ X86_INS_VINSERTF64X2,
+ X86_INS_VINSERTF64X4,
+ X86_INS_VINSERTI128,
+ X86_INS_VINSERTI32X4,
+ X86_INS_VINSERTI32X8,
+ X86_INS_VINSERTI64X2,
+ X86_INS_VINSERTI64X4,
+ X86_INS_VINSERTPS,
+ X86_INS_VLDDQU,
+ X86_INS_VLDMXCSR,
+ X86_INS_VMASKMOVDQU,
+ X86_INS_VMASKMOVPD,
+ X86_INS_VMASKMOVPS,
+ X86_INS_VMAXPD,
+ X86_INS_VMAXPS,
+ X86_INS_VMAXSD,
+ X86_INS_VMAXSS,
+ X86_INS_VMCALL,
+ X86_INS_VMCLEAR,
+ X86_INS_VMFUNC,
+ X86_INS_VMINPD,
+ X86_INS_VMINPS,
+ X86_INS_VMINSD,
+ X86_INS_VMINSS,
+ X86_INS_VMLAUNCH,
+ X86_INS_VMLOAD,
+ X86_INS_VMMCALL,
+ X86_INS_VMOVQ,
+ X86_INS_VMOVDDUP,
+ X86_INS_VMOVD,
+ X86_INS_VMOVDQA32,
+ X86_INS_VMOVDQA64,
+ X86_INS_VMOVDQA,
+ X86_INS_VMOVDQU16,
+ X86_INS_VMOVDQU32,
+ X86_INS_VMOVDQU64,
+ X86_INS_VMOVDQU8,
+ X86_INS_VMOVDQU,
+ X86_INS_VMOVHLPS,
+ X86_INS_VMOVHPD,
+ X86_INS_VMOVHPS,
+ X86_INS_VMOVLHPS,
+ X86_INS_VMOVLPD,
+ X86_INS_VMOVLPS,
+ X86_INS_VMOVMSKPD,
+ X86_INS_VMOVMSKPS,
+ X86_INS_VMOVNTDQA,
+ X86_INS_VMOVNTDQ,
+ X86_INS_VMOVNTPD,
+ X86_INS_VMOVNTPS,
+ X86_INS_VMOVSD,
+ X86_INS_VMOVSHDUP,
+ X86_INS_VMOVSLDUP,
+ X86_INS_VMOVSS,
+ X86_INS_VMOVUPD,
+ X86_INS_VMOVUPS,
+ X86_INS_VMPSADBW,
+ X86_INS_VMPTRLD,
+ X86_INS_VMPTRST,
+ X86_INS_VMREAD,
+ X86_INS_VMRESUME,
+ X86_INS_VMRUN,
+ X86_INS_VMSAVE,
+ X86_INS_VMULPD,
+ X86_INS_VMULPS,
+ X86_INS_VMULSD,
+ X86_INS_VMULSS,
+ X86_INS_VMWRITE,
+ X86_INS_VMXOFF,
+ X86_INS_VMXON,
+ X86_INS_VPABSB,
+ X86_INS_VPABSD,
+ X86_INS_VPABSQ,
+ X86_INS_VPABSW,
+ X86_INS_VPACKSSDW,
+ X86_INS_VPACKSSWB,
+ X86_INS_VPACKUSDW,
+ X86_INS_VPACKUSWB,
+ X86_INS_VPADDB,
+ X86_INS_VPADDD,
+ X86_INS_VPADDQ,
+ X86_INS_VPADDSB,
+ X86_INS_VPADDSW,
+ X86_INS_VPADDUSB,
+ X86_INS_VPADDUSW,
+ X86_INS_VPADDW,
+ X86_INS_VPALIGNR,
+ X86_INS_VPANDD,
+ X86_INS_VPANDND,
+ X86_INS_VPANDNQ,
+ X86_INS_VPANDN,
+ X86_INS_VPANDQ,
+ X86_INS_VPAND,
+ X86_INS_VPAVGB,
+ X86_INS_VPAVGW,
+ X86_INS_VPBLENDD,
+ X86_INS_VPBLENDMB,
+ X86_INS_VPBLENDMD,
+ X86_INS_VPBLENDMQ,
+ X86_INS_VPBLENDMW,
+ X86_INS_VPBLENDVB,
+ X86_INS_VPBLENDW,
+ X86_INS_VPBROADCASTB,
+ X86_INS_VPBROADCASTD,
+ X86_INS_VPBROADCASTMB2Q,
+ X86_INS_VPBROADCASTMW2D,
+ X86_INS_VPBROADCASTQ,
+ X86_INS_VPBROADCASTW,
+ X86_INS_VPCLMULQDQ,
+ X86_INS_VPCMOV,
+ X86_INS_VPCMPB,
+ X86_INS_VPCMPD,
+ X86_INS_VPCMPEQB,
+ X86_INS_VPCMPEQD,
+ X86_INS_VPCMPEQQ,
+ X86_INS_VPCMPEQW,
+ X86_INS_VPCMPESTRI,
+ X86_INS_VPCMPESTRM,
+ X86_INS_VPCMPGTB,
+ X86_INS_VPCMPGTD,
+ X86_INS_VPCMPGTQ,
+ X86_INS_VPCMPGTW,
+ X86_INS_VPCMPISTRI,
+ X86_INS_VPCMPISTRM,
+ X86_INS_VPCMPQ,
+ X86_INS_VPCMPUB,
+ X86_INS_VPCMPUD,
+ X86_INS_VPCMPUQ,
+ X86_INS_VPCMPUW,
+ X86_INS_VPCMPW,
+ X86_INS_VPCOMB,
+ X86_INS_VPCOMD,
+ X86_INS_VPCOMPRESSD,
+ X86_INS_VPCOMPRESSQ,
+ X86_INS_VPCOMQ,
+ X86_INS_VPCOMUB,
+ X86_INS_VPCOMUD,
+ X86_INS_VPCOMUQ,
+ X86_INS_VPCOMUW,
+ X86_INS_VPCOMW,
+ X86_INS_VPCONFLICTD,
+ X86_INS_VPCONFLICTQ,
+ X86_INS_VPERM2F128,
+ X86_INS_VPERM2I128,
+ X86_INS_VPERMD,
+ X86_INS_VPERMI2D,
+ X86_INS_VPERMI2PD,
+ X86_INS_VPERMI2PS,
+ X86_INS_VPERMI2Q,
+ X86_INS_VPERMIL2PD,
+ X86_INS_VPERMIL2PS,
+ X86_INS_VPERMILPD,
+ X86_INS_VPERMILPS,
+ X86_INS_VPERMPD,
+ X86_INS_VPERMPS,
+ X86_INS_VPERMQ,
+ X86_INS_VPERMT2D,
+ X86_INS_VPERMT2PD,
+ X86_INS_VPERMT2PS,
+ X86_INS_VPERMT2Q,
+ X86_INS_VPEXPANDD,
+ X86_INS_VPEXPANDQ,
+ X86_INS_VPEXTRB,
+ X86_INS_VPEXTRD,
+ X86_INS_VPEXTRQ,
+ X86_INS_VPEXTRW,
+ X86_INS_VPGATHERDD,
+ X86_INS_VPGATHERDQ,
+ X86_INS_VPGATHERQD,
+ X86_INS_VPGATHERQQ,
+ X86_INS_VPHADDBD,
+ X86_INS_VPHADDBQ,
+ X86_INS_VPHADDBW,
+ X86_INS_VPHADDDQ,
+ X86_INS_VPHADDD,
+ X86_INS_VPHADDSW,
+ X86_INS_VPHADDUBD,
+ X86_INS_VPHADDUBQ,
+ X86_INS_VPHADDUBW,
+ X86_INS_VPHADDUDQ,
+ X86_INS_VPHADDUWD,
+ X86_INS_VPHADDUWQ,
+ X86_INS_VPHADDWD,
+ X86_INS_VPHADDWQ,
+ X86_INS_VPHADDW,
+ X86_INS_VPHMINPOSUW,
+ X86_INS_VPHSUBBW,
+ X86_INS_VPHSUBDQ,
+ X86_INS_VPHSUBD,
+ X86_INS_VPHSUBSW,
+ X86_INS_VPHSUBWD,
+ X86_INS_VPHSUBW,
+ X86_INS_VPINSRB,
+ X86_INS_VPINSRD,
+ X86_INS_VPINSRQ,
+ X86_INS_VPINSRW,
+ X86_INS_VPLZCNTD,
+ X86_INS_VPLZCNTQ,
+ X86_INS_VPMACSDD,
+ X86_INS_VPMACSDQH,
+ X86_INS_VPMACSDQL,
+ X86_INS_VPMACSSDD,
+ X86_INS_VPMACSSDQH,
+ X86_INS_VPMACSSDQL,
+ X86_INS_VPMACSSWD,
+ X86_INS_VPMACSSWW,
+ X86_INS_VPMACSWD,
+ X86_INS_VPMACSWW,
+ X86_INS_VPMADCSSWD,
+ X86_INS_VPMADCSWD,
+ X86_INS_VPMADDUBSW,
+ X86_INS_VPMADDWD,
+ X86_INS_VPMASKMOVD,
+ X86_INS_VPMASKMOVQ,
+ X86_INS_VPMAXSB,
+ X86_INS_VPMAXSD,
+ X86_INS_VPMAXSQ,
+ X86_INS_VPMAXSW,
+ X86_INS_VPMAXUB,
+ X86_INS_VPMAXUD,
+ X86_INS_VPMAXUQ,
+ X86_INS_VPMAXUW,
+ X86_INS_VPMINSB,
+ X86_INS_VPMINSD,
+ X86_INS_VPMINSQ,
+ X86_INS_VPMINSW,
+ X86_INS_VPMINUB,
+ X86_INS_VPMINUD,
+ X86_INS_VPMINUQ,
+ X86_INS_VPMINUW,
+ X86_INS_VPMOVDB,
+ X86_INS_VPMOVDW,
+ X86_INS_VPMOVM2B,
+ X86_INS_VPMOVM2D,
+ X86_INS_VPMOVM2Q,
+ X86_INS_VPMOVM2W,
+ X86_INS_VPMOVMSKB,
+ X86_INS_VPMOVQB,
+ X86_INS_VPMOVQD,
+ X86_INS_VPMOVQW,
+ X86_INS_VPMOVSDB,
+ X86_INS_VPMOVSDW,
+ X86_INS_VPMOVSQB,
+ X86_INS_VPMOVSQD,
+ X86_INS_VPMOVSQW,
+ X86_INS_VPMOVSXBD,
+ X86_INS_VPMOVSXBQ,
+ X86_INS_VPMOVSXBW,
+ X86_INS_VPMOVSXDQ,
+ X86_INS_VPMOVSXWD,
+ X86_INS_VPMOVSXWQ,
+ X86_INS_VPMOVUSDB,
+ X86_INS_VPMOVUSDW,
+ X86_INS_VPMOVUSQB,
+ X86_INS_VPMOVUSQD,
+ X86_INS_VPMOVUSQW,
+ X86_INS_VPMOVZXBD,
+ X86_INS_VPMOVZXBQ,
+ X86_INS_VPMOVZXBW,
+ X86_INS_VPMOVZXDQ,
+ X86_INS_VPMOVZXWD,
+ X86_INS_VPMOVZXWQ,
+ X86_INS_VPMULDQ,
+ X86_INS_VPMULHRSW,
+ X86_INS_VPMULHUW,
+ X86_INS_VPMULHW,
+ X86_INS_VPMULLD,
+ X86_INS_VPMULLQ,
+ X86_INS_VPMULLW,
+ X86_INS_VPMULUDQ,
+ X86_INS_VPORD,
+ X86_INS_VPORQ,
+ X86_INS_VPOR,
+ X86_INS_VPPERM,
+ X86_INS_VPROTB,
+ X86_INS_VPROTD,
+ X86_INS_VPROTQ,
+ X86_INS_VPROTW,
+ X86_INS_VPSADBW,
+ X86_INS_VPSCATTERDD,
+ X86_INS_VPSCATTERDQ,
+ X86_INS_VPSCATTERQD,
+ X86_INS_VPSCATTERQQ,
+ X86_INS_VPSHAB,
+ X86_INS_VPSHAD,
+ X86_INS_VPSHAQ,
+ X86_INS_VPSHAW,
+ X86_INS_VPSHLB,
+ X86_INS_VPSHLD,
+ X86_INS_VPSHLQ,
+ X86_INS_VPSHLW,
+ X86_INS_VPSHUFB,
+ X86_INS_VPSHUFD,
+ X86_INS_VPSHUFHW,
+ X86_INS_VPSHUFLW,
+ X86_INS_VPSIGNB,
+ X86_INS_VPSIGND,
+ X86_INS_VPSIGNW,
+ X86_INS_VPSLLDQ,
+ X86_INS_VPSLLD,
+ X86_INS_VPSLLQ,
+ X86_INS_VPSLLVD,
+ X86_INS_VPSLLVQ,
+ X86_INS_VPSLLW,
+ X86_INS_VPSRAD,
+ X86_INS_VPSRAQ,
+ X86_INS_VPSRAVD,
+ X86_INS_VPSRAVQ,
+ X86_INS_VPSRAW,
+ X86_INS_VPSRLDQ,
+ X86_INS_VPSRLD,
+ X86_INS_VPSRLQ,
+ X86_INS_VPSRLVD,
+ X86_INS_VPSRLVQ,
+ X86_INS_VPSRLW,
+ X86_INS_VPSUBB,
+ X86_INS_VPSUBD,
+ X86_INS_VPSUBQ,
+ X86_INS_VPSUBSB,
+ X86_INS_VPSUBSW,
+ X86_INS_VPSUBUSB,
+ X86_INS_VPSUBUSW,
+ X86_INS_VPSUBW,
+ X86_INS_VPTESTMD,
+ X86_INS_VPTESTMQ,
+ X86_INS_VPTESTNMD,
+ X86_INS_VPTESTNMQ,
+ X86_INS_VPTEST,
+ X86_INS_VPUNPCKHBW,
+ X86_INS_VPUNPCKHDQ,
+ X86_INS_VPUNPCKHQDQ,
+ X86_INS_VPUNPCKHWD,
+ X86_INS_VPUNPCKLBW,
+ X86_INS_VPUNPCKLDQ,
+ X86_INS_VPUNPCKLQDQ,
+ X86_INS_VPUNPCKLWD,
+ X86_INS_VPXORD,
+ X86_INS_VPXORQ,
+ X86_INS_VPXOR,
+ X86_INS_VRCP14PD,
+ X86_INS_VRCP14PS,
+ X86_INS_VRCP14SD,
+ X86_INS_VRCP14SS,
+ X86_INS_VRCP28PD,
+ X86_INS_VRCP28PS,
+ X86_INS_VRCP28SD,
+ X86_INS_VRCP28SS,
+ X86_INS_VRCPPS,
+ X86_INS_VRCPSS,
+ X86_INS_VRNDSCALEPD,
+ X86_INS_VRNDSCALEPS,
+ X86_INS_VRNDSCALESD,
+ X86_INS_VRNDSCALESS,
+ X86_INS_VROUNDPD,
+ X86_INS_VROUNDPS,
+ X86_INS_VROUNDSD,
+ X86_INS_VROUNDSS,
+ X86_INS_VRSQRT14PD,
+ X86_INS_VRSQRT14PS,
+ X86_INS_VRSQRT14SD,
+ X86_INS_VRSQRT14SS,
+ X86_INS_VRSQRT28PD,
+ X86_INS_VRSQRT28PS,
+ X86_INS_VRSQRT28SD,
+ X86_INS_VRSQRT28SS,
+ X86_INS_VRSQRTPS,
+ X86_INS_VRSQRTSS,
+ X86_INS_VSCATTERDPD,
+ X86_INS_VSCATTERDPS,
+ X86_INS_VSCATTERPF0DPD,
+ X86_INS_VSCATTERPF0DPS,
+ X86_INS_VSCATTERPF0QPD,
+ X86_INS_VSCATTERPF0QPS,
+ X86_INS_VSCATTERPF1DPD,
+ X86_INS_VSCATTERPF1DPS,
+ X86_INS_VSCATTERPF1QPD,
+ X86_INS_VSCATTERPF1QPS,
+ X86_INS_VSCATTERQPD,
+ X86_INS_VSCATTERQPS,
+ X86_INS_VSHUFPD,
+ X86_INS_VSHUFPS,
+ X86_INS_VSQRTPD,
+ X86_INS_VSQRTPS,
+ X86_INS_VSQRTSD,
+ X86_INS_VSQRTSS,
+ X86_INS_VSTMXCSR,
+ X86_INS_VSUBPD,
+ X86_INS_VSUBPS,
+ X86_INS_VSUBSD,
+ X86_INS_VSUBSS,
+ X86_INS_VTESTPD,
+ X86_INS_VTESTPS,
+ X86_INS_VUNPCKHPD,
+ X86_INS_VUNPCKHPS,
+ X86_INS_VUNPCKLPD,
+ X86_INS_VUNPCKLPS,
+ X86_INS_VZEROALL,
+ X86_INS_VZEROUPPER,
+ X86_INS_WAIT,
+ X86_INS_WBINVD,
+ X86_INS_WRFSBASE,
+ X86_INS_WRGSBASE,
+ X86_INS_WRMSR,
+ X86_INS_XABORT,
+ X86_INS_XACQUIRE,
+ X86_INS_XBEGIN,
+ X86_INS_XCHG,
+ X86_INS_XCRYPTCBC,
+ X86_INS_XCRYPTCFB,
+ X86_INS_XCRYPTCTR,
+ X86_INS_XCRYPTECB,
+ X86_INS_XCRYPTOFB,
+ X86_INS_XEND,
+ X86_INS_XGETBV,
+ X86_INS_XLATB,
+ X86_INS_XRELEASE,
+ X86_INS_XRSTOR,
+ X86_INS_XRSTOR64,
+ X86_INS_XRSTORS,
+ X86_INS_XRSTORS64,
+ X86_INS_XSAVE,
+ X86_INS_XSAVE64,
+ X86_INS_XSAVEC,
+ X86_INS_XSAVEC64,
+ X86_INS_XSAVEOPT,
+ X86_INS_XSAVEOPT64,
+ X86_INS_XSAVES,
+ X86_INS_XSAVES64,
+ X86_INS_XSETBV,
+ X86_INS_XSHA1,
+ X86_INS_XSHA256,
+ X86_INS_XSTORE,
+ X86_INS_XTEST,
+ X86_INS_FDISI8087_NOP,
+ X86_INS_FENI8087_NOP,
+
+ // pseudo instructions
+ X86_INS_CMPSS,
+ X86_INS_CMPEQSS,
+ X86_INS_CMPLTSS,
+ X86_INS_CMPLESS,
+ X86_INS_CMPUNORDSS,
+ X86_INS_CMPNEQSS,
+ X86_INS_CMPNLTSS,
+ X86_INS_CMPNLESS,
+ X86_INS_CMPORDSS,
+
+ X86_INS_CMPSD,
+ X86_INS_CMPEQSD,
+ X86_INS_CMPLTSD,
+ X86_INS_CMPLESD,
+ X86_INS_CMPUNORDSD,
+ X86_INS_CMPNEQSD,
+ X86_INS_CMPNLTSD,
+ X86_INS_CMPNLESD,
+ X86_INS_CMPORDSD,
+
+ X86_INS_CMPPS,
+ X86_INS_CMPEQPS,
+ X86_INS_CMPLTPS,
+ X86_INS_CMPLEPS,
+ X86_INS_CMPUNORDPS,
+ X86_INS_CMPNEQPS,
+ X86_INS_CMPNLTPS,
+ X86_INS_CMPNLEPS,
+ X86_INS_CMPORDPS,
+
+ X86_INS_CMPPD,
+ X86_INS_CMPEQPD,
+ X86_INS_CMPLTPD,
+ X86_INS_CMPLEPD,
+ X86_INS_CMPUNORDPD,
+ X86_INS_CMPNEQPD,
+ X86_INS_CMPNLTPD,
+ X86_INS_CMPNLEPD,
+ X86_INS_CMPORDPD,
+
+ X86_INS_VCMPSS,
+ X86_INS_VCMPEQSS,
+ X86_INS_VCMPLTSS,
+ X86_INS_VCMPLESS,
+ X86_INS_VCMPUNORDSS,
+ X86_INS_VCMPNEQSS,
+ X86_INS_VCMPNLTSS,
+ X86_INS_VCMPNLESS,
+ X86_INS_VCMPORDSS,
+ X86_INS_VCMPEQ_UQSS,
+ X86_INS_VCMPNGESS,
+ X86_INS_VCMPNGTSS,
+ X86_INS_VCMPFALSESS,
+ X86_INS_VCMPNEQ_OQSS,
+ X86_INS_VCMPGESS,
+ X86_INS_VCMPGTSS,
+ X86_INS_VCMPTRUESS,
+ X86_INS_VCMPEQ_OSSS,
+ X86_INS_VCMPLT_OQSS,
+ X86_INS_VCMPLE_OQSS,
+ X86_INS_VCMPUNORD_SSS,
+ X86_INS_VCMPNEQ_USSS,
+ X86_INS_VCMPNLT_UQSS,
+ X86_INS_VCMPNLE_UQSS,
+ X86_INS_VCMPORD_SSS,
+ X86_INS_VCMPEQ_USSS,
+ X86_INS_VCMPNGE_UQSS,
+ X86_INS_VCMPNGT_UQSS,
+ X86_INS_VCMPFALSE_OSSS,
+ X86_INS_VCMPNEQ_OSSS,
+ X86_INS_VCMPGE_OQSS,
+ X86_INS_VCMPGT_OQSS,
+ X86_INS_VCMPTRUE_USSS,
+
+ X86_INS_VCMPSD,
+ X86_INS_VCMPEQSD,
+ X86_INS_VCMPLTSD,
+ X86_INS_VCMPLESD,
+ X86_INS_VCMPUNORDSD,
+ X86_INS_VCMPNEQSD,
+ X86_INS_VCMPNLTSD,
+ X86_INS_VCMPNLESD,
+ X86_INS_VCMPORDSD,
+ X86_INS_VCMPEQ_UQSD,
+ X86_INS_VCMPNGESD,
+ X86_INS_VCMPNGTSD,
+ X86_INS_VCMPFALSESD,
+ X86_INS_VCMPNEQ_OQSD,
+ X86_INS_VCMPGESD,
+ X86_INS_VCMPGTSD,
+ X86_INS_VCMPTRUESD,
+ X86_INS_VCMPEQ_OSSD,
+ X86_INS_VCMPLT_OQSD,
+ X86_INS_VCMPLE_OQSD,
+ X86_INS_VCMPUNORD_SSD,
+ X86_INS_VCMPNEQ_USSD,
+ X86_INS_VCMPNLT_UQSD,
+ X86_INS_VCMPNLE_UQSD,
+ X86_INS_VCMPORD_SSD,
+ X86_INS_VCMPEQ_USSD,
+ X86_INS_VCMPNGE_UQSD,
+ X86_INS_VCMPNGT_UQSD,
+ X86_INS_VCMPFALSE_OSSD,
+ X86_INS_VCMPNEQ_OSSD,
+ X86_INS_VCMPGE_OQSD,
+ X86_INS_VCMPGT_OQSD,
+ X86_INS_VCMPTRUE_USSD,
+
+ X86_INS_VCMPPS,
+ X86_INS_VCMPEQPS,
+ X86_INS_VCMPLTPS,
+ X86_INS_VCMPLEPS,
+ X86_INS_VCMPUNORDPS,
+ X86_INS_VCMPNEQPS,
+ X86_INS_VCMPNLTPS,
+ X86_INS_VCMPNLEPS,
+ X86_INS_VCMPORDPS,
+ X86_INS_VCMPEQ_UQPS,
+ X86_INS_VCMPNGEPS,
+ X86_INS_VCMPNGTPS,
+ X86_INS_VCMPFALSEPS,
+ X86_INS_VCMPNEQ_OQPS,
+ X86_INS_VCMPGEPS,
+ X86_INS_VCMPGTPS,
+ X86_INS_VCMPTRUEPS,
+ X86_INS_VCMPEQ_OSPS,
+ X86_INS_VCMPLT_OQPS,
+ X86_INS_VCMPLE_OQPS,
+ X86_INS_VCMPUNORD_SPS,
+ X86_INS_VCMPNEQ_USPS,
+ X86_INS_VCMPNLT_UQPS,
+ X86_INS_VCMPNLE_UQPS,
+ X86_INS_VCMPORD_SPS,
+ X86_INS_VCMPEQ_USPS,
+ X86_INS_VCMPNGE_UQPS,
+ X86_INS_VCMPNGT_UQPS,
+ X86_INS_VCMPFALSE_OSPS,
+ X86_INS_VCMPNEQ_OSPS,
+ X86_INS_VCMPGE_OQPS,
+ X86_INS_VCMPGT_OQPS,
+ X86_INS_VCMPTRUE_USPS,
+
+ X86_INS_VCMPPD,
+ X86_INS_VCMPEQPD,
+ X86_INS_VCMPLTPD,
+ X86_INS_VCMPLEPD,
+ X86_INS_VCMPUNORDPD,
+ X86_INS_VCMPNEQPD,
+ X86_INS_VCMPNLTPD,
+ X86_INS_VCMPNLEPD,
+ X86_INS_VCMPORDPD,
+ X86_INS_VCMPEQ_UQPD,
+ X86_INS_VCMPNGEPD,
+ X86_INS_VCMPNGTPD,
+ X86_INS_VCMPFALSEPD,
+ X86_INS_VCMPNEQ_OQPD,
+ X86_INS_VCMPGEPD,
+ X86_INS_VCMPGTPD,
+ X86_INS_VCMPTRUEPD,
+ X86_INS_VCMPEQ_OSPD,
+ X86_INS_VCMPLT_OQPD,
+ X86_INS_VCMPLE_OQPD,
+ X86_INS_VCMPUNORD_SPD,
+ X86_INS_VCMPNEQ_USPD,
+ X86_INS_VCMPNLT_UQPD,
+ X86_INS_VCMPNLE_UQPD,
+ X86_INS_VCMPORD_SPD,
+ X86_INS_VCMPEQ_USPD,
+ X86_INS_VCMPNGE_UQPD,
+ X86_INS_VCMPNGT_UQPD,
+ X86_INS_VCMPFALSE_OSPD,
+ X86_INS_VCMPNEQ_OSPD,
+ X86_INS_VCMPGE_OQPD,
+ X86_INS_VCMPGT_OQPD,
+ X86_INS_VCMPTRUE_USPD,
+
+ X86_INS_UD0,
+ X86_INS_ENDBR32,
+ X86_INS_ENDBR64,
+
+ X86_INS_ENDING, // mark the end of the list of insn
+} x86_insn;
+
+/// Group of X86 instructions
+typedef enum x86_insn_group {
+ X86_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ X86_GRP_JUMP, ///< = CS_GRP_JUMP
+ // all call instructions
+ X86_GRP_CALL, ///< = CS_GRP_CALL
+ // all return instructions
+ X86_GRP_RET, ///< = CS_GRP_RET
+ // all interrupt instructions (int+syscall)
+ X86_GRP_INT, ///< = CS_GRP_INT
+ // all interrupt return instructions
+ X86_GRP_IRET, ///< = CS_GRP_IRET
+ // all privileged instructions
+ X86_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE
+ // all relative branching instructions
+ X86_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+ // Architecture-specific groups
+ X86_GRP_VM = 128, ///< all virtualization instructions (VT-x + AMD-V)
+ X86_GRP_3DNOW,
+ X86_GRP_AES,
+ X86_GRP_ADX,
+ X86_GRP_AVX,
+ X86_GRP_AVX2,
+ X86_GRP_AVX512,
+ X86_GRP_BMI,
+ X86_GRP_BMI2,
+ X86_GRP_CMOV,
+ X86_GRP_F16C,
+ X86_GRP_FMA,
+ X86_GRP_FMA4,
+ X86_GRP_FSGSBASE,
+ X86_GRP_HLE,
+ X86_GRP_MMX,
+ X86_GRP_MODE32,
+ X86_GRP_MODE64,
+ X86_GRP_RTM,
+ X86_GRP_SHA,
+ X86_GRP_SSE1,
+ X86_GRP_SSE2,
+ X86_GRP_SSE3,
+ X86_GRP_SSE41,
+ X86_GRP_SSE42,
+ X86_GRP_SSE4A,
+ X86_GRP_SSSE3,
+ X86_GRP_PCLMUL,
+ X86_GRP_XOP,
+ X86_GRP_CDI,
+ X86_GRP_ERI,
+ X86_GRP_TBM,
+ X86_GRP_16BITMODE,
+ X86_GRP_NOT64BITMODE,
+ X86_GRP_SGX,
+ X86_GRP_DQI,
+ X86_GRP_BWI,
+ X86_GRP_PFI,
+ X86_GRP_VLX,
+ X86_GRP_SMAP,
+ X86_GRP_NOVLX,
+ X86_GRP_FPU,
+
+ X86_GRP_ENDING
+} x86_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/xcore.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/xcore.h
new file mode 100644
index 00000000..6db1f246
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/capstone/xcore.h
@@ -0,0 +1,235 @@
+#ifndef CAPSTONE_XCORE_H
+#define CAPSTONE_XCORE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh , 2014-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Operand type for instruction's operands
+typedef enum xcore_op_type {
+ XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+ XCORE_OP_REG, ///< = CS_OP_REG (Register operand).
+ XCORE_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+ XCORE_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} xcore_op_type;
+
+/// XCore registers
+typedef enum xcore_reg {
+ XCORE_REG_INVALID = 0,
+
+ XCORE_REG_CP,
+ XCORE_REG_DP,
+ XCORE_REG_LR,
+ XCORE_REG_SP,
+ XCORE_REG_R0,
+ XCORE_REG_R1,
+ XCORE_REG_R2,
+ XCORE_REG_R3,
+ XCORE_REG_R4,
+ XCORE_REG_R5,
+ XCORE_REG_R6,
+ XCORE_REG_R7,
+ XCORE_REG_R8,
+ XCORE_REG_R9,
+ XCORE_REG_R10,
+ XCORE_REG_R11,
+
+ // pseudo registers
+ XCORE_REG_PC, ///< pc
+
+ // internal thread registers
+ // see The-XMOS-XS1-Architecture(X7879A).pdf
+ XCORE_REG_SCP, ///< save pc
+ XCORE_REG_SSR, //< save status
+ XCORE_REG_ET, //< exception type
+ XCORE_REG_ED, //< exception data
+ XCORE_REG_SED, //< save exception data
+ XCORE_REG_KEP, //< kernel entry pointer
+ XCORE_REG_KSP, //< kernel stack pointer
+ XCORE_REG_ID, //< thread ID
+
+ XCORE_REG_ENDING, // <-- mark the end of the list of registers
+} xcore_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with XCORE_OP_MEM operand type above
+typedef struct xcore_op_mem {
+ uint8_t base; ///< base register, can be safely interpreted as
+ ///< a value of type `xcore_reg`, but it is only
+ ///< one byte wide
+ uint8_t index; ///< index register, same conditions apply here
+ int32_t disp; ///< displacement/offset value
+ int direct; ///< +1: forward, -1: backward
+} xcore_op_mem;
+
+/// Instruction operand
+typedef struct cs_xcore_op {
+ xcore_op_type type; ///< operand type
+ union {
+ xcore_reg reg; ///< register value for REG operand
+ int32_t imm; ///< immediate value for IMM operand
+ xcore_op_mem mem; ///< base/disp value for MEM operand
+ };
+} cs_xcore_op;
+
+/// Instruction structure
+typedef struct cs_xcore {
+ /// Number of operands of this instruction,
+ /// or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_xcore_op operands[8]; ///< operands for this instruction.
+} cs_xcore;
+
+/// XCore instruction
+typedef enum xcore_insn {
+ XCORE_INS_INVALID = 0,
+
+ XCORE_INS_ADD,
+ XCORE_INS_ANDNOT,
+ XCORE_INS_AND,
+ XCORE_INS_ASHR,
+ XCORE_INS_BAU,
+ XCORE_INS_BITREV,
+ XCORE_INS_BLA,
+ XCORE_INS_BLAT,
+ XCORE_INS_BL,
+ XCORE_INS_BF,
+ XCORE_INS_BT,
+ XCORE_INS_BU,
+ XCORE_INS_BRU,
+ XCORE_INS_BYTEREV,
+ XCORE_INS_CHKCT,
+ XCORE_INS_CLRE,
+ XCORE_INS_CLRPT,
+ XCORE_INS_CLRSR,
+ XCORE_INS_CLZ,
+ XCORE_INS_CRC8,
+ XCORE_INS_CRC32,
+ XCORE_INS_DCALL,
+ XCORE_INS_DENTSP,
+ XCORE_INS_DGETREG,
+ XCORE_INS_DIVS,
+ XCORE_INS_DIVU,
+ XCORE_INS_DRESTSP,
+ XCORE_INS_DRET,
+ XCORE_INS_ECALLF,
+ XCORE_INS_ECALLT,
+ XCORE_INS_EDU,
+ XCORE_INS_EEF,
+ XCORE_INS_EET,
+ XCORE_INS_EEU,
+ XCORE_INS_ENDIN,
+ XCORE_INS_ENTSP,
+ XCORE_INS_EQ,
+ XCORE_INS_EXTDP,
+ XCORE_INS_EXTSP,
+ XCORE_INS_FREER,
+ XCORE_INS_FREET,
+ XCORE_INS_GETD,
+ XCORE_INS_GET,
+ XCORE_INS_GETN,
+ XCORE_INS_GETR,
+ XCORE_INS_GETSR,
+ XCORE_INS_GETST,
+ XCORE_INS_GETTS,
+ XCORE_INS_INCT,
+ XCORE_INS_INIT,
+ XCORE_INS_INPW,
+ XCORE_INS_INSHR,
+ XCORE_INS_INT,
+ XCORE_INS_IN,
+ XCORE_INS_KCALL,
+ XCORE_INS_KENTSP,
+ XCORE_INS_KRESTSP,
+ XCORE_INS_KRET,
+ XCORE_INS_LADD,
+ XCORE_INS_LD16S,
+ XCORE_INS_LD8U,
+ XCORE_INS_LDA16,
+ XCORE_INS_LDAP,
+ XCORE_INS_LDAW,
+ XCORE_INS_LDC,
+ XCORE_INS_LDW,
+ XCORE_INS_LDIVU,
+ XCORE_INS_LMUL,
+ XCORE_INS_LSS,
+ XCORE_INS_LSUB,
+ XCORE_INS_LSU,
+ XCORE_INS_MACCS,
+ XCORE_INS_MACCU,
+ XCORE_INS_MJOIN,
+ XCORE_INS_MKMSK,
+ XCORE_INS_MSYNC,
+ XCORE_INS_MUL,
+ XCORE_INS_NEG,
+ XCORE_INS_NOT,
+ XCORE_INS_OR,
+ XCORE_INS_OUTCT,
+ XCORE_INS_OUTPW,
+ XCORE_INS_OUTSHR,
+ XCORE_INS_OUTT,
+ XCORE_INS_OUT,
+ XCORE_INS_PEEK,
+ XCORE_INS_REMS,
+ XCORE_INS_REMU,
+ XCORE_INS_RETSP,
+ XCORE_INS_SETCLK,
+ XCORE_INS_SET,
+ XCORE_INS_SETC,
+ XCORE_INS_SETD,
+ XCORE_INS_SETEV,
+ XCORE_INS_SETN,
+ XCORE_INS_SETPSC,
+ XCORE_INS_SETPT,
+ XCORE_INS_SETRDY,
+ XCORE_INS_SETSR,
+ XCORE_INS_SETTW,
+ XCORE_INS_SETV,
+ XCORE_INS_SEXT,
+ XCORE_INS_SHL,
+ XCORE_INS_SHR,
+ XCORE_INS_SSYNC,
+ XCORE_INS_ST16,
+ XCORE_INS_ST8,
+ XCORE_INS_STW,
+ XCORE_INS_SUB,
+ XCORE_INS_SYNCR,
+ XCORE_INS_TESTCT,
+ XCORE_INS_TESTLCL,
+ XCORE_INS_TESTWCT,
+ XCORE_INS_TSETMR,
+ XCORE_INS_START,
+ XCORE_INS_WAITEF,
+ XCORE_INS_WAITET,
+ XCORE_INS_WAITEU,
+ XCORE_INS_XOR,
+ XCORE_INS_ZEXT,
+
+ XCORE_INS_ENDING, // <-- mark the end of the list of instructions
+} xcore_insn;
+
+/// Group of XCore instructions
+typedef enum xcore_insn_group {
+ XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+ // Generic groups
+ // all jump instructions (conditional+direct+indirect jumps)
+ XCORE_GRP_JUMP, ///< = CS_GRP_JUMP
+
+ XCORE_GRP_ENDING, // <-- mark the end of the list of groups
+} xcore_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/platform.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/platform.h
new file mode 100644
index 00000000..b0d1a2d8
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/platform.h
@@ -0,0 +1,110 @@
+/* Capstone Disassembly Engine */
+/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
+
+#ifndef CAPSTONE_PLATFORM_H
+#define CAPSTONE_PLATFORM_H
+
+// handle C99 issue (for pre-2013 VisualStudio)
+#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+// MSVC
+
+// stdbool.h
+#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)
+// this system does not have stdbool.h
+#ifndef __cplusplus
+typedef unsigned char bool;
+#define false 0
+#define true 1
+#endif
+
+#else
+// VisualStudio 2013+ -> C99 is supported
+#include
+#endif
+
+#else
+// not MSVC -> C99 is supported
+#include
+#endif
+
+
+// handle C99 issue (for pre-2013 VisualStudio)
+#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
+// this system does not have inttypes.h
+
+#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
+// this system does not have stdint.h
+typedef signed char int8_t;
+typedef signed short int16_t;
+typedef signed int int32_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef signed long long int64_t;
+typedef unsigned long long uint64_t;
+
+#define INT8_MIN (-127i8 - 1)
+#define INT16_MIN (-32767i16 - 1)
+#define INT32_MIN (-2147483647i32 - 1)
+#define INT64_MIN (-9223372036854775807i64 - 1)
+#define INT8_MAX 127i8
+#define INT16_MAX 32767i16
+#define INT32_MAX 2147483647i32
+#define INT64_MAX 9223372036854775807i64
+#define UINT8_MAX 0xffui8
+#define UINT16_MAX 0xffffui16
+#define UINT32_MAX 0xffffffffui32
+#define UINT64_MAX 0xffffffffffffffffui64
+#endif
+
+#define __PRI_8_LENGTH_MODIFIER__ "hh"
+#define __PRI_64_LENGTH_MODIFIER__ "ll"
+
+#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
+#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
+#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
+#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
+#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
+#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
+
+#define PRId16 "hd"
+#define PRIi16 "hi"
+#define PRIo16 "ho"
+#define PRIu16 "hu"
+#define PRIx16 "hx"
+#define PRIX16 "hX"
+
+#if defined(_MSC_VER) && _MSC_VER <= 1700
+#define PRId32 "ld"
+#define PRIi32 "li"
+#define PRIo32 "lo"
+#define PRIu32 "lu"
+#define PRIx32 "lx"
+#define PRIX32 "lX"
+#else // OSX
+#define PRId32 "d"
+#define PRIi32 "i"
+#define PRIo32 "o"
+#define PRIu32 "u"
+#define PRIx32 "x"
+#define PRIX32 "X"
+#endif
+
+#if defined(_MSC_VER) && _MSC_VER <= 1700
+// redefine functions from inttypes.h used in cstool
+#define strtoull _strtoui64
+#endif
+
+#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
+#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
+#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
+#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
+#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
+#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
+
+#else
+// this system has inttypes.h by default
+#include
+#endif
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/windowsce/intrin.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/windowsce/intrin.h
new file mode 100644
index 00000000..fde4bde5
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/windowsce/intrin.h
@@ -0,0 +1,12 @@
+
+#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(__INTRIN_H_) && !defined(_INTRIN)
+#define _STDINT
+
+#ifdef _M_ARM
+#include
+#if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
+#include
+#endif
+#endif // _M_ARM
+
+#endif
diff --git a/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/windowsce/stdint.h b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/windowsce/stdint.h
new file mode 100644
index 00000000..014a1632
--- /dev/null
+++ b/patch_kernel_root/3rdparty/capstone-4.0.2-win64/include/windowsce/stdint.h
@@ -0,0 +1,133 @@
+
+#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(_STDINT_H_) && !defined(_STDINT)
+#define _STDINT
+
+typedef __int8
+ int8_t,
+ int_least8_t;
+
+typedef __int16
+ int16_t,
+ int_least16_t;
+
+typedef __int32
+ int32_t,
+ int_least32_t,
+ int_fast8_t,
+ int_fast16_t,
+ int_fast32_t;
+
+typedef __int64
+ int64_t,
+ intmax_t,
+ int_least64_t,
+ int_fast64_t;
+
+typedef unsigned __int8
+ uint8_t,
+ uint_least8_t;
+
+typedef unsigned __int16
+ uint16_t,
+ uint_least16_t;
+
+typedef unsigned __int32
+ uint32_t,
+ uint_least32_t,
+ uint_fast8_t,
+ uint_fast16_t,
+ uint_fast32_t;
+
+typedef unsigned __int64
+ uint64_t,
+ uintmax_t,
+ uint_least64_t,
+ uint_fast64_t;
+
+#ifndef _INTPTR_T_DEFINED
+#define _INTPTR_T_DEFINED
+typedef __int32 intptr_t;
+#endif
+
+#ifndef _UINTPTR_T_DEFINED
+#define _UINTPTR_T_DEFINED
+typedef unsigned __int32 uintptr_t;
+#endif
+
+#define INT8_MIN (-127i8 - 1)
+#define INT16_MIN (-32767i16 - 1)
+#define INT32_MIN (-2147483647i32 - 1)
+#define INT64_MIN (-9223372036854775807i64 - 1)
+#define INT8_MAX 127i8
+#define INT16_MAX 32767i16
+#define INT32_MAX 2147483647i32
+#define INT64_MAX 9223372036854775807i64
+#define UINT8_MAX 0xffui8
+#define UINT16_MAX 0xffffui16
+#define UINT32_MAX 0xffffffffui32
+#define UINT64_MAX 0xffffffffffffffffui64
+
+#define INT_LEAST8_MIN INT8_MIN
+#define INT_LEAST16_MIN INT16_MIN
+#define INT_LEAST32_MIN INT32_MIN
+#define INT_LEAST64_MIN INT64_MIN
+#define INT_LEAST8_MAX INT8_MAX
+#define INT_LEAST16_MAX INT16_MAX
+#define INT_LEAST32_MAX INT32_MAX
+#define INT_LEAST64_MAX INT64_MAX
+#define UINT_LEAST8_MAX UINT8_MAX
+#define UINT_LEAST16_MAX UINT16_MAX
+#define UINT_LEAST32_MAX UINT32_MAX
+#define UINT_LEAST64_MAX UINT64_MAX
+
+#define INT_FAST8_MIN INT8_MIN
+#define INT_FAST16_MIN INT32_MIN
+#define INT_FAST32_MIN INT32_MIN
+#define INT_FAST64_MIN INT64_MIN
+#define INT_FAST8_MAX INT8_MAX
+#define INT_FAST16_MAX INT32_MAX
+#define INT_FAST32_MAX INT32_MAX
+#define INT_FAST64_MAX INT64_MAX
+#define UINT_FAST8_MAX UINT8_MAX
+#define UINT_FAST16_MAX UINT32_MAX
+#define UINT_FAST32_MAX UINT32_MAX
+#define UINT_FAST64_MAX UINT64_MAX
+
+#define INTPTR_MIN INT32_MIN
+#define INTPTR_MAX INT32_MAX
+#define UINTPTR_MAX UINT32_MAX
+
+#define INTMAX_MIN INT64_MIN
+#define INTMAX_MAX INT64_MAX
+#define UINTMAX_MAX UINT64_MAX
+
+#define PTRDIFF_MIN INTPTR_MIN
+#define PTRDIFF_MAX INTPTR_MAX
+
+#ifndef SIZE_MAX
+#define SIZE_MAX UINTPTR_MAX
+#endif
+
+#define SIG_ATOMIC_MIN INT32_MIN
+#define SIG_ATOMIC_MAX INT32_MAX
+
+#define WCHAR_MIN 0x0000
+#define WCHAR_MAX 0xffff
+
+#define WINT_MIN 0x0000
+#define WINT_MAX 0xffff
+
+#define INT8_C(x) (x)
+#define INT16_C(x) (x)
+#define INT32_C(x) (x)
+#define INT64_C(x) (x ## LL)
+
+#define UINT8_C(x) (x)
+#define UINT16_C(x) (x)
+#define UINT32_C(x) (x ## U)
+#define UINT64_C(x) (x ## ULL)
+
+#define INTMAX_C(x) INT64_C(x)
+#define UINTMAX_C(x) UINT64_C(x)
+
+#endif
diff --git a/patch_kernel_root/3rdparty/find_mrs_register.h b/patch_kernel_root/3rdparty/find_mrs_register.h
new file mode 100644
index 00000000..056e4840
--- /dev/null
+++ b/patch_kernel_root/3rdparty/find_mrs_register.h
@@ -0,0 +1,232 @@
+#pragma once
+#include
+#include