From 0484348b5ab5eb99df6774f4ba816edc47fc27a0 Mon Sep 17 00:00:00 2001
From: curuvar <58759586+curuvar@users.noreply.github.com>
Date: Sat, 24 May 2025 12:41:04 -0400
Subject: [PATCH 1/2] Fixes to interrupt handling

---
 modules/riscv32-common/src/riscv32_common.zig | 2 +-
 port/raspberrypi/rp2xxx/src/cpus/hazard3.zig  | 9 +++------
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/modules/riscv32-common/src/riscv32_common.zig b/modules/riscv32-common/src/riscv32_common.zig
index 30599dd86..4d1384846 100644
--- a/modules/riscv32-common/src/riscv32_common.zig
+++ b/modules/riscv32-common/src/riscv32_common.zig
@@ -498,7 +498,7 @@ pub const utilities = struct {
                 }
 
                 pub fn is_pending(int: CoreInterruptEnum) bool {
-                    return csr.mip.read() & (@as(u32, 1) << @intFromEnum(int));
+                    return csr.mip.read() & (@as(u32, 1) << @intFromEnum(int)) != 0;
                 }
 
                 pub fn set_pending(int: CoreInterruptEnum) void {
diff --git a/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig b/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig
index 1ebeebfb3..197156e02 100644
--- a/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig
+++ b/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig
@@ -116,8 +116,8 @@ pub const interrupt = struct {
         const shift: u4 = @intCast(4 * (num & 0x4));
         const set_mask: u16 = @as(u16, @intFromEnum(priority)) << shift;
         const clear_mask: u16 = @as(u16, 0xf) << shift;
-        csr.meifa.clear(.{ .index = index, .window = clear_mask });
-        csr.meifa.set(.{ .index = index, .window = set_mask });
+        csr.meipra.clear(.{ .index = index, .window = clear_mask });
+        csr.meipra.set(.{ .index = index, .window = set_mask });
     }
 
     pub fn get_priority(int: ExternalInterrupt) Priority {
@@ -125,7 +125,7 @@ pub const interrupt = struct {
         const index: u5 = @intCast(num >> 2);
         const shift: u4 = @intCast(4 * (num & 0x4));
         const mask: u16 = @as(u16, 0xf) << shift;
-        return @enumFromInt((csr.meifa.read_set(.{ .index = index }).window & mask) >> shift);
+        return @enumFromInt((csr.meipra.read_set(.{ .index = index }).window & mask) >> shift);
     }
 
     pub inline fn has_ram_vectors() bool {
@@ -219,9 +219,6 @@ pub const startup_logic = struct {
             @memcpy(&ram_vectors, &startup_logic.external_interrupt_table);
         }
 
-        // NOTE: tact1m4n3: I don't think it's fine to enable this behind the user's back.
-        interrupt.core.enable(.MachineExternal);
-
         microzig_main();
     }
 

From b08ed251f8b428261232e3aabe8da63ba36abbdb Mon Sep 17 00:00:00 2001
From: curuvar <58759586+curuvar@users.noreply.github.com>
Date: Sat, 24 May 2025 15:43:35 -0400
Subject: [PATCH 2/2] Updated interrupt example

---
 examples/raspberrypi/rp2xxx/src/interrupts.zig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/examples/raspberrypi/rp2xxx/src/interrupts.zig b/examples/raspberrypi/rp2xxx/src/interrupts.zig
index 9d9dda06a..e27791e77 100644
--- a/examples/raspberrypi/rp2xxx/src/interrupts.zig
+++ b/examples/raspberrypi/rp2xxx/src/interrupts.zig
@@ -67,6 +67,11 @@ pub fn main() !void {
 
     interrupt.enable(timer_irq);
 
+    // Enable machine external interrupts on RISC-V
+    if (rp2xxx.compatibility.arch == .riscv) {
+        microzig.cpu.interrupt.core.enable(.MachineExternal);
+    }
+
     microzig.cpu.interrupt.enable_interrupts();
 
     while (true) {