cleanup comments

Author: Grazfather

sim/aviron/src/lib/io.zig

@@ -125,7 +125,6 @@ pub const RAM = struct {
                 // ATmega328P memory map: SRAM starts at 0x0100
                 // Map logical addresses 0x0100-0x08FF to array indices 0x0000-0x07FF
                 const sram_offset: Address = if (addr >= 0x100) addr - 0x100 else addr;
-                if (sram_offset >= size) return 0; // Return 0 for out-of-bounds reads
                 return mem.data[sram_offset];
             }
 
@@ -134,7 +133,6 @@ pub const RAM = struct {
                 // ATmega328P memory map: SRAM starts at 0x0100
                 // Map logical addresses 0x0100-0x08FF to array indices 0x0000-0x07FF
                 const sram_offset: Address = if (addr >= 0x100) addr - 0x100 else addr;
-                if (sram_offset >= size) return; // Ignore out-of-bounds writes
                 mem.data[sram_offset] = value;
             }
         };

sim/aviron/src/main.zig

@@ -128,7 +128,7 @@ pub fn main() !u8 {
 
     std.debug.print("\nSTOP: {s}\n", .{@tagName(result)});
 
-    // Handle program exit - the defer block will still run
+    // Handle program exit
     if (result == .program_exit) {
         return io.exit_code;
     }
@@ -152,13 +152,10 @@ pub const FileFormat = enum {
 const Cli = struct {
     help: bool = false,
     trace: bool = false,
-    // Dump full register state every instruction
     mcu: MCU = .atmega328p,
     info: bool = false,
     format: FileFormat = .elf,
-    // Breakpoints / halting aids
     break_pc: ?u24 = null,
-    // Stop after N instructions
     gas: ?u64 = null,
 
     pub const shorthands = .{

sim/aviron/src/testrunner.zig

@@ -139,11 +139,10 @@ pub fn main() !u8 {
     test_system = SystemState{
         .options = cli.options,
         .config = config,
-        .io = undefined, // Will be initialized below
-        .cpu = undefined, // Will be initialized below
+        .io = undefined, // Initialized below
+        .cpu = undefined, // Initialized below
     };
 
-    // Initialize IO first
     test_system.io = IO{
         .sreg = undefined, // Will be set after CPU initialization
         // Initialize SP to RAMEND (0x0100 + SRAM size - 1)
@@ -155,7 +154,6 @@ pub fn main() !u8 {
         .stderr = &stderr,
     };
 
-    // Initialize CPU
     test_system.cpu = aviron.Cpu{
         .trace = cli.options.trace,
 
@@ -182,7 +180,6 @@ pub fn main() !u8 {
         },
     };
 
-    // Now link the sreg after both are initialized
     test_system.io.sreg = &test_system.cpu.sreg;
 
     // Initialize CPU state: