finally at el1

Author: liukangxu

os/boot/Makefile

@@ -7,10 +7,10 @@ INCLUDES	  := -I../lib/include/ -I../driver/include/ -I../mm/include/ -I../inclu
 
 .PHONY: clean
 
-all: asm.o el3.o main.o
+all: asm.o el2.o main.o
 
 asm.o :
-	$(AS) asm.s -o asm.o
+	$(AS) $(INCLUDES) asm.s -o asm.o
 
 clean:
 	rm -rf *~ *.o

os/boot/asm.s

@@ -1,3 +1,5 @@
+#include "sysconfig.h"
+
 .globl _start
 _start:
     MRS X0, MPIDR_EL1       // Check Core Id, we only use one core. 
@@ -8,30 +10,46 @@ _start:
 
 master:
     LDR X0, =0X04008000
-    MOV SP, X0
-    BL el3_main
+    MOV SP, X0               // Set EL3 SP
+    BL el2_main
 
 hang:
     B hang
     
 .globl get_current_el
 get_current_el:
     MRS X0, CURRENTEL
+    MOV X1, #2
+    LSR X0, X0, #2
     RET
     
-.globl EL1_mmu_activate
-EL1_mmu_activate:
-    LDR X0, =0X04008000     // Set TTBR0
-    MSR TTBR0_EL3, X0       // Set TTBR0
-    LDR X2, =0X20018
-    MSR TCR_EL3, X2         // Set TCR
-    ISB                     // The ISB forces these changes to be seen before the MMU is enabled.
-    RET
-    TLBI ALLE3IS            // Invalidate the entire TLB.
-    MRS X0, SCTLR_EL3       // Read System Control Register configuration data.
-    ORR X0, X0, #1          // Set [M] bit and enable the MMU.
-    MSR SCTLR_EL3, X0       // Write System Control Register configuration data.
-    ISB                     // The ISB forces these changes to be seen by the next instruction.
+.globl el1_mmu_activate
+el1_mmu_activate:
+    LDR X0, =0X04CC
+    MSR MAIR_EL1, X0
+    ISB
+
+    LDR X1, =0X02000000
+    MSR TTBR0_EL1, X1
+    ISB
+
+    MRS X2, TCR_EL1
+    LDR X3, =0x70040FFBF
+    BIC X2, X2, X3
+
+    LDR X3, =0X200803F18
+    ORR X2, X2, X3
+    MSR TCR_EL1, X2
+    ISB
+
+    MRS X3, SCTLR_EL1
+    LDR X4, =0X80000
+    BIC X3, X3, X4
+    
+    LDR X4, =0X1005
+    ORR X3, X3, X4
+    MSR SCTLR_EL1, X3
+    ISB
     RET
 
 .globl jump_to_el1

os/boot/el3.c

@@ -4,24 +4,25 @@
 #include "pmap.h"
 
 extern u_long get_current_el();
+extern void el1_mmu_activate();
 
 void main (void)
 {
-        
-    printf("%lx\n", get_current_el());
+    printf("We are finally at EL%lx!\n", get_current_el());
+    
+    // activate mmu for el1
+    el1_mmu_activate();
 
-    printf("We are finally at EL1!\n");
-
     page_check();
 
-    printf("Page check passed!\n");
+    printf("Page check passed!\n\n\n\n");
 
     gpio_output_init(17);
     for (;;)
     {
         gpio_set(17);
         sleep(1000);
-
+        
         gpio_clr(17);
         sleep(1000);
     }

os/boot/main.c

@@ -1,6 +1,8 @@
 #ifndef _MMU_H_
 #define _MMU_H_
 
+#include "sysconfig.h"
+
 /*
  * This file contains:
  *
@@ -12,7 +14,6 @@
 /*
  * Part 1.  ARM definitions.
  */
-#define MAXPA   (512 * 1024 * 1024)
 #define BY2PG   4096            // bytes to a page
 #define PDMAP	(4*1024)	// bytes mapped by a third page table entry
 
@@ -36,14 +37,23 @@
 /* Page Table/Directory Entry flags
  *   these are defined by the hardware
  */
-#define PTE_V       0x0003  // Table Entry Valid bit
-#define PBE_V       0x0001  // Block Entry Valid bit
-#define PTE_R       0x0000  // Dirty bit ,'0' means only read ,otherwise make interrupt
-// #define PTE_G       0x0100  // Global bit
-// #define PTE_D       0x0002  // fileSystem Cached is dirty
-// #define PTE_COW     0x0001  // Copy On Write
-// #define PTE_UC      0x0800  // unCached
-// #define PTE_LIBRARY 0x0004  // share memmory
+#define PTE_V                       0x3 << 0  // Table Entry Valid bit
+#define PBE_V                       0x1 << 0  // Block Entry Valid bit
+#define PTE_R                       0x0 << 0  // Dirty bit ,'0' means only read ,otherwise make interrupt
+#define ATTRIB_AP_RW_EL1	        0x0 << 6
+#define ATTRIB_AP_RW_ALL	        0x1 << 6
+#define ATTRIB_AP_RO_EL1	        0x2 << 6
+#define ATTRIB_AP_RO_ALL	        0x3 << 6
+#define ATTRIB_SH_NON_SHAREABLE		0x0 << 8
+#define ATTRIB_SH_OUTER_SHAREABLE	0x2 << 8
+#define ATTRIB_SH_INNER_SHAREABLE	0x3 << 8
+#define AF                          0x1 << 10
+#define PXN                         0x0 << 53
+#define UXN                         0x1UL << 54
+
+#define ATTRINDX_NORMAL		0   // inner/outer write-back non-transient, non-allocating
+#define ATTRINDX_DEVICE		1   // Device-nGnRE
+#define ATTRINDX_COHERENT	2	// Device-nGnRnE
 
 /*
  * Part 2.  Our conventions.
@@ -54,32 +64,22 @@
  o                           |                            |
  o                           |            ...             |
  o                           |                            |
- o               UTOP -----> +----------------------------+------------0x          0430 9000
+ o        EL2STACKTOP -----> +----------------------------+------------0x          0400 0000
+ o                           |          EL2 stack         |
+ o          KSTACKTOP -----> +----------------------------+------------0x          03C0 0000
+ o                           |         Kernel stack       |
+ o               UTOP -----> +----------------------------+------------0x          0230 1000
  o                           |           PAGES            |
- o             UPAGES -----> +----------------------------+------------0x          0400 9000
+ o             UPAGES -----> +----------------------------+------------0x          0200 1000
  o                           |         Page Table         |
- o  UVPT, EL3STACKTOP -----> +----------------------------+------------0x          0400 8000
- o                           |          EL3 stack         |
- o          KSTACKTOP -----> +----------------------------+------------0x          03C0 8000
- o                           |         Kernel stack       |
- o                           |                            |
+ o               UVPT -----> +----------------------------|------------0x          0200 0000
  o                           |         Kernel Text        |
  o           KERNBASE -----> +----------------------------+------------0x             8 0000
  o                           |          reserved          |
  a           0 ------------> +----------------------------+------------0x               0000
  o
 */
 
-#define KERNBASE 0x8000
-
-#define KSTACKTOP   EL3STACKTOP - 0x400000
-#define EL3STACKTOP 0x04008000
-#define UVPT        EL3STACKTOP
-#define UPAGES      UVPT + 0x1000
-#define UTOP        UPAGES + 0x300000
-
-#define KSTKSIZE (60*1024*1024)
-
 #ifndef __ASSEMBLER__
 
 /*