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1 | 1 | .globl _start |
2 | 2 | _start: |
3 | | - B skip |
4 | | - |
5 | | -.space 0x8000 - 0x4, 0 |
6 | | - |
7 | | -skip: |
8 | | - MRS X0, mpidr_el1 |
9 | | - MOV X1, #0xC1000000 |
| 3 | + MRS X0, MPIDR_EL1 // Check Core Id, we only use one core. |
| 4 | + MOV X1, #0XC1000000 |
10 | 5 | BIC X0, X0, X1 |
11 | 6 | CBZ X0, master |
12 | 7 | B hang |
13 | 8 |
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14 | 9 | master: |
15 | | - LDR X0, =0x04008000 |
| 10 | + LDR X0, =0X04008000 |
16 | 11 | MOV SP, X0 |
17 | 12 | BL el3_main |
18 | 13 |
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19 | 14 | hang: |
20 | 15 | B hang |
21 | 16 | |
22 | | -.globl el1_mmu_activate |
23 | | -el1_mmu_activate: |
24 | | - LDR X0, =0x04008000 // Set TTBR0 |
25 | | - MSR TTBR0_EL1, X0 // Set TTBR0 |
26 | | - MSR TCR_EL1, X2 // Set TCR |
27 | | - ISB // The ISB forces these changes to be seen before the MMU is enabled. |
| 17 | +.globl get_current_el |
| 18 | +get_current_el: |
| 19 | + MRS X0, CURRENTEL |
| 20 | + RET |
28 | 21 | |
29 | | - MRS X0, SCTLR_EL1 // Read System Control Register configuration data |
| 22 | +.globl EL1_mmu_activate |
| 23 | +EL1_mmu_activate: |
| 24 | + LDR X0, =0X04008000 // Set TTBR0 |
| 25 | + MSR TTBR0_EL3, X0 // Set TTBR0 |
| 26 | + LDR X2, =0X20018 |
| 27 | + MSR TCR_EL3, X2 // Set TCR |
| 28 | + ISB // The ISB forces these changes to be seen before the MMU is enabled. |
| 29 | + RET |
| 30 | + TLBI ALLE3IS // Invalidate the entire TLB. |
| 31 | + MRS X0, SCTLR_EL3 // Read System Control Register configuration data. |
30 | 32 | ORR X0, X0, #1 // Set [M] bit and enable the MMU. |
31 | | - MSR SCTLR_EL1, X0 // Write System Control Register configuration data |
| 33 | + MSR SCTLR_EL3, X0 // Write System Control Register configuration data. |
32 | 34 | ISB // The ISB forces these changes to be seen by the next instruction. |
| 35 | + RET |
33 | 36 |
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34 | 37 | .globl jump_to_el1 |
35 | 38 | jump_to_el1: |
36 | | - LDR X0, main |
37 | | - MSR ELR_EL3, X0 |
38 | | - LDR X0, =0x03C08000 |
39 | | - MSR SP_EL1, X0 // Set SP |
40 | | - MOV X0, #0x5 |
41 | | - MSR SPSR_EL3, X0 |
42 | | - ERET |
| 39 | + MRS X0, CURRENTEL // Check if already in EL1 |
| 40 | + CMP X0, #4 |
| 41 | + BEQ 1f |
43 | 42 |
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| 43 | + LDR X0, =0X03C08000 |
| 44 | + MSR SP_EL1, X0 // Init the stack of EL1 |
| 45 | + |
| 46 | + // Disable coprocessor traps |
| 47 | + MOV X0, #0X33ff |
| 48 | + MSR CPTR_EL2, X0 // Disable coprocessor traps to EL2 |
| 49 | + MSR HSTR_EL2, xzr // Disable coprocessor traps to EL2 |
| 50 | + MOV X0, #3 << 20 |
| 51 | + MSR CPACR_EL1, X0 // Enable FP/SIMD at EL1 |
| 52 | + |
| 53 | + // Initialize HCR_EL2 |
| 54 | + MOV X0, #(1 << 31) |
| 55 | + MSR HCR_EL2, X0 // Set EL1 to 64 bit |
| 56 | + MOV X0, #0X0800 |
| 57 | + MOVK X0, #0X30d0, LSL #16 |
| 58 | + MSR SCTLR_EL1, X0 |
| 59 | + |
| 60 | + // Return to the EL1_SP1 mode from EL2 |
| 61 | + MOV X0, #0X3C5 |
| 62 | + MSR SPSR_EL2, X0 // EL1_SP0 | D | A | I | F |
| 63 | + ADR X0, 1f |
| 64 | + MSR ELR_EL2, X0 |
| 65 | + ERET |
| 66 | + |
| 67 | +1: |
| 68 | + MRS X0, SCTLR_EL1 |
| 69 | + ORR X0, X0, #(1 << 12) |
| 70 | + MSR SCTLR_EL1, X0 // enable instruction cache |
| 71 | + |
| 72 | + B main |
| 73 | + |
44 | 74 | .globl tlb_invalidate |
45 | 75 | tlb_invalidate: |
46 | 76 | DSB ISHST // ensure write has completed |
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