IODELAY

IODELAY

Ports

Port	Size	Direction
DF	1	output
DI	1	input
DLYSTEP	8	input
DO	1	output
SDTAP	1	input
VALUE	1	input

Parameters

Parameter	Default Value
ADAPT_EN	FALSE
C_STATIC_DLY	0 (0b00000000000000000000000000000000)
DYN_DLY_EN	FALSE

Verilog Instantiation

IODELAY #(
    .ADAPT_EN(ADAPT_EN),
    .C_STATIC_DLY(C_STATIC_DLY),
    .DYN_DLY_EN(DYN_DLY_EN)
) iodelay_inst (
    .DF(DF),
    .DI(DI),
    .DLYSTEP(DLYSTEP),
    .DO(DO),
    .SDTAP(SDTAP),
    .VALUE(VALUE)
);