IEM

The IEM (Input Edge Monitor) primitive is a sampling module used for detecting data edges, which can be used in conjunction with a delay module to adjust the dynamic sampling window for DDR mode. It has inputs D (data input signal), CLK (clock input signal), MCLK (IEM detecting clock from user logic), RESET (asynchronous reset), and outputs LAG (lag flag) and LEAD (lead flag). The IEM can be configured with different window size settings (WINSIZE) and enable global or local resets (GSREN and LSREN, respectively).

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CLK	1	input
D	1	input
LAG	1	output
LEAD	1	output
MCLK	1	input
RESET	1	input

Parameters

Parameter	Default Value
GSREN	false
LSREN	true
WINSIZE	SMALL

Verilog Instantiation

IEM #(
    .GSREN(GSREN),
    .LSREN(LSREN),
    .WINSIZE(WINSIZE)
) iem_inst (
    .CLK(CLK),
    .D(D),
    .LAG(LAG),
    .LEAD(LEAD),
    .MCLK(MCLK),
    .RESET(RESET)
);