DQCE

The DQCE (Dynamic Quotient Clock Enable) primitive allows for dynamic control over the internal clock network in a Gowin FPGA device. Specifically, it enables or disables the PCLK network in a quadrant, and can also disable the dynamic clock control to always enable the PCLK network when disabled. This feature reduces power consumption by preventing logic driven by the affected clocks from toggling when the clocks are disabled.

This device is supported in Apicula.

Ports

Port	Size	Direction
CE	1	input
CLKIN	1	input
CLKOUT	1	output

Verilog Instantiation

DQCE dqce_inst (
    .CE(CE),
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT)
);