DL

The Data Latch (DL) primitive has a control signal G that is active-high. The D input stores data, which is then output as Q when G is high, otherwise retaining its initial value of 0.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
D	1	input
G	1	input
Q	1	output

Parameters

Parameter	Default Value
INIT	0 (0b0)

Verilog Instantiation

DL #(
    .INIT(INIT)
) dl_inst (
    .D(D),
    .G(G),
    .Q(Q)
);