DDRDLL

The Gowin DDRDLL primitive can generate different phase delay steps based on a given input clock for clock phase shift. It calculates an output STEP signal that drives DQS, DLLDLY modules, and also allows the STEP to be routed to user logic. The clock input sources of DDRDLL include GCLK and the adjacent HCLK.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CLKIN	1	input
LOCK	1	output
RESET	1	input
STEP	8	output
STOP	1	input
UPDNCNTL	1	input

Parameters

Parameter	Default Value
CODESCAL	000
DIV_SEL	0 (0b0)
DLL_FORCE	FALSE
SCAL_EN	TRUE

Verilog Instantiation

DDRDLL #(
    .CODESCAL(CODESCAL),
    .DIV_SEL(DIV_SEL),
    .DLL_FORCE(DLL_FORCE),
    .SCAL_EN(SCAL_EN)
) ddrdll_inst (
    .CLKIN(CLKIN),
    .LOCK(LOCK),
    .RESET(RESET),
    .STEP(STEP),
    .STOP(STOP),
    .UPDNCNTL(UPDNCNTL)
);