CLKDIV

The Gowin CLKDIV primitive is a clock frequency divider that generates a divider clock with the same phase as the input clock. It supports various division modes, including 2/3.5/4/5 frequency division for some devices, and 2/3.5/4/5 frequency division for other devices. The CALIB signal can be used to adjust the output clock phase in conjunction with IOLOGIC, resulting in different phase adjustments per falling edge and cycle based on the specific division mode (e.g., 180 degrees every 2 falling edges for a 2x divider).

This device is supported in Apicula.

Ports

Port	Size	Direction
CALIB	1	input
CLKOUT	1	output
HCLKIN	1	input
RESETN	1	input

Parameters

Parameter	Default Value
DIV_MODE	2

Verilog Instantiation

CLKDIV #(
    .DIV_MODE(DIV_MODE)
) clkdiv_inst (
    .CALIB(CALIB),
    .CLKOUT(CLKOUT),
    .HCLKIN(HCLKIN),
    .RESETN(RESETN)
);