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Releases: YosysHQ/apicula

0.1

15 Dec 18:36
b860eaa
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0.1

Known issues!

This release is by no means perfect. Some complex designs appear to generate bitstreams with timing violations. Passing -nodffe resolves this in some cases. Depends on the exact commit of Yosys and Nextpnr used.

The main reason for publishing this release is that some major changes are coming, and we want to be able to do an alpha relese while most users will by default get a somewhat more stable release. Expect many bugfix and feature releases in the future.

What's Changed

Full Changelog: 0.0.1a12...0.1

0.0.1a12

06 Nov 13:08
f3c22dd
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0.0.1a12 Pre-release
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What's Changed

  • Add ALU packing and unpacking. by @yrabbit in #54
  • Add dualmode pins options to gowin_pack by @yrabbit in #58
  • Get info about packages/pins from the IDE files. by @yrabbit in #57

Full Changelog: 0.0.1a11...0.0.1a12

0.0.1a11

12 Oct 15:22
4140d04
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What's Changed

Full Changelog: 0.0.1a10...0.0.1a11

0.0.1a10

12 Oct 15:20
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What's Changed

New Contributors

Full Changelog: 0.0.1a9...0.0.1a10

GW1NS-2C support

06 Jul 10:08
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0.0.1a9

generate GW1NS-2 chipdb on CI

Slightly less broken

25 Apr 17:13
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0.0.1a8

allow different reset polarity in same cls

0.0.1a6

02 Feb 11:15
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0.0.1a6 Pre-release
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Merge branch 'master' of github.com:pepijndevos/apicula

0.0.0.dev

14 Nov 12:54
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