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ProyectoFinalCasiquenoEsteSi.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 18:35:49 octubre 27, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ProyectoFinalCasiquenoEsteSi_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY ProyectoFinalCasiquenoEsteSi
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:35:49 OCTUBRE 27, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE usart_t.vhd
set_global_assignment -name VHDL_FILE suma.vhd
set_global_assignment -name VHDL_FILE usart_pkg.vhd
set_global_assignment -name VHDL_FILE USART.vhd
set_global_assignment -name VHDL_FILE repartidor.vhd
set_global_assignment -name VHDL_FILE reg1bit.vhd
set_global_assignment -name VHDL_FILE habilitador.vhd
set_global_assignment -name VHDL_FILE guarda_reparticion.vhd
set_global_assignment -name VHDL_FILE corrimiento_registros.vhd
set_global_assignment -name VHDL_FILE contadorUSART.vhd
set_global_assignment -name VHDL_FILE PWM.vhd
set_global_assignment -name VHDL_FILE ProyectoFinalCasiquenoEsteSi.vhd
set_global_assignment -name VHDL_FILE Maquina.vhd
set_global_assignment -name VHDL_FILE contador.vhd
set_global_assignment -name VHDL_FILE componentes_pkg.vhd
set_global_assignment -name VHDL_FILE preescalar_reloj.vhd
set_location_assignment PIN_R8 -to clk
set_location_assignment PIN_T13 -to entrada_usb
set_location_assignment PIN_N16 -to motor_banda
set_location_assignment PIN_P16 -to motor_brazo
set_location_assignment PIN_J13 -to motor_garra
set_location_assignment PIN_K16 -to motor_giro
set_location_assignment PIN_J15 -to reset_n
set_location_assignment PIN_J14 -to not_s1
set_location_assignment PIN_K15 -to not_s2
set_location_assignment PIN_L13 -to s3
set_location_assignment PIN_N14 -to s5
set_location_assignment PIN_P14 -to x
set_location_assignment PIN_M1 -to SC[1]
set_location_assignment PIN_T8 -to SC[0]
set_location_assignment PIN_A15 -to led1
set_location_assignment PIN_L3 -to led2
set_location_assignment PIN_B1 -to actual_estado[0]
set_location_assignment PIN_F3 -to actual_estado[1]
set_location_assignment PIN_D1 -to actual_estado[2]
set_location_assignment PIN_A11 -to actual_estado[3]
set_location_assignment PIN_B13 -to actual_estado[4]
set_location_assignment PIN_T12 -to salida_usb
set_location_assignment PIN_R10 -to led_stop
set_location_assignment PIN_T11 -to led_banda
set_location_assignment PIN_R11 -to led_brazo
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top