Added design name.

Author: Paebbels

pyVHDLModel/__init__.py

@@ -54,7 +54,7 @@
 from enum                      import unique, Enum, Flag, auto
 from pathlib                   import Path
 
-from typing                    import Union, Dict, cast, List, Generator
+from typing                    import Union, Dict, cast, List, Generator, Optional as Nullable
 
 from pyTooling.Decorators      import export
 from pyTooling.Graph           import Graph, Vertex, Edge
@@ -371,17 +371,23 @@ class Design(ModelEntity):
 	A ``Design`` represents all loaded and analysed files (see :class:`~pyVHDLModel.Document`). It's the root of this
 	document-object-model (DOM). It contains at least one VHDL library (see :class:`~pyVHDLModel.Library`).
 	"""
-	_libraries:  Dict[str, 'Library']  #: List of all libraries defined for a design.
-	_documents:  List['Document']      #: List of all documents loaded for a design.
-
-	_compileOrderGraph: Graph[None, None, None, None, None, 'Document', None, None, None, None, None, None, None]
-	_dependencyGraph:   Graph[None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None]
-	_hierarchyGraph:    Graph[None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None]
-	_toplevel:          Union[Entity, Configuration]
+	name:               Nullable[str]         #: Name of the design
+	_libraries:         Dict[str, 'Library']  #: List of all libraries defined for a design.
+	_documents:         List['Document']      #: List of all documents loaded for a design.
+	_dependencyGraph:   Graph[None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None]   #: The graph of all dependencies in the designs.
+	_compileOrderGraph: Graph[None, None, None, None, None, 'Document', None, None, None, None, None, None, None]  #: A graph derived from dependency graph containing the order of documents for compilation.
+	_hierarchyGraph:    Graph[None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None]   #: A graph derived from dependency graph containing the design hierarchy.
+	_toplevel:          Union[Entity, Configuration]  #: When computed, the toplevel design unit is cached in this field.
+
+	def __init__(self, name: str = None):
+		"""
+		Initializes a VHDL design.
 
-	def __init__(self):
+		:param name: Name of the design.
+		"""
 		super().__init__()
 
+		self.name =       name
 		self._libraries = {}
 		self._documents = []