Skip to content

Commit 17597bf

Browse files
committed
Added Component and matching symbol.
1 parent 840b6b7 commit 17597bf

File tree

1 file changed

+34
-0
lines changed

1 file changed

+34
-0
lines changed

pyVHDLModel/VHDLModel.py

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -251,6 +251,19 @@ def Architecture(self) -> 'Architecture':
251251
return self._architecture
252252

253253

254+
@export
255+
class ComponentSymbol(Symbol):
256+
_component: 'Component'
257+
258+
def __init__(self):
259+
super().__init__()
260+
self._component = None
261+
262+
@property
263+
def Component(self) -> 'Component':
264+
return self._component
265+
266+
254267
@export
255268
class ConfigurationSymbol(Symbol):
256269
_configuration: 'Configuration'
@@ -1770,6 +1783,27 @@ def BodyItems(self) -> List['ConcurrentStatement']:
17701783
return self._bodyItems
17711784

17721785

1786+
@export
1787+
class Component(ModelEntity, NamedEntity):
1788+
_genericItems: List[GenericInterfaceItem]
1789+
_portItems: List[PortInterfaceItem]
1790+
1791+
def __init__(self, name: str):
1792+
super().__init__()
1793+
NamedEntity.__init__(self, name)
1794+
1795+
self._genericItems = []
1796+
self._portItems = []
1797+
1798+
@property
1799+
def GenericItems(self) -> List[GenericInterfaceItem]:
1800+
return self._genericItems
1801+
1802+
@property
1803+
def PortItems(self) -> List[PortInterfaceItem]:
1804+
return self._portItems
1805+
1806+
17731807
@export
17741808
class Configuration(PrimaryUnit, MixinDesignUnitWithContext):
17751809
def __init__(self, name: str):

0 commit comments

Comments
 (0)