v0.17.0

Author: Paebbels

.github/workflows/Pipeline.yml

@@ -100,7 +100,7 @@ jobs:
 
       - name: 🐍 Install dependencies
         run: |
-          pip3 install git+https://github.com/ghdl/ghdl.git@$(ghdl version hash)
+          pip3 install --disable-pip-version-check git+https://github.com/ghdl/ghdl.git@$(ghdl version hash)
 
       - name: ✂ Extract code snippet from README
         shell: python

doc/LanguageModel/ConcurrentStatements.rst

@@ -3,26 +3,12 @@
 Concurrent Statements
 #####################
 
-* :ref:`vhdlmodel-con-assertstatement`
-* :ref:`vhdlmodel-con-signalassignment`
-* :ref:`vhdlmodel-instantiations`
-
-  * :ref:`vhdlmodel-entityinstantiation`
-  * :ref:`vhdlmodel-componentinstantiation`
-  * :ref:`vhdlmodel-configurationinstantiation`
-
-* :ref:`vhdlmodel-generates`
-
-  * :ref:`vhdlmodel-ifgenerate`
-  * :ref:`vhdlmodel-casegenerate`
-  * :ref:`vhdlmodel-forgenerate`
-
-* :ref:`vhdlmodel-con-procedurecall`
-* :ref:`vhdlmodel-process`
+.. contents:: Table of Content
+   :local:
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.ConcurrentAssertStatement pyVHDLModel.VHDLModel.ConcurrentSignalAssignment pyVHDLModel.VHDLModel.ConcurrentBlockStatement pyVHDLModel.VHDLModel.ProcessStatement pyVHDLModel.VHDLModel.IfGenerateStatement pyVHDLModel.VHDLModel.CaseGenerateStatement pyVHDLModel.VHDLModel.ForGenerateStatement pyVHDLModel.VHDLModel.ComponentInstantiation pyVHDLModel.VHDLModel.ConfigurationInstantiation pyVHDLModel.VHDLModel.EntityInstantiation pyVHDLModel.VHDLModel.ConcurrentProcedureCall
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.ConcurrentAssertStatement pyVHDLModel.SyntaxModel.ConcurrentSignalAssignment pyVHDLModel.SyntaxModel.ConcurrentBlockStatement pyVHDLModel.SyntaxModel.ProcessStatement pyVHDLModel.SyntaxModel.IfGenerateStatement pyVHDLModel.SyntaxModel.CaseGenerateStatement pyVHDLModel.SyntaxModel.ForGenerateStatement pyVHDLModel.SyntaxModel.ComponentInstantiation pyVHDLModel.SyntaxModel.ConfigurationInstantiation pyVHDLModel.SyntaxModel.EntityInstantiation pyVHDLModel.SyntaxModel.ConcurrentProcedureCall
    :parts: 1
 
 .. _vhdlmodel-con-assertstatement:
@@ -34,7 +20,7 @@ Assert Statement
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ConcurrentSignalAssignment`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ConcurrentSignalAssignment`:
 
 .. code-block:: Python
 
@@ -70,7 +56,7 @@ Signal Assignment
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ConcurrentSignalAssignment`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ConcurrentSignalAssignment`:
 
 .. code-block:: Python
 
@@ -102,7 +88,7 @@ Concurrent Block Statement
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ConcurrentBlockStatement`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ConcurrentBlockStatement`:
 
 .. code-block:: Python
 
@@ -166,7 +152,7 @@ If Generate
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.IfGenerateStatement`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.IfGenerateStatement`:
 
 .. code-block:: Python
 
@@ -201,7 +187,7 @@ Case Generate
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.CaseGenerateStatement`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.CaseGenerateStatement`:
 
 .. code-block:: Python
 
@@ -233,7 +219,7 @@ For Generate
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ForGenerateStatement`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ForGenerateStatement`:
 
 .. code-block:: Python
 
@@ -282,7 +268,7 @@ Process
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ForGenerateStatement`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ForGenerateStatement`:
 
 .. code-block:: Python
 

doc/LanguageModel/DesignUnits.rst

@@ -6,24 +6,12 @@ Design Units
 A VHDL design (see :ref:`vhdlmodel-design`) is assembled from *design units*. VHDL distinguishes
 between *primary* and *secondary* design units.
 
-.. rubric:: Table of Content
-
-* :ref:`vhdlmodel-primary`
-
-  * :ref:`vhdlmodel-context`
-  * :ref:`vhdlmodel-configuration`
-  * :ref:`vhdlmodel-entity`
-  * :ref:`vhdlmodel-package`
-
-* :ref:`vhdlmodel-secondary`
-
-  * :ref:`vhdlmodel-architeture`
-  * :ref:`vhdlmodel-packagebody`
-
+.. contents:: Table of Content
+   :local:
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.Architecture pyVHDLModel.VHDLModel.Context pyVHDLModel.VHDLModel.Configuration pyVHDLModel.VHDLModel.Entity pyVHDLModel.VHDLModel.Package pyVHDLModel.VHDLModel.PackageBody
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.Architecture pyVHDLModel.SyntaxModel.Context pyVHDLModel.SyntaxModel.Configuration pyVHDLModel.SyntaxModel.Entity pyVHDLModel.SyntaxModel.Package pyVHDLModel.SyntaxModel.PackageBody
    :parts: 1
 
 .. _vhdlmodel-primary:
@@ -64,7 +52,7 @@ available as lists. An entities also provides lists of generic and port items.
 The list of declared items (e.g. objects) also contains defined items (e.g.
 types). An entity's list of statements is called body items.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Entity`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Entity`:
 
 .. code-block:: Python
 
@@ -112,7 +100,7 @@ Package
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Package`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Package`:
 
 .. code-block:: Python
 
@@ -159,7 +147,7 @@ Architeture
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Architecture`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Architecture`:
 
 .. code-block:: Python
 
@@ -204,7 +192,7 @@ Package Body
 
    Write documentation.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.PackageBody`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.PackageBody`:
 
 .. code-block:: Python
 

doc/LanguageModel/Enumerations.rst

@@ -4,24 +4,20 @@ Enumerations
 ############
 
 The language model contains some enumerations to express a *kind* of a models
-entity. These are not enumerated types defined by VHDL itself, like `boolean`.
-
-.. rubric:: Table of Content
-
-* :ref:`vhdlmodel-direction`
-* :ref:`vhdlmodel-mode`
-* :ref:`vhdlmodel-objclass`
+entity. These are not enumerated types defined by VHDL itself, like ``boolean``.
 
+.. contents:: Table of Content
+   :local:
 
 
 .. _vhdlmodel-direction:
 
 Direction
 =========
 
-Ranges and slices have an ascending (`to`) or descending (`downto`) direction.
+Ranges and slices have an ascending (``To``) or descending (``DownTo``) direction.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Direction`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Direction`:
 
 .. code-block:: Python
 
@@ -38,10 +34,10 @@ Mode
 ====
 
 A *mode* describes the direction of data exchange e.g. for entity ports or subprogram parameters.
-In addition to the modes defined by VHDL (`In`, `Out`, `InOut`, `Buffer` and `Linkage`), `Default`
+In addition to the modes defined by VHDL (``In``, ``Out``, ``InOut``, ``Buffer`` and ``Linkage``), ``Default``
 is a placeholder for omitted modes. The mode is then determined from the context.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Mode`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Mode`:
 
 .. code-block:: Python
 
@@ -65,7 +61,7 @@ In addition to the 4 object classes defined by VHDL (`Constant`, `Variable`,
 `Signal` and `File`), `Default` is used when no object class is defined. In
 such a case, the object class is determined from the context.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ObjectClass`:
+**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ObjectClass`:
 
 .. code-block:: Python
 

doc/LanguageModel/Expressions.rst

@@ -3,27 +3,12 @@
 Literals and Expressions
 ########################
 
-
-
-.. rubric:: Table of Content
-
-* :ref:`vhdlmodel-literals`
-
-  * :ref:`vhdlmodel-enumerationliteral`
-  * :ref:`vhdlmodel-integerliteral`
-  * :ref:`vhdlmodel-realliteral`
-  * :ref:`vhdlmodel-physicalliteral`
-
-* :ref:`vhdlmodel-expressions`
-
-  * :ref:`vhdlmodel-unary`
-  * :ref:`vhdlmodel-binary`
-  * :ref:`vhdlmodel-ternary`
-
+.. contents:: Table of Content
+   :local:
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.EnumerationLiteral pyVHDLModel.VHDLModel.IntegerLiteral pyVHDLModel.VHDLModel.FloatingPointLiteral pyVHDLModel.VHDLModel.PhysicalLiteral pyVHDLModel.VHDLModel.CharacterLiteral pyVHDLModel.VHDLModel.StringLiteral pyVHDLModel.VHDLModel.BitStringLiteral
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.EnumerationLiteral pyVHDLModel.SyntaxModel.IntegerLiteral pyVHDLModel.SyntaxModel.FloatingPointLiteral pyVHDLModel.SyntaxModel.PhysicalLiteral pyVHDLModel.SyntaxModel.CharacterLiteral pyVHDLModel.SyntaxModel.StringLiteral pyVHDLModel.SyntaxModel.BitStringLiteral
    :parts: 1
 
 .. _vhdlmodel-literals:
@@ -82,7 +67,7 @@ Expressions
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.UnaryExpression pyVHDLModel.VHDLModel.AddingExpression pyVHDLModel.VHDLModel.MultiplyingExpression pyVHDLModel.VHDLModel.LogicalExpression pyVHDLModel.VHDLModel.ShiftExpression pyVHDLModel.VHDLModel.TernaryExpression
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.UnaryExpression pyVHDLModel.SyntaxModel.AddingExpression pyVHDLModel.SyntaxModel.MultiplyingExpression pyVHDLModel.SyntaxModel.LogicalExpression pyVHDLModel.SyntaxModel.ShiftExpression pyVHDLModel.SyntaxModel.TernaryExpression
    :parts: 1
 
 .. todo::
@@ -98,7 +83,7 @@ Unary Expressions
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.InverseExpression pyVHDLModel.VHDLModel.IdentityExpression pyVHDLModel.VHDLModel.NegationExpression pyVHDLModel.VHDLModel.AbsoluteExpression pyVHDLModel.VHDLModel.TypeConversion pyVHDLModel.VHDLModel.FunctionCall pyVHDLModel.VHDLModel.QualifiedExpression
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.InverseExpression pyVHDLModel.SyntaxModel.IdentityExpression pyVHDLModel.SyntaxModel.NegationExpression pyVHDLModel.SyntaxModel.AbsoluteExpression pyVHDLModel.SyntaxModel.TypeConversion pyVHDLModel.SyntaxModel.FunctionCall pyVHDLModel.SyntaxModel.QualifiedExpression
    :parts: 1
 
 .. todo::
@@ -114,7 +99,7 @@ Binary Expressions
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.AddingExpression pyVHDLModel.VHDLModel.MultiplyingExpression pyVHDLModel.VHDLModel.LogicalExpression pyVHDLModel.VHDLModel.RelationalExpression pyVHDLModel.VHDLModel.ShiftExpression
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.AddingExpression pyVHDLModel.SyntaxModel.MultiplyingExpression pyVHDLModel.SyntaxModel.LogicalExpression pyVHDLModel.SyntaxModel.RelationalExpression pyVHDLModel.SyntaxModel.ShiftExpression
    :parts: 1
 
 .. todo::
@@ -130,7 +115,7 @@ Adding Expressions
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.AdditionExpression pyVHDLModel.VHDLModel.SubtractionExpression pyVHDLModel.VHDLModel.ConcatenationExpression
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.AdditionExpression pyVHDLModel.SyntaxModel.SubtractionExpression pyVHDLModel.SyntaxModel.ConcatenationExpression
    :parts: 1
 
 .. todo::
@@ -146,7 +131,7 @@ Multiplying Expressions
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.MultiplyExpression pyVHDLModel.VHDLModel.DivisionExpression pyVHDLModel.VHDLModel.RemainderExpression pyVHDLModel.VHDLModel.ModuloExpression pyVHDLModel.VHDLModel.ExponentiationExpression
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.MultiplyExpression pyVHDLModel.SyntaxModel.DivisionExpression pyVHDLModel.SyntaxModel.RemainderExpression pyVHDLModel.SyntaxModel.ModuloExpression pyVHDLModel.SyntaxModel.ExponentiationExpression
    :parts: 1
 
 .. todo::
@@ -162,7 +147,7 @@ Logical Expressions
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.AndExpression pyVHDLModel.VHDLModel.NandExpression pyVHDLModel.VHDLModel.OrExpression pyVHDLModel.VHDLModel.NorExpression pyVHDLModel.VHDLModel.XorExpression	pyVHDLModel.VHDLModel.XnorExpression
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.AndExpression pyVHDLModel.SyntaxModel.NandExpression pyVHDLModel.SyntaxModel.OrExpression pyVHDLModel.SyntaxModel.NorExpression pyVHDLModel.SyntaxModel.XorExpression	pyVHDLModel.SyntaxModel.XnorExpression
    :parts: 1
 
 .. todo::
@@ -178,7 +163,7 @@ Relational Expressions
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.EqualExpression pyVHDLModel.VHDLModel.UnequalExpression pyVHDLModel.VHDLModel.GreaterThanExpression pyVHDLModel.VHDLModel.GreaterEqualExpression pyVHDLModel.VHDLModel.LessThanExpression
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.EqualExpression pyVHDLModel.SyntaxModel.UnequalExpression pyVHDLModel.SyntaxModel.GreaterThanExpression pyVHDLModel.SyntaxModel.GreaterEqualExpression pyVHDLModel.SyntaxModel.LessThanExpression
    :parts: 1
 
 .. todo::
@@ -194,7 +179,7 @@ Shifting Expressions
 
 .. rubric:: Class Hierarchy
 
-.. inheritance-diagram:: pyVHDLModel.VHDLModel.ShiftRightLogicExpression pyVHDLModel.VHDLModel.ShiftLeftLogicExpression pyVHDLModel.VHDLModel.ShiftRightArithmeticExpression pyVHDLModel.VHDLModel.ShiftLeftArithmeticExpression pyVHDLModel.VHDLModel.RotateRightExpression pyVHDLModel.VHDLModel.RotateLeftExpression
+.. inheritance-diagram:: pyVHDLModel.SyntaxModel.ShiftRightLogicExpression pyVHDLModel.SyntaxModel.ShiftLeftLogicExpression pyVHDLModel.SyntaxModel.ShiftRightArithmeticExpression pyVHDLModel.SyntaxModel.ShiftLeftArithmeticExpression pyVHDLModel.SyntaxModel.RotateRightExpression pyVHDLModel.SyntaxModel.RotateLeftExpression
    :parts: 1
 
 .. todo::