Added more documentation.

Author: Paebbels

doc/LanguageModel/DesignUnits.rst

@@ -3,41 +3,58 @@
 Design Units
 ############
 
-* Primary Units
+A VHDL design (see :ref:`vhdlmodel-design`) is assembled from *design units*. VHDL distinguishes
+between *primary* and *secondary* design units.
 
-  * Context
-  * Configuration
-  * Entity
-  * Package
+.. rubric:: Table of Content
 
-* Secondary Units
+* :ref:`vhdlmodel-primary`
 
-  * Architeture
-  * Package Body
+  * :ref:`vhdlmodel-context`
+  * :ref:`vhdlmodel-configuration`
+  * :ref:`vhdlmodel-entity`
+  * :ref:`vhdlmodel-package`
+
+* :ref:`vhdlmodel-secondary`
+
+  * :ref:`vhdlmodel-architeture`
+  * :ref:`vhdlmodel-packagebody`
+
+
+.. _vhdlmodel-primary:
 
 Primary Units
 =============
 
+.. _vhdlmodel-context:
+
 Context
 -------
 
 .. todo::
 
    Write documentation.
 
+
+
+.. _vhdlmodel-configuration:
+
 Configuration
 -------------
 
 .. todo::
 
    Write documentation.
 
+
+
+.. _vhdlmodel-entity:
+
 Entity
 ------
 
-.. todo::
-
-   Write documentation.
+An ``Entity`` represents a VHDL entity declaration. It has a list of generic and
+port items. It can contain a list of declared and body items.
 
 **Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Entity`:
 
@@ -46,7 +63,7 @@ Entity
    @export
    class Entity(PrimaryUnit):
      _libraryReferences: List[LibraryReference]
-     _uses:              List[Use]
+     _packageReferences: List[PackageReference]
      _genericItems:      List[GenericInterfaceItem]
      _portItems:         List[PortInterfaceItem]
      _declaredItems:     List   # FIXME: define liste element type e.g. via Union
@@ -58,7 +75,7 @@ Entity
      def LibraryReferences(self) -> List[LibraryReference]:
 
      @property
-     def Uses(self) -> List[Use]:
+     def PackageReferences(self) -> List[PackageReference]:
 
      @property
      def GenericItems(self) -> List[GenericInterfaceItem]:
@@ -74,6 +91,8 @@ Entity
 
 
 
+.. _vhdlmodel-package:
+
 Package
 -------
 
@@ -88,7 +107,7 @@ Package
    @export
    class Package(PrimaryUnit):
      _libraryReferences: List[Library]
-     _uses:              List[Use]
+     _packageReferences: List[PackageReference]
      _genericItems:      List[GenericInterfaceItem]
      _declaredItems:     List
 
@@ -98,7 +117,7 @@ Package
      def LibraryReferences(self) -> List[Library]:
 
      @property
-     def Uses(self) -> List[Use]:
+     def PackageReferences(self) -> List[PackageReference]:
 
      @property
      def GenericItems(self) -> List[GenericInterfaceItem]:
@@ -108,9 +127,13 @@ Package
 
 
 
+.. _vhdlmodel-secondary:
+
 Secondary Units
 ===============
 
+.. _vhdlmodel-architeture:
+
 Architeture
 -----------
 
@@ -126,7 +149,7 @@ Architeture
    class Architecture(SecondaryUnit):
      _entity:            Entity
      _libraryReferences: List[Library]
-     _uses:              List[Use]
+     _packageReferences: List[PackageReference]
      _declaredItems:     List   # FIXME: define liste element type e.g. via Union
      _bodyItems:         List['ConcurrentStatement']
 
@@ -139,7 +162,7 @@ Architeture
      def LibraryReferences(self) -> List[Library]:
 
      @property
-     def Uses(self) -> List[Use]:
+     def PackageReferences(self) -> List[PackageReference]:
 
      @property
      def DeclaredItems(self) -> List:
@@ -149,6 +172,8 @@ Architeture
 
 
 
+.. _vhdlmodel-packagebody:
+
 Package Body
 ------------
 
@@ -164,7 +189,7 @@ Package Body
    class PackageBody(SecondaryUnit):
      _package:           Package
      _libraryReferences: List[Library]
-     _uses:              List[Use]
+     _packageReferences: List[PackageReference]
      _declaredItems:     List
 
      def __init__(self, name: str):
@@ -176,7 +201,7 @@ Package Body
      def LibraryReferences(self) -> List[Library]:
 
      @property
-     def Uses(self) -> List[Use]:
+     def PackageReferences(self) -> List[PackageReference]:
 
      @property
      def DeclaredItems(self) -> List:

doc/LanguageModel/Enumerations.rst

@@ -3,16 +3,30 @@
 Enumerations
 ############
 
+The language model contains some enumerations to express a *kind* of a models entity.
 
-Modes
-=====
+.. rubric:: Table of Content
+
+* :ref:`vhdlmodel-mode`
+* :ref:`vhdlmodel-objclass`
+
+
+
+.. _vhdlmodel-mode:
+
+Mode
+====
 
 .. todo::
 
    Write documentation.
 
-Object Classes
-==============
+
+
+.. _vhdlmodel-objclass:
+
+Object Class
+============
 
 .. todo::
 

doc/LanguageModel/Miscellaneous.rst

@@ -9,9 +9,10 @@ specific to the implementer.
 
 .. rubric:: Table of Content
 
-* :ref:`Design <vhdlmodel-design>`
-* :ref:`Library <vhdlmodel-library>`
-* :ref:`Document <vhdlmodel-document>`
+* :ref:`vhdlmodel-design`
+* :ref:`vhdlmodel-library`
+* :ref:`vhdlmodel-document`
+
 
 .. _vhdlmodel-design:
 

doc/LanguageModel/SubprogramDefinitions.rst

@@ -3,8 +3,14 @@
 Subprogram Declarations
 ########################
 
-* Procedure
-* Function
+.. rubric:: Table of Content
+
+* :ref:`vhdlmodel-procedure`
+* :ref:`vhdlmodel-function`
+
+
+
+.. _vhdlmodel-procedure:
 
 Procedure
 =========
@@ -13,6 +19,10 @@ Procedure
 
    Write documentation.
 
+
+
+.. _vhdlmodel-function:
+
 Function
 ========