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Add ParenthesisExpression.
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pyVHDLModel/VHDLModel.py

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@@ -839,6 +839,10 @@ class TypeConversion(UnaryExpression):
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class FunctionCall(UnaryExpression):
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pass
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@export
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class ParenthesisExpression(UnaryExpression):
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pass
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@export
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class QualifiedExpression(UnaryExpression):
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pass

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