From 866e3f6ed1b9563b68eac4021532d7856d2c2563 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Sun, 23 Nov 2025 23:16:45 +0100 Subject: [PATCH 1/5] Add output port for GitVersionRegister with its register content as records --- .../AXI4Lite/AXI4Lite_GitVersionRegister.vhdl | 8 +- src/mem/mem_GitVersionRegister.pkg.vhdl | 86 ++++++++++++++++--- 2 files changed, 80 insertions(+), 14 deletions(-) diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl index 999e932d8..60764f9e9 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl @@ -10,6 +10,9 @@ -- ------------------------------------- -- This version register can be auto filled with constants from Git. Software -- can read from what revision a firmware (bitstream, PL code) was build. +-- +-- The Version-out-Port is used to make all values accessible to the PL. This +-- can be used by another interface than AXI4L, if necessary. -- -- Use the pre-synthesis script from -- PoC/tools/git/preSynth_GitVersionRegister_Vivado.tcl @@ -62,7 +65,9 @@ entity AXI4Lite_GitVersionRegister is Reset : in std_logic; AXI4Lite_m2s : in T_AXI4Lite_BUS_M2S; - AXI4Lite_s2m : out T_AXI4Lite_BUS_S2M + AXI4Lite_s2m : out T_AXI4Lite_BUS_S2M; + + Version : out T_Version_Register ); end entity; @@ -100,6 +105,7 @@ begin ); RegisterFile_WritePort(0 to C_Num_Version_Header -1) <= VersionData; RegisterFile_WritePort(C_Num_Version_Header to C_Num_Version_Register -1) <= UID_vec; + Version <= to_Version_Register(RegisterFile_ReadPort); --------------------------------- -- Generate data for UID-vector diff --git a/src/mem/mem_GitVersionRegister.pkg.vhdl b/src/mem/mem_GitVersionRegister.pkg.vhdl index 046856354..26d6daa2a 100644 --- a/src/mem/mem_GitVersionRegister.pkg.vhdl +++ b/src/mem/mem_GitVersionRegister.pkg.vhdl @@ -59,9 +59,9 @@ package mem_GitVersionRegister is NumberModule : std_logic_vector(23 downto 0); VersionOfVersionReg : std_logic_vector(7 downto 0); - VivadoVersion_Year : std_logic_vector(15 downto 0); - VivadoVersion_Release : std_logic_vector(7 downto 0); - VivadoVersion_SubRelease : std_logic_vector(7 downto 0); + ToolVersion_Year : std_logic_vector(15 downto 0); + ToolVersion_Release : std_logic_vector(7 downto 0); + ToolVersion_SubRelease : std_logic_vector(7 downto 0); ProjektName : std_logic_vector(159 downto 0); end record; @@ -70,7 +70,9 @@ package mem_GitVersionRegister is Version_Major : std_logic_vector(7 downto 0); Version_Minor : std_logic_vector(7 downto 0); Version_Release : std_logic_vector(7 downto 0); - Version_Flags : std_logic_vector(7 downto 0); + Version_CommitsToTag : std_logic_vector(5 downto 0); + Version_DirtyUntracked : std_logic; + Version_DirtyModified : std_logic; GitHash : std_logic_vector(159 downto 0); @@ -94,6 +96,12 @@ package mem_GitVersionRegister is User_ID : std_logic_vector(95 downto 0); end record; + type T_Version_Register is record + Common : T_Version_Register_Common; + Top : T_Version_Register_Top; + UID : T_Version_Register_UID; + end record; + constant C_VERSION_REGISTER_UID_INIT : T_Version_Register_UID := ( UID => (others => '0'), User_eFuse => (others => '0'), @@ -116,6 +124,7 @@ package mem_GitVersionRegister is function to_SLVV_32_Common (data : T_Version_Register_Common) return T_SLVV_32; function to_SLVV_32_Top (data : T_Version_Register_Top) return T_SLVV_32; + function to_Version_Register (register_vector : T_SLVV) return T_Version_Register; function get_Dummy_Descriptor(len : natural) return T_AXI4_Register_Vector; function get_Version_Descriptor return T_AXI4_Register_Vector; @@ -135,7 +144,7 @@ package body mem_GitVersionRegister is addr := addr +4; pos := pos +1; temp(pos) := to_AXI4_Register(Name => "Common.NumberModule_VersionOfVersionReg", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); addr := addr +4; pos := pos +1; - temp(pos) := to_AXI4_Register(Name => "Common.VivadoVersion", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + temp(pos) := to_AXI4_Register(Name => "Common.ToolVersion", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); addr := addr +4; pos := pos +1; for i in 0 to 4 loop temp(pos) := to_AXI4_Register(Name => "Common.ProjektName(" & integer'image(i) & ")", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); @@ -176,6 +185,55 @@ package body mem_GitVersionRegister is return temp(0 to pos -1); end function; + function to_Version_Register (reg_vec : T_SLVV) return T_Version_Register is + variable temp : T_Version_Register; + begin + temp.Common.BuildDate_Day := reg_vec(0)(31 downto 24); + temp.Common.BuildDate_Month := reg_vec(0)(23 downto 16); + temp.Common.BuildDate_Year := reg_vec(0)(15 downto 0); + temp.Common.NumberModule := reg_vec(1)(31 downto 8); + temp.Common.VersionOfVersionReg := reg_vec(1)( 7 downto 0); + temp.Common.ToolVersion_Year := reg_vec(2)(31 downto 16); + temp.Common.ToolVersion_Release := reg_vec(2)(15 downto 8); + temp.Common.ToolVersion_SubRelease := reg_vec(2)( 7 downto 0); + for i in 0 to 4 loop + temp.Common.ProjektName(32 * i +31 downto 32 * i) := reg_vec(i + 3); + end loop; + + temp.Top.Version_Major := reg_vec(8)(31 downto 24); + temp.Top.Version_Minor := reg_vec(8)(23 downto 16); + temp.Top.Version_Release := reg_vec(8)(15 downto 8); + temp.Top.Version_CommitsToTag := reg_vec(8)( 7 downto 2); + temp.Top.Version_DirtyUntracked := reg_vec(8)(1); + temp.Top.Version_DirtyModified := reg_vec(8)(0); + for i in 0 to 4 loop + temp.Top.GitHash(32 * i +31 downto 32 * i) := reg_vec(i + 9); + end loop; + temp.Top.GitDate_Day := reg_vec(14)(31 downto 24); + temp.Top.GitDate_Month := reg_vec(14)(23 downto 16); + temp.Top.GitDate_Year := reg_vec(14)(15 downto 0); + temp.Top.GitTime_Hour := reg_vec(15)(31 downto 24); + temp.Top.GitTime_Min := reg_vec(15)(23 downto 16); + temp.Top.GitTime_Sec := reg_vec(15)(15 downto 8); + temp.Top.GitTime_Zone := reg_vec(15)( 7 downto 0); + for i in 0 to 15 loop + temp.Top.BranchName_Tag(32 * i +31 downto 32 * i) := reg_vec(i + 16); + end loop; + for i in 0 to 31 loop + temp.Top.GitURL(32 * i +31 downto 32 * i) := reg_vec(i + 32); + end loop; + + for i in 0 to 3 loop + temp.UID.UID(32 * i +31 downto 32 * i) := reg_vec(i + 64); + end loop; + temp.UID.User_eFuse := reg_vec(68); + for i in 0 to 2 loop + temp.UID.User_ID(32 * i +31 downto 32 * i) := reg_vec(i + 69); + end loop; + + return temp; + end function; + function get_Dummy_Descriptor(len : natural) return T_AXI4_Register_Vector is variable descriptor : T_AXI4_Register_Vector(0 to len -1); @@ -196,7 +254,7 @@ package body mem_GitVersionRegister is begin temp(0) := data.BuildDate_Day & data.BuildDate_Month & data.BuildDate_Year; temp(1) := data.NumberModule & data.VersionOfVersionReg; - temp(2) := data.VivadoVersion_Year & data.VivadoVersion_Release & data.VivadoVersion_SubRelease; + temp(2) := data.ToolVersion_Year & data.ToolVersion_Release & data.ToolVersion_SubRelease; for i in name'reverse_range loop temp(i +3) := name(i); end loop; @@ -213,7 +271,7 @@ package body mem_GitVersionRegister is variable idx : natural := 0; begin - temp(0) := data.Version_Major & data.Version_Minor & data.Version_Release & data.Version_Flags; + temp(0) := data.Version_Major & data.Version_Minor & data.Version_Release & data.Version_CommitsToTag & data.Version_DirtyUntracked & data.Version_DirtyModified; idx := idx +1; for i in hash'reverse_range loop @@ -289,17 +347,17 @@ package body mem_GitVersionRegister is Len := CurrentLine'length; read(CurrentLine, result_s(1 to Len), Good); assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; - HW_BUILD_VERSION_COMMON.VivadoVersion_Year := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 16)); + HW_BUILD_VERSION_COMMON.ToolVersion_Year := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 16)); readline(FileHandle, CurrentLine); Len := CurrentLine'length; read(CurrentLine, result_s(1 to Len), Good); assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; - HW_BUILD_VERSION_COMMON.VivadoVersion_Release := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + HW_BUILD_VERSION_COMMON.ToolVersion_Release := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); readline(FileHandle, CurrentLine); Len := CurrentLine'length; read(CurrentLine, result_s(1 to Len), Good); assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; - HW_BUILD_VERSION_COMMON.VivadoVersion_SubRelease := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + HW_BUILD_VERSION_COMMON.ToolVersion_SubRelease := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); readline(FileHandle, CurrentLine); Len := CurrentLine'length; @@ -327,17 +385,19 @@ package body mem_GitVersionRegister is Len := CurrentLine'length; read(CurrentLine, result_s(1 to Len), Good); assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; - HW_BUILD_VERSION_TOP.Version_Flags(7 downto 2) := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 6)); + HW_BUILD_VERSION_TOP.Version_CommitsToTag := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 6)); readline(FileHandle, CurrentLine); Len := CurrentLine'length; read(CurrentLine, result_s(1 to Len), Good); assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; - HW_BUILD_VERSION_TOP.Version_Flags(1 downto 1) := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 1)); + result_h(0 downto 0) := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 1)); -- result_h is unused until here + HW_BUILD_VERSION_TOP.Version_DirtyUntracked := result_h(0); readline(FileHandle, CurrentLine); Len := CurrentLine'length; read(CurrentLine, result_s(1 to Len), Good); assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; - HW_BUILD_VERSION_TOP.Version_Flags(0 downto 0) := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 1)); + result_h(0 downto 0) := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 1)); -- result_h is unused until here + HW_BUILD_VERSION_TOP.Version_DirtyModified := result_h(0); readline(FileHandle, CurrentLine); Len := CurrentLine'length; From ffa6f1b3563b681d59a8162003a7c29050404b6d Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Sun, 23 Nov 2025 23:17:16 +0100 Subject: [PATCH 2/5] Add missing sources to TerosHDL project file --- prj/TerosHDL/PileOfCores_TerosHDL.yml | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/prj/TerosHDL/PileOfCores_TerosHDL.yml b/prj/TerosHDL/PileOfCores_TerosHDL.yml index a3251ac50..89226cce2 100644 --- a/prj/TerosHDL/PileOfCores_TerosHDL.yml +++ b/prj/TerosHDL/PileOfCores_TerosHDL.yml @@ -1,7 +1,7 @@ name: PileOfCores project_disk_path: '' project_type: genericProject -toplevel: ../../src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl +toplevel: ../../src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl files: - name: ../../src/common/common.vhdl file_type: vhdlSource @@ -1909,6 +1909,22 @@ files: logical_name: PoC is_manual: true source_type: none + - name: ../../src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl + file_type: vhdlSource + file_version: '2008' + is_include_file: false + include_path: '' + logical_name: PoC + is_manual: true + source_type: none + - name: ../../src/mem/mem_GitVersionRegister.pkg.vhdl + file_type: vhdlSource + file_version: '2008' + is_include_file: false + include_path: '' + logical_name: PoC + is_manual: true + source_type: none hooks: pre_build: [] post_build: [] From 62abd4c98b752c376c498b7134752bfa8e6b9459 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Mon, 24 Nov 2025 17:57:05 +0100 Subject: [PATCH 3/5] fix function declaration --- src/mem/mem_GitVersionRegister.pkg.vhdl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mem/mem_GitVersionRegister.pkg.vhdl b/src/mem/mem_GitVersionRegister.pkg.vhdl index 26d6daa2a..71f08138c 100644 --- a/src/mem/mem_GitVersionRegister.pkg.vhdl +++ b/src/mem/mem_GitVersionRegister.pkg.vhdl @@ -124,7 +124,7 @@ package mem_GitVersionRegister is function to_SLVV_32_Common (data : T_Version_Register_Common) return T_SLVV_32; function to_SLVV_32_Top (data : T_Version_Register_Top) return T_SLVV_32; - function to_Version_Register (register_vector : T_SLVV) return T_Version_Register; + function to_Version_Register (reg_vec : T_SLVV) return T_Version_Register; function get_Dummy_Descriptor(len : natural) return T_AXI4_Register_Vector; function get_Version_Descriptor return T_AXI4_Register_Vector; From bf3b5b0468465b55bca2418dcec1a811b3f342e8 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Mon, 24 Nov 2025 17:58:06 +0100 Subject: [PATCH 4/5] create function for reading mem-content directly into record-constant --- src/mem/mem_GitVersionRegister.pkg.vhdl | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mem/mem_GitVersionRegister.pkg.vhdl b/src/mem/mem_GitVersionRegister.pkg.vhdl index 71f08138c..a3264689a 100644 --- a/src/mem/mem_GitVersionRegister.pkg.vhdl +++ b/src/mem/mem_GitVersionRegister.pkg.vhdl @@ -130,13 +130,14 @@ package mem_GitVersionRegister is function get_Version_Descriptor return T_AXI4_Register_Vector; impure function read_Version_from_mem(FileName : string) return T_SLVV_32; + impure function to_Version_Register (FileName : string) return T_Version_Register; end package; package body mem_GitVersionRegister is function get_Version_Descriptor return T_AXI4_Register_Vector is - variable temp : T_AXI4_Register_Vector(0 to 127); + variable temp : T_AXI4_Register_Vector(0 to C_Num_Version_Register -1); variable pos : natural := 0; variable addr : natural := 0; begin @@ -468,4 +469,14 @@ package body mem_GitVersionRegister is return temp; end function; + + impure function to_Version_Register (FileName : string) return T_Version_Register is + variable VersionData : T_SLVV_32(0 to C_Num_Version_Register - 1); + + begin + VersionData(0 to C_Num_Version_Header - 1) := read_Version_from_mem(FileName); + VersionData(C_Num_Version_Header to C_Num_Version_Register - 1) := (others => (others => '0')); + return to_Version_Register(VersionData); + end function; + end package body; From bcc92ddc835ed85326a579af220c7ccdd858e319 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Mon, 24 Nov 2025 18:01:52 +0100 Subject: [PATCH 5/5] Add description for constant usage --- src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl index 60764f9e9..070bc37ab 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl @@ -10,9 +10,12 @@ -- ------------------------------------- -- This version register can be auto filled with constants from Git. Software -- can read from what revision a firmware (bitstream, PL code) was build. --- +-- -- The Version-out-Port is used to make all values accessible to the PL. This -- can be used by another interface than AXI4L, if necessary. +-- If you dont need the UID field, use this to directly create a constant out of +-- the mem-file: +-- constant My_Version : T_Version_Register := to_Version_Register(MEM_PATH); -- -- Use the pre-synthesis script from -- PoC/tools/git/preSynth_GitVersionRegister_Vivado.tcl