From 4d88da8a7dd849863715bf97ab528484e91be9ca Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 13 Oct 2025 12:06:48 +0200 Subject: [PATCH 01/56] Fixed cross-reference labels. --- docs/ChangeLog/2014/index.rst | 2 +- docs/ChangeLog/2015/index.rst | 2 +- docs/ChangeLog/2016/index.rst | 2 +- docs/ChangeLog/2016/v1.x.rst | 42 +++++++++---------- .../ConstraintFiles/Altera/CycloneIII/DE0.rst | 4 -- .../Altera/CycloneIII/DE0nano.rst | 4 -- .../Altera/CycloneIII/index.rst | 12 ------ docs/ConstraintFiles/Altera/StratixIV/DE4.rst | 4 -- .../Altera/StratixIV/index.rst | 10 ----- .../ConstraintFiles/Xilinx/Spartan3/S3ESK.rst | 4 -- docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst | 4 -- .../ConstraintFiles/Xilinx/Spartan3/index.rst | 12 ------ .../ConstraintFiles/Xilinx/Spartan6/Atlys.rst | 4 -- .../ConstraintFiles/Xilinx/Spartan6/index.rst | 10 ----- docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst | 4 -- docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst | 4 -- docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst | 4 -- docs/ConstraintFiles/Xilinx/Virtex5/index.rst | 14 ------- docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst | 4 -- docs/ConstraintFiles/Xilinx/Virtex6/index.rst | 10 ----- docs/ConstraintFiles/index.rst | 7 +--- docs/ConstraintFiles/misc/index.rst | 10 ----- .../ConstraintFiles/{misc => }/sync/index.rst | 0 .../{misc => }/sync/sync_Bits.rst | 0 .../{misc => }/sync/sync_Command.rst | 0 .../{misc => }/sync/sync_Reset.rst | 0 .../{misc => }/sync/sync_Vector.rst | 0 docs/GetInvolved/index.rst | 4 +- docs/IPCores/alt/index.rst | 2 +- docs/IPCores/arith/arith.pkg.rst | 20 ++++----- docs/IPCores/arith/arith_addw.rst | 2 +- docs/IPCores/arith/arith_bcdcollect.rst | 2 +- docs/IPCores/arith/arith_carrychain_inc.rst | 2 +- docs/IPCores/arith/arith_convert_bin2bcd.rst | 2 +- docs/IPCores/arith/arith_counter_bcd.rst | 2 +- docs/IPCores/arith/arith_counter_free.rst | 2 +- docs/IPCores/arith/arith_counter_gray.rst | 2 +- docs/IPCores/arith/arith_counter_ring.rst | 2 +- docs/IPCores/arith/arith_div.rst | 2 +- docs/IPCores/arith/arith_firstone.rst | 2 +- docs/IPCores/arith/arith_muls_wide.rst | 2 +- docs/IPCores/arith/arith_prefix_and.rst | 2 +- docs/IPCores/arith/arith_prefix_or.rst | 2 +- docs/IPCores/arith/arith_prng.rst | 2 +- docs/IPCores/arith/arith_same.rst | 2 +- docs/IPCores/arith/arith_scaler.rst | 2 +- docs/IPCores/arith/arith_shifter_barrel.rst | 2 +- docs/IPCores/arith/arith_sqrt.rst | 2 +- docs/IPCores/arith/index.rst | 38 ++++++++--------- docs/IPCores/bus/bus_Arbiter.rst | 2 +- docs/IPCores/bus/index.rst | 8 ++-- docs/IPCores/bus/stream/index.rst | 2 +- docs/IPCores/bus/stream/stream.pkg.rst | 2 +- docs/IPCores/bus/stream/stream_DeMux.rst | 2 +- docs/IPCores/bus/stream/stream_FIFO.rst | 2 +- .../bus/stream/stream_FrameGenerator.rst | 2 +- docs/IPCores/bus/stream/stream_Mirror.rst | 2 +- docs/IPCores/bus/stream/stream_Mux.rst | 2 +- docs/IPCores/bus/stream/stream_Sink.rst | 2 +- docs/IPCores/bus/stream/stream_Source.rst | 2 +- docs/IPCores/bus/wb/index.rst | 2 +- docs/IPCores/bus/wb/wb.pkg.rst | 2 +- docs/IPCores/bus/wb/wb_fifo_adapter.rst | 2 +- docs/IPCores/bus/wb/wb_ocram.rst | 2 +- docs/IPCores/bus/wb/wb_uart_wrapper.rst | 2 +- docs/IPCores/cache/cache_cpu.rst | 8 ++-- docs/IPCores/cache/cache_mem.rst | 12 +++--- docs/IPCores/cache/cache_par.rst | 2 +- docs/IPCores/cache/cache_par2.rst | 4 +- .../cache/cache_replacement_policy.rst | 2 +- docs/IPCores/cache/cache_tagunit_par.rst | 2 +- docs/IPCores/cache/cache_tagunit_seq.rst | 2 +- docs/IPCores/cache/index.rst | 16 +++---- docs/IPCores/comm/comm.pkg.rst | 2 +- docs/IPCores/comm/comm_crc.rst | 2 +- docs/IPCores/comm/comm_scramble.rst | 2 +- docs/IPCores/comm/index.rst | 2 +- docs/IPCores/comm/remote/index.rst | 2 +- .../comm/remote/remote_terminal_control.rst | 2 +- docs/IPCores/dstruct/dstruct_deque.rst | 2 +- docs/IPCores/dstruct/dstruct_stack.rst | 2 +- docs/IPCores/dstruct/index.rst | 8 ++-- docs/IPCores/fifo/fifo.pkg.rst | 2 +- docs/IPCores/fifo/fifo_cc_got.rst | 8 ++-- docs/IPCores/fifo/fifo_cc_got_tempgot.rst | 2 +- docs/IPCores/fifo/fifo_cc_got_tempput.rst | 2 +- docs/IPCores/fifo/fifo_dc_got_sm.rst | 2 +- docs/IPCores/fifo/fifo_ic_assembly.rst | 2 +- docs/IPCores/fifo/fifo_ic_got.rst | 2 +- docs/IPCores/fifo/fifo_shift.rst | 2 +- docs/IPCores/fifo/fifo_stage.rst | 2 +- docs/IPCores/fifo/index.rst | 18 ++++---- docs/IPCores/io/ddrio/ddrio.pkg.rst | 2 +- docs/IPCores/io/ddrio/ddrio_in.rst | 2 +- docs/IPCores/io/ddrio/ddrio_inout.rst | 2 +- docs/IPCores/io/ddrio/ddrio_out.rst | 2 +- docs/IPCores/io/ddrio/index.rst | 8 ++-- docs/IPCores/io/iic/iic.pkg.rst | 2 +- docs/IPCores/io/iic/iic_BusController.rst | 2 +- docs/IPCores/io/iic/iic_Controller.rst | 2 +- .../IPCores/io/iic/iic_Controller_SFF8431.rst | 2 +- docs/IPCores/io/iic/iic_Switch_PCA9548A.rst | 2 +- docs/IPCores/io/iic/index.rst | 2 +- docs/IPCores/io/index.rst | 2 +- docs/IPCores/io/io.pkg.rst | 2 +- docs/IPCores/io/io_7SegmentMux_BCD.rst | 2 +- docs/IPCores/io/io_7SegmentMux_HEX.rst | 2 +- docs/IPCores/io/io_Debounce.rst | 2 +- docs/IPCores/io/io_FanControl.rst | 2 +- docs/IPCores/io/io_FrequencyCounter.rst | 2 +- docs/IPCores/io/io_GlitchFilter.rst | 2 +- docs/IPCores/io/io_KeyPadScanner.rst | 2 +- docs/IPCores/io/io_PulseWidthModulation.rst | 2 +- docs/IPCores/io/io_TimingCounter.rst | 2 +- docs/IPCores/io/jtag/index.rst | 2 +- docs/IPCores/io/lcd/index.rst | 2 +- docs/IPCores/io/lcd/lcd.pkg.rst | 2 +- docs/IPCores/io/lcd/lcd_LCDBuffer.rst | 2 +- docs/IPCores/io/lcd/lcd_LCDBusController.rst | 2 +- .../io/lcd/lcd_LCDController_KS0066U.rst | 2 +- docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst | 2 +- docs/IPCores/io/lcd/lcd_dotmatrix.rst | 2 +- docs/IPCores/io/mdio/index.rst | 2 +- docs/IPCores/io/mdio/mdio_Controller.rst | 2 +- docs/IPCores/io/mdio/mdio_IIC_Adapter.rst | 2 +- docs/IPCores/io/ow/index.rst | 2 +- docs/IPCores/io/pio/index.rst | 2 +- docs/IPCores/io/pio/pio_fifo_in.rst | 2 +- docs/IPCores/io/pio/pio_fifo_out.rst | 2 +- docs/IPCores/io/pio/pio_in.rst | 2 +- docs/IPCores/io/pio/pio_out.rst | 2 +- docs/IPCores/io/pmod/index.rst | 8 ++-- docs/IPCores/io/pmod/pmod.pkg.rst | 2 +- docs/IPCores/io/pmod/pmod_KYPD.rst | 2 +- docs/IPCores/io/pmod/pmod_SSD.rst | 2 +- docs/IPCores/io/pmod/pmod_USBUART.rst | 2 +- docs/IPCores/io/ps2/index.rst | 2 +- docs/IPCores/io/uart/index.rst | 10 ++--- docs/IPCores/io/uart/uart.pkg.rst | 2 +- docs/IPCores/io/uart/uart_bclk.rst | 2 +- docs/IPCores/io/uart/uart_fifo.rst | 2 +- docs/IPCores/io/uart/uart_ft245.rst | 2 +- docs/IPCores/io/uart/uart_rx.rst | 2 +- docs/IPCores/io/uart/uart_tx.rst | 2 +- docs/IPCores/io/vga/index.rst | 2 +- docs/IPCores/io/vga/vga.pkg.rst | 2 +- docs/IPCores/io/vga/vga_phy.rst | 2 +- docs/IPCores/io/vga/vga_phy_ch7301c.rst | 2 +- docs/IPCores/io/vga/vga_timing.rst | 2 +- .../ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 2 +- docs/IPCores/mem/ddr2/index.rst | 4 +- .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 2 +- docs/IPCores/mem/ddr3/index.rst | 4 +- docs/IPCores/mem/index.rst | 16 +++---- docs/IPCores/mem/lut/index.rst | 4 +- docs/IPCores/mem/lut/lut_Sine.rst | 2 +- docs/IPCores/mem/mem.pkg.rst | 4 +- docs/IPCores/mem/ocram/index.rst | 16 +++---- docs/IPCores/mem/ocram/ocram.pkg.rst | 2 +- docs/IPCores/mem/ocram/ocram_esdp.rst | 6 +-- docs/IPCores/mem/ocram/ocram_sdp.rst | 4 +- docs/IPCores/mem/ocram/ocram_sdp_wf.rst | 2 +- docs/IPCores/mem/ocram/ocram_sp.rst | 2 +- docs/IPCores/mem/ocram/ocram_tdp.rst | 4 +- docs/IPCores/mem/ocram/ocram_tdp_sim.rst | 2 +- docs/IPCores/mem/ocram/ocram_tdp_wf.rst | 4 +- docs/IPCores/mem/ocrom/index.rst | 6 +-- docs/IPCores/mem/ocrom/ocrom.pkg.rst | 2 +- docs/IPCores/mem/ocrom/ocrom_dp.rst | 2 +- docs/IPCores/mem/ocrom/ocrom_sp.rst | 2 +- docs/IPCores/mem/sdram/index.rst | 16 +++---- docs/IPCores/mem/sdram/sdram_ctrl_de0.rst | 4 +- docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst | 2 +- docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst | 4 +- .../mem/sdram/sdram_ctrl_phy_s3esk.rst | 4 +- docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst | 2 +- docs/IPCores/misc/filter/filter_and.rst | 2 +- docs/IPCores/misc/filter/filter_mean.rst | 2 +- docs/IPCores/misc/filter/filter_or.rst | 2 +- docs/IPCores/misc/filter/index.rst | 8 ++-- docs/IPCores/misc/gearbox/gearbox_down_cc.rst | 2 +- docs/IPCores/misc/gearbox/gearbox_down_dc.rst | 2 +- docs/IPCores/misc/gearbox/gearbox_up_cc.rst | 2 +- docs/IPCores/misc/gearbox/gearbox_up_dc.rst | 2 +- docs/IPCores/misc/gearbox/index.rst | 10 ++--- docs/IPCores/misc/index.rst | 24 +++++------ docs/IPCores/misc/misc.pkg.rst | 2 +- docs/IPCores/misc/misc_BitwidthConverter.rst | 2 +- docs/IPCores/misc/misc_ByteAligner.rst | 2 +- docs/IPCores/misc/misc_Delay.rst | 2 +- .../misc/misc_FrequencyMeasurement.rst | 2 +- docs/IPCores/misc/misc_PulseTrain.rst | 2 +- docs/IPCores/misc/misc_Sequencer.rst | 2 +- docs/IPCores/misc/misc_StrobeGenerator.rst | 2 +- docs/IPCores/misc/misc_StrobeLimiter.rst | 2 +- docs/IPCores/misc/misc_WordAligner.rst | 2 +- docs/IPCores/misc/misc_bit_lz.rst | 2 +- docs/IPCores/misc/stat/index.rst | 10 ++--- docs/IPCores/misc/stat/stat_Average.rst | 2 +- docs/IPCores/misc/stat/stat_Histogram.rst | 2 +- docs/IPCores/misc/stat/stat_Maximum.rst | 2 +- docs/IPCores/misc/stat/stat_Minimum.rst | 2 +- docs/IPCores/misc/sync/index.rst | 22 +++++----- docs/IPCores/misc/sync/sync.pkg.rst | 2 +- docs/IPCores/misc/sync/sync_Bits.rst | 2 +- docs/IPCores/misc/sync/sync_Command.rst | 2 +- docs/IPCores/misc/sync/sync_Pulse.rst | 2 +- docs/IPCores/misc/sync/sync_Reset.rst | 2 +- docs/IPCores/misc/sync/sync_Strobe.rst | 2 +- docs/IPCores/misc/sync/sync_Vector.rst | 2 +- .../net/arp/arp_BroadCast_Receiver.rst | 2 +- .../net/arp/arp_BroadCast_Requester.rst | 2 +- docs/IPCores/net/arp/arp_Cache.rst | 2 +- docs/IPCores/net/arp/arp_IPPool.rst | 2 +- docs/IPCores/net/arp/arp_Tester.rst | 2 +- docs/IPCores/net/arp/arp_UniCast_Receiver.rst | 2 +- .../IPCores/net/arp/arp_UniCast_Responder.rst | 2 +- docs/IPCores/net/arp/arp_Wrapper.rst | 2 +- docs/IPCores/net/arp/index.rst | 2 +- docs/IPCores/net/eth/eth_GEMAC_GMII.rst | 2 +- docs/IPCores/net/eth/eth_GEMAC_RX.rst | 2 +- docs/IPCores/net/eth/eth_GEMAC_TX.rst | 2 +- docs/IPCores/net/eth/eth_PHYController.rst | 2 +- .../eth/eth_PHYController_Marvell_88E1111.rst | 2 +- docs/IPCores/net/eth/eth_Wrapper.rst | 2 +- docs/IPCores/net/eth/index.rst | 2 +- docs/IPCores/net/icmpv4/icmpv4_RX.rst | 2 +- docs/IPCores/net/icmpv4/icmpv4_TX.rst | 2 +- docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst | 2 +- docs/IPCores/net/icmpv4/index.rst | 2 +- docs/IPCores/net/icmpv6/icmpv6_RX.rst | 2 +- docs/IPCores/net/icmpv6/icmpv6_TX.rst | 2 +- docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst | 2 +- docs/IPCores/net/icmpv6/index.rst | 2 +- docs/IPCores/net/index.rst | 26 ++++++------ docs/IPCores/net/ipv4/index.rst | 2 +- docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst | 2 +- docs/IPCores/net/ipv4/ipv4_RX.rst | 2 +- docs/IPCores/net/ipv4/ipv4_TX.rst | 2 +- docs/IPCores/net/ipv4/ipv4_Wrapper.rst | 2 +- docs/IPCores/net/ipv6/index.rst | 2 +- docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst | 2 +- docs/IPCores/net/ipv6/ipv6_RX.rst | 2 +- docs/IPCores/net/ipv6/ipv6_TX.rst | 2 +- docs/IPCores/net/ipv6/ipv6_Wrapper.rst | 2 +- docs/IPCores/net/mac/index.rst | 2 +- docs/IPCores/net/mac/mac_FrameLoopback.rst | 2 +- .../IPCores/net/mac/mac_RX_DestMAC_Switch.rst | 2 +- docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst | 2 +- docs/IPCores/net/mac/mac_RX_Type_Switch.rst | 2 +- .../net/mac/mac_TX_DestMAC_Prepender.rst | 2 +- .../net/mac/mac_TX_SrcMAC_Prepender.rst | 2 +- .../IPCores/net/mac/mac_TX_Type_Prepender.rst | 2 +- docs/IPCores/net/mac/mac_Wrapper.rst | 2 +- docs/IPCores/net/ndp/index.rst | 2 +- docs/IPCores/net/ndp/ndp_DestinationCache.rst | 2 +- docs/IPCores/net/ndp/ndp_FSMQuery.rst | 2 +- docs/IPCores/net/ndp/ndp_NeighborCache.rst | 2 +- docs/IPCores/net/ndp/ndp_Wrapper.rst | 2 +- docs/IPCores/net/net.pkg.rst | 2 +- docs/IPCores/net/net_FrameChecksum.rst | 2 +- docs/IPCores/net/net_FrameLoopback.rst | 2 +- .../net/net_FramePerformanceCounter.rst | 2 +- docs/IPCores/net/stack/index.rst | 2 +- docs/IPCores/net/stack/stack_UDPv4.rst | 2 +- docs/IPCores/net/udp/index.rst | 2 +- docs/IPCores/net/udp/udp_FrameLoopback.rst | 2 +- docs/IPCores/net/udp/udp_RX.rst | 2 +- docs/IPCores/net/udp/udp_TX.rst | 2 +- docs/IPCores/net/udp/udp_Wrapper.rst | 2 +- docs/IPCores/sort/index.rst | 14 +++---- docs/IPCores/sort/sort_ExpireList.rst | 2 +- docs/IPCores/sort/sort_InsertSort.rst | 2 +- .../IPCores/sort/sort_LeastFrequentlyUsed.rst | 2 +- docs/IPCores/sort/sort_lru_cache.rst | 2 +- docs/IPCores/sort/sort_lru_list.rst | 2 +- docs/IPCores/sort/sortnet/index.rst | 16 +++---- docs/IPCores/sort/sortnet/sortnet.pkg.rst | 8 ++-- .../sort/sortnet/sortnet_BitonicSort.rst | 2 +- .../sortnet/sortnet_MergeSort_Streamed.rst | 2 +- .../sort/sortnet/sortnet_OddEvenMergeSort.rst | 2 +- .../sort/sortnet/sortnet_OddEvenSort.rst | 2 +- .../sort/sortnet/sortnet_Stream_Adapter.rst | 2 +- .../sort/sortnet/sortnet_Stream_Adapter2.rst | 2 +- .../sort/sortnet/sortnet_Transform.rst | 2 +- docs/IPCores/xil/index.rst | 22 +++++----- docs/IPCores/xil/reconfig/index.rst | 6 +-- .../xil/reconfig/reconfig_icap_fsm.rst | 2 +- .../xil/reconfig/reconfig_icap_wrapper.rst | 2 +- docs/IPCores/xil/xil.pkg.rst | 2 +- docs/IPCores/xil/xil_BSCAN.rst | 2 +- docs/IPCores/xil/xil_DRP_BusMux.rst | 2 +- docs/IPCores/xil/xil_DRP_BusSync.rst | 2 +- docs/IPCores/xil/xil_ICAP.rst | 2 +- docs/IPCores/xil/xil_Reconfigurator.rst | 2 +- docs/IPCores/xil/xil_SystemMonitor.rst | 2 +- docs/Miscelaneous/ThirdParty.rst | 2 +- docs/QuickStart.rst | 26 ++++++------ docs/References/CmdRefs/Compile.rst | 4 +- docs/References/CmdRefs/PoC.rst | 2 +- docs/References/CmdRefs/Wrapper.rst | 2 +- docs/References/Database.rst | 34 +++++++-------- docs/References/FileFormats/FilesFormat.rst | 2 +- docs/References/FileFormats/IniFormat.rst | 2 +- docs/References/FileFormats/RulesFormat.rst | 2 +- docs/References/KnownIssues.rst | 18 ++++---- docs/UsingPoC/AddingIPCores.rst | 2 +- docs/UsingPoC/Download.rst | 12 +++--- docs/UsingPoC/Integration.rst | 4 +- docs/UsingPoC/PoCConfiguration.rst | 26 ++++++------ docs/UsingPoC/PrecompilingVendorLibraries.rst | 34 +++++++-------- docs/UsingPoC/ProjectManagement.rst | 2 +- docs/UsingPoC/Requirements.rst | 12 +++--- docs/UsingPoC/Simulation.rst | 22 +++++----- docs/UsingPoC/Synthesis.rst | 24 +++++------ docs/UsingPoC/VHDLConfiguration.rst | 6 +-- docs/UsingPoC/index.rst | 14 +++---- docs/WhatIsPoC/SupportedToolChains.rst | 2 +- 318 files changed, 599 insertions(+), 722 deletions(-) delete mode 100644 docs/ConstraintFiles/Altera/CycloneIII/DE0.rst delete mode 100644 docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst delete mode 100644 docs/ConstraintFiles/Altera/CycloneIII/index.rst delete mode 100644 docs/ConstraintFiles/Altera/StratixIV/DE4.rst delete mode 100644 docs/ConstraintFiles/Altera/StratixIV/index.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Spartan3/index.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Spartan6/index.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Virtex5/index.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst delete mode 100644 docs/ConstraintFiles/Xilinx/Virtex6/index.rst delete mode 100644 docs/ConstraintFiles/misc/index.rst rename docs/ConstraintFiles/{misc => }/sync/index.rst (100%) rename docs/ConstraintFiles/{misc => }/sync/sync_Bits.rst (100%) rename docs/ConstraintFiles/{misc => }/sync/sync_Command.rst (100%) rename docs/ConstraintFiles/{misc => }/sync/sync_Reset.rst (100%) rename docs/ConstraintFiles/{misc => }/sync/sync_Vector.rst (100%) diff --git a/docs/ChangeLog/2014/index.rst b/docs/ChangeLog/2014/index.rst index 5a16b240d..502d25c0c 100644 --- a/docs/ChangeLog/2014/index.rst +++ b/docs/ChangeLog/2014/index.rst @@ -1,4 +1,4 @@ -.. _CHANGE:2014: +.. _CHANGE/2014: 2014 #### diff --git a/docs/ChangeLog/2015/index.rst b/docs/ChangeLog/2015/index.rst index 22bcfb5ff..92724c063 100644 --- a/docs/ChangeLog/2015/index.rst +++ b/docs/ChangeLog/2015/index.rst @@ -1,4 +1,4 @@ -.. _CHANGE:2015: +.. _CHANGE/2015: 2015 #### diff --git a/docs/ChangeLog/2016/index.rst b/docs/ChangeLog/2016/index.rst index 7ce940191..3e5c79ed6 100644 --- a/docs/ChangeLog/2016/index.rst +++ b/docs/ChangeLog/2016/index.rst @@ -1,4 +1,4 @@ -.. _CHANGE:2016: +.. _CHANGE/2016: 2016 #### diff --git a/docs/ChangeLog/2016/v1.x.rst b/docs/ChangeLog/2016/v1.x.rst index f690763d3..d414fd0e7 100644 --- a/docs/ChangeLog/2016/v1.x.rst +++ b/docs/ChangeLog/2016/v1.x.rst @@ -10,36 +10,36 @@ Already documented changes are available on the ``release`` branch at GitHub. * New Entities - * :ref:`IP:ocram_sdp_wf` - * :ref:`IP:ocram_tdp_wf` - * :ref:`IP:cache_par2` - * :ref:`IP:cache_cpu` - * :ref:`IP:cache_mem` - * Simulation helper :ref:`IP:ocram_tdp_sim` + * :ref:`IP/ocram_sdp_wf` + * :ref:`IP/ocram_tdp_wf` + * :ref:`IP/cache_par2` + * :ref:`IP/cache_cpu` + * :ref:`IP/cache_mem` + * Simulation helper :ref:`IP/ocram_tdp_sim` * Updated Entities - * Interface of :ref:`IP:cache_tagunit_par` changed slightly. - * New port "write-mask" in :ref:`IP:ddr3_mem2mig_adapter_Series7`. - * New port "write-mask" in :ref:`IP:ddr2_mem2mig_adapter_Spartan6`. - * Fixed :ref:`IP:dstruct_deque` + * Interface of :ref:`IP/cache_tagunit_par` changed slightly. + * New port "write-mask" in :ref:`IP/ddr3_mem2mig_adapter_Series7`. + * New port "write-mask" in :ref:`IP/ddr2_mem2mig_adapter_Spartan6`. + * Fixed :ref:`IP/dstruct_deque` * New Testbenches - * Testbench for :ref:`IP:ocram_sdp_wf` - * Testbench for :ref:`IP:ocram_tdp_wf` - * Testbench for :ref:`IP:cache_par2` - * Testbench for :ref:`IP:cache_cpu` - * Testbench for :ref:`IP:cache_mem` + * Testbench for :ref:`IP/ocram_sdp_wf` + * Testbench for :ref:`IP/ocram_tdp_wf` + * Testbench for :ref:`IP/cache_par2` + * Testbench for :ref:`IP/cache_cpu` + * Testbench for :ref:`IP/cache_mem` * Updated Testbenches - * Testbench for :ref:`IP:ocram_sdp` - * Testbench for :ref:`IP:ocram_esdp` - * Testbench for :ref:`IP:ocram_tdp` - * Testbench for :ref:`IP:sortnet_BitonicSort` - * Testbench for :ref:`IP:sortnet_OddEvenSort` - * Testbench for :ref:`IP:sortnet_OddEvenMergeSort` + * Testbench for :ref:`IP/ocram_sdp` + * Testbench for :ref:`IP/ocram_esdp` + * Testbench for :ref:`IP/ocram_tdp` + * Testbench for :ref:`IP/sortnet_BitonicSort` + * Testbench for :ref:`IP/sortnet_OddEvenSort` + * Testbench for :ref:`IP/sortnet_OddEvenMergeSort` * New Constraints * Updated Constraints diff --git a/docs/ConstraintFiles/Altera/CycloneIII/DE0.rst b/docs/ConstraintFiles/Altera/CycloneIII/DE0.rst deleted file mode 100644 index 05ba9f97d..000000000 --- a/docs/ConstraintFiles/Altera/CycloneIII/DE0.rst +++ /dev/null @@ -1,4 +0,0 @@ - -ECP5 Versa -########## - diff --git a/docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst b/docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst deleted file mode 100644 index 05ba9f97d..000000000 --- a/docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst +++ /dev/null @@ -1,4 +0,0 @@ - -ECP5 Versa -########## - diff --git a/docs/ConstraintFiles/Altera/CycloneIII/index.rst b/docs/ConstraintFiles/Altera/CycloneIII/index.rst deleted file mode 100644 index dc69dbd75..000000000 --- a/docs/ConstraintFiles/Altera/CycloneIII/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -Cyclone III -########### - - * DE0 - * DE0 nano - -.. toctree:: - :hidden: - - DE0 - DE0nano diff --git a/docs/ConstraintFiles/Altera/StratixIV/DE4.rst b/docs/ConstraintFiles/Altera/StratixIV/DE4.rst deleted file mode 100644 index af207c3dc..000000000 --- a/docs/ConstraintFiles/Altera/StratixIV/DE4.rst +++ /dev/null @@ -1,4 +0,0 @@ - -DE4 -### - diff --git a/docs/ConstraintFiles/Altera/StratixIV/index.rst b/docs/ConstraintFiles/Altera/StratixIV/index.rst deleted file mode 100644 index 2f8c8ed97..000000000 --- a/docs/ConstraintFiles/Altera/StratixIV/index.rst +++ /dev/null @@ -1,10 +0,0 @@ - -Stratix IV -########## - - * DE4 - -.. toctree:: - :hidden: - - DE4 diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst b/docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst deleted file mode 100644 index a921a923d..000000000 --- a/docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst +++ /dev/null @@ -1,4 +0,0 @@ - -S3ESK -##### - diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst b/docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst deleted file mode 100644 index 91f756a19..000000000 --- a/docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst +++ /dev/null @@ -1,4 +0,0 @@ - -S3SK -#### - diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/index.rst b/docs/ConstraintFiles/Xilinx/Spartan3/index.rst deleted file mode 100644 index a78e77a5c..000000000 --- a/docs/ConstraintFiles/Xilinx/Spartan3/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -Spartan-3 -######### - - * Spartan-3 Starter Kit (S3SK) - * Spartan-3E Starter Kit (S3ESK) - -.. toctree:: - :hidden: - - S3SK - S3ESK diff --git a/docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst b/docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst deleted file mode 100644 index d6164828f..000000000 --- a/docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst +++ /dev/null @@ -1,4 +0,0 @@ - -Atlys -##### - diff --git a/docs/ConstraintFiles/Xilinx/Spartan6/index.rst b/docs/ConstraintFiles/Xilinx/Spartan6/index.rst deleted file mode 100644 index a8cb8d106..000000000 --- a/docs/ConstraintFiles/Xilinx/Spartan6/index.rst +++ /dev/null @@ -1,10 +0,0 @@ - -Spartan-6 -######### - - * Atlys - -.. toctree:: - :hidden: - - Atlys diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst b/docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst deleted file mode 100644 index 6e3180f91..000000000 --- a/docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst +++ /dev/null @@ -1,4 +0,0 @@ - -ML505 -##### - diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst b/docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst deleted file mode 100644 index 29a94894e..000000000 --- a/docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst +++ /dev/null @@ -1,4 +0,0 @@ - -ML506 -##### - diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst b/docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst deleted file mode 100644 index aba4d0eaf..000000000 --- a/docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst +++ /dev/null @@ -1,4 +0,0 @@ - -XUPV5 -##### - diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/index.rst b/docs/ConstraintFiles/Xilinx/Virtex5/index.rst deleted file mode 100644 index 7d4d6633e..000000000 --- a/docs/ConstraintFiles/Xilinx/Virtex5/index.rst +++ /dev/null @@ -1,14 +0,0 @@ - -Virtex-5 -######## - - * ML505 - * ML506 - * XUPV5 - -.. toctree:: - :hidden: - - ML505 - ML506 - XUPV5 diff --git a/docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst b/docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst deleted file mode 100644 index c9e8ab683..000000000 --- a/docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst +++ /dev/null @@ -1,4 +0,0 @@ - -ML605 -##### - diff --git a/docs/ConstraintFiles/Xilinx/Virtex6/index.rst b/docs/ConstraintFiles/Xilinx/Virtex6/index.rst deleted file mode 100644 index 54daf4580..000000000 --- a/docs/ConstraintFiles/Xilinx/Virtex6/index.rst +++ /dev/null @@ -1,10 +0,0 @@ - -Virtex-6 -######## - - * ML605 - -.. toctree:: - :hidden: - - ML605 diff --git a/docs/ConstraintFiles/index.rst b/docs/ConstraintFiles/index.rst index b593e029b..0f320f7a8 100644 --- a/docs/ConstraintFiles/index.rst +++ b/docs/ConstraintFiles/index.rst @@ -7,21 +7,18 @@ IP Core Constraint Files ************************ * fifo -* misc - - * sync - * net * eth +* sync .. toctree:: :hidden: fifo - misc net + sync Board Constraint Files diff --git a/docs/ConstraintFiles/misc/index.rst b/docs/ConstraintFiles/misc/index.rst deleted file mode 100644 index 5eda1e35a..000000000 --- a/docs/ConstraintFiles/misc/index.rst +++ /dev/null @@ -1,10 +0,0 @@ - -misc -#### - - * sync - -.. toctree:: - :hidden: - - sync/index diff --git a/docs/ConstraintFiles/misc/sync/index.rst b/docs/ConstraintFiles/sync/index.rst similarity index 100% rename from docs/ConstraintFiles/misc/sync/index.rst rename to docs/ConstraintFiles/sync/index.rst diff --git a/docs/ConstraintFiles/misc/sync/sync_Bits.rst b/docs/ConstraintFiles/sync/sync_Bits.rst similarity index 100% rename from docs/ConstraintFiles/misc/sync/sync_Bits.rst rename to docs/ConstraintFiles/sync/sync_Bits.rst diff --git a/docs/ConstraintFiles/misc/sync/sync_Command.rst b/docs/ConstraintFiles/sync/sync_Command.rst similarity index 100% rename from docs/ConstraintFiles/misc/sync/sync_Command.rst rename to docs/ConstraintFiles/sync/sync_Command.rst diff --git a/docs/ConstraintFiles/misc/sync/sync_Reset.rst b/docs/ConstraintFiles/sync/sync_Reset.rst similarity index 100% rename from docs/ConstraintFiles/misc/sync/sync_Reset.rst rename to docs/ConstraintFiles/sync/sync_Reset.rst diff --git a/docs/ConstraintFiles/misc/sync/sync_Vector.rst b/docs/ConstraintFiles/sync/sync_Vector.rst similarity index 100% rename from docs/ConstraintFiles/misc/sync/sync_Vector.rst rename to docs/ConstraintFiles/sync/sync_Vector.rst diff --git a/docs/GetInvolved/index.rst b/docs/GetInvolved/index.rst index a1986e8c3..e059f0439 100644 --- a/docs/GetInvolved/index.rst +++ b/docs/GetInvolved/index.rst @@ -107,7 +107,7 @@ organisation's account. In the following the forked repository is referenced as 2. Clone the new Fork ===================== -Clone this new fork to your machine. See :ref:`Downloading via Git clone ` +Clone this new fork to your machine. See :ref:`Downloading via Git clone ` for more details on how to clone PoC. If you have already cloned PoC, then you can setup the new fork as an additional *remote*. You should set ``VLSI-EDA/PoC`` as fetch target and the new fork ``/PoC`` as push target. @@ -147,7 +147,7 @@ Checkout the ``master`` or ``release`` branch and maybe stash outstanding change 4. Setup PoC for Developers =========================== -Run PoC's :ref:`configuration routines ` and setup the +Run PoC's :ref:`configuration routines ` and setup the developer tools. .. code-block:: PowerShell diff --git a/docs/IPCores/alt/index.rst b/docs/IPCores/alt/index.rst index c0752f3f7..6298354f1 100644 --- a/docs/IPCores/alt/index.rst +++ b/docs/IPCores/alt/index.rst @@ -1,4 +1,4 @@ -.. _NS:alt: +.. _NS/alt: PoC.alt ======== diff --git a/docs/IPCores/arith/arith.pkg.rst b/docs/IPCores/arith/arith.pkg.rst index 4857abab0..9e207bdf1 100644 --- a/docs/IPCores/arith/arith.pkg.rst +++ b/docs/IPCores/arith/arith.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:arith: +.. _PKG/arith: PoC.arith Package ================= @@ -28,19 +28,19 @@ This package holds all component declarations for this namespace. .. rubric:: Exported Components -* :ref:`PoC.arith.addw ` +* :ref:`PoC.arith.addw ` * PoC.arith.carrychain_inc_xilinx -* :ref:`PoC.arith.counter_bcd ` -* :ref:`PoC.arith.counter_gray ` -* :ref:`PoC.arith.div ` -* :ref:`PoC.arith.firstone ` +* :ref:`PoC.arith.counter_bcd ` +* :ref:`PoC.arith.counter_gray ` +* :ref:`PoC.arith.div ` +* :ref:`PoC.arith.firstone ` * PoC.arith.inc_ovcy_xilinx -* :ref:`PoC.arith.muls_wide ` +* :ref:`PoC.arith.muls_wide ` * PoC.arith.prefix_and_xilinx * PoC.arith.prefix_or_xilinx -* :ref:`PoC.arith.prng ` -* :ref:`PoC.arith.same ` -* :ref:`PoC.arith.sqrt ` +* :ref:`PoC.arith.prng ` +* :ref:`PoC.arith.same ` +* :ref:`PoC.arith.sqrt ` .. only:: latex diff --git a/docs/IPCores/arith/arith_addw.rst b/docs/IPCores/arith/arith_addw.rst index b6884c8fb..5bc595a43 100644 --- a/docs/IPCores/arith/arith_addw.rst +++ b/docs/IPCores/arith/arith_addw.rst @@ -1,4 +1,4 @@ -.. _IP:arith_addw: +.. _IP/arith_addw: PoC.arith.addw ############## diff --git a/docs/IPCores/arith/arith_bcdcollect.rst b/docs/IPCores/arith/arith_bcdcollect.rst index 9fcf9e1b9..df101bfc9 100644 --- a/docs/IPCores/arith/arith_bcdcollect.rst +++ b/docs/IPCores/arith/arith_bcdcollect.rst @@ -1,4 +1,4 @@ -.. _IP:arith_bcdcollect: +.. _IP/arith_bcdcollect: PoC.arith.bcdcollect #################### diff --git a/docs/IPCores/arith/arith_carrychain_inc.rst b/docs/IPCores/arith/arith_carrychain_inc.rst index aeb6eedd4..8fd23ea4d 100644 --- a/docs/IPCores/arith/arith_carrychain_inc.rst +++ b/docs/IPCores/arith/arith_carrychain_inc.rst @@ -1,4 +1,4 @@ -.. _IP:arith_carrychain_inc: +.. _IP/arith_carrychain_inc: PoC.arith.carrychain_inc ######################## diff --git a/docs/IPCores/arith/arith_convert_bin2bcd.rst b/docs/IPCores/arith/arith_convert_bin2bcd.rst index 4267b204b..7443bf360 100644 --- a/docs/IPCores/arith/arith_convert_bin2bcd.rst +++ b/docs/IPCores/arith/arith_convert_bin2bcd.rst @@ -1,4 +1,4 @@ -.. _IP:arith_convert_bin2bcd: +.. _IP/arith_convert_bin2bcd: PoC.arith.convert_bin2bcd ######################### diff --git a/docs/IPCores/arith/arith_counter_bcd.rst b/docs/IPCores/arith/arith_counter_bcd.rst index 6e683c065..9c83841de 100644 --- a/docs/IPCores/arith/arith_counter_bcd.rst +++ b/docs/IPCores/arith/arith_counter_bcd.rst @@ -1,4 +1,4 @@ -.. _IP:arith_counter_bcd: +.. _IP/arith_counter_bcd: PoC.arith.counter_bcd ##################### diff --git a/docs/IPCores/arith/arith_counter_free.rst b/docs/IPCores/arith/arith_counter_free.rst index 741f2d913..36af6d9d4 100644 --- a/docs/IPCores/arith/arith_counter_free.rst +++ b/docs/IPCores/arith/arith_counter_free.rst @@ -1,4 +1,4 @@ -.. _IP:arith_counter_free: +.. _IP/arith_counter_free: PoC.arith.counter_free ###################### diff --git a/docs/IPCores/arith/arith_counter_gray.rst b/docs/IPCores/arith/arith_counter_gray.rst index d6ee1e682..072eea5ad 100644 --- a/docs/IPCores/arith/arith_counter_gray.rst +++ b/docs/IPCores/arith/arith_counter_gray.rst @@ -1,4 +1,4 @@ -.. _IP:arith_counter_gray: +.. _IP/arith_counter_gray: PoC.arith.counter_gray ###################### diff --git a/docs/IPCores/arith/arith_counter_ring.rst b/docs/IPCores/arith/arith_counter_ring.rst index c7541bcb0..bc36071df 100644 --- a/docs/IPCores/arith/arith_counter_ring.rst +++ b/docs/IPCores/arith/arith_counter_ring.rst @@ -1,4 +1,4 @@ -.. _IP:arith_counter_ring: +.. _IP/arith_counter_ring: PoC.arith.counter_ring ###################### diff --git a/docs/IPCores/arith/arith_div.rst b/docs/IPCores/arith/arith_div.rst index 2a3ee2ad4..3d7aae38a 100644 --- a/docs/IPCores/arith/arith_div.rst +++ b/docs/IPCores/arith/arith_div.rst @@ -1,4 +1,4 @@ -.. _IP:arith_div: +.. _IP/arith_div: PoC.arith.div ############# diff --git a/docs/IPCores/arith/arith_firstone.rst b/docs/IPCores/arith/arith_firstone.rst index 10755ee9f..2db747f72 100644 --- a/docs/IPCores/arith/arith_firstone.rst +++ b/docs/IPCores/arith/arith_firstone.rst @@ -1,4 +1,4 @@ -.. _IP:arith_firstone: +.. _IP/arith_firstone: PoC.arith.firstone ################## diff --git a/docs/IPCores/arith/arith_muls_wide.rst b/docs/IPCores/arith/arith_muls_wide.rst index 68ed6a993..11d78bef8 100644 --- a/docs/IPCores/arith/arith_muls_wide.rst +++ b/docs/IPCores/arith/arith_muls_wide.rst @@ -1,4 +1,4 @@ -.. _IP:arith_muls_wide: +.. _IP/arith_muls_wide: PoC.arith.muls_wide ################### diff --git a/docs/IPCores/arith/arith_prefix_and.rst b/docs/IPCores/arith/arith_prefix_and.rst index df992f4ad..bfbb17bb5 100644 --- a/docs/IPCores/arith/arith_prefix_and.rst +++ b/docs/IPCores/arith/arith_prefix_and.rst @@ -1,4 +1,4 @@ -.. _IP:arith_prefix_and: +.. _IP/arith_prefix_and: PoC.arith.prefix_and #################### diff --git a/docs/IPCores/arith/arith_prefix_or.rst b/docs/IPCores/arith/arith_prefix_or.rst index 22ca9db23..91c4fae6d 100644 --- a/docs/IPCores/arith/arith_prefix_or.rst +++ b/docs/IPCores/arith/arith_prefix_or.rst @@ -1,4 +1,4 @@ -.. _IP:arith_prefix_or: +.. _IP/arith_prefix_or: PoC.arith.prefix_or ################### diff --git a/docs/IPCores/arith/arith_prng.rst b/docs/IPCores/arith/arith_prng.rst index 935f8b805..cd1da4e56 100644 --- a/docs/IPCores/arith/arith_prng.rst +++ b/docs/IPCores/arith/arith_prng.rst @@ -1,4 +1,4 @@ -.. _IP:arith_prng: +.. _IP/arith_prng: PoC.arith.prng ############## diff --git a/docs/IPCores/arith/arith_same.rst b/docs/IPCores/arith/arith_same.rst index 605f25df6..bc3e51df1 100644 --- a/docs/IPCores/arith/arith_same.rst +++ b/docs/IPCores/arith/arith_same.rst @@ -1,4 +1,4 @@ -.. _IP:arith_same: +.. _IP/arith_same: PoC.arith.same ############## diff --git a/docs/IPCores/arith/arith_scaler.rst b/docs/IPCores/arith/arith_scaler.rst index 6ca0174f4..535f5aad2 100644 --- a/docs/IPCores/arith/arith_scaler.rst +++ b/docs/IPCores/arith/arith_scaler.rst @@ -1,4 +1,4 @@ -.. _IP:arith_scaler: +.. _IP/arith_scaler: PoC.arith.scaler ################ diff --git a/docs/IPCores/arith/arith_shifter_barrel.rst b/docs/IPCores/arith/arith_shifter_barrel.rst index ee45718bc..27f5bae85 100644 --- a/docs/IPCores/arith/arith_shifter_barrel.rst +++ b/docs/IPCores/arith/arith_shifter_barrel.rst @@ -1,4 +1,4 @@ -.. _IP:arith_shifter_barrel: +.. _IP/arith_shifter_barrel: PoC.arith.shifter_barrel ######################## diff --git a/docs/IPCores/arith/arith_sqrt.rst b/docs/IPCores/arith/arith_sqrt.rst index f69b40d1a..a650c787d 100644 --- a/docs/IPCores/arith/arith_sqrt.rst +++ b/docs/IPCores/arith/arith_sqrt.rst @@ -1,4 +1,4 @@ -.. _IP:arith_sqrt: +.. _IP/arith_sqrt: PoC.arith.sqrt ############## diff --git a/docs/IPCores/arith/index.rst b/docs/IPCores/arith/index.rst index 11da2e3a4..7c48fa07c 100644 --- a/docs/IPCores/arith/index.rst +++ b/docs/IPCores/arith/index.rst @@ -1,4 +1,4 @@ -.. _NS:arith: +.. _NS/arith: PoC.arith ========= @@ -7,27 +7,27 @@ These are arithmetic entities.... **Package** -:ref:`PKG:arith` +:ref:`PKG/arith` **Entities** - * :ref:`IP:arith_addw` - * :ref:`IP:arith_carrychain_inc` - * :ref:`IP:arith_convert_bin2bcd` - * :ref:`IP:arith_counter_bcd` - * :ref:`IP:arith_counter_free` - * :ref:`IP:arith_counter_gray` - * :ref:`IP:arith_counter_ring` - * :ref:`IP:arith_div` - * :ref:`IP:arith_firstone` - * :ref:`IP:arith_muls_wide` - * :ref:`IP:arith_prefix_and` - * :ref:`IP:arith_prefix_or` - * :ref:`IP:arith_prng` - * :ref:`IP:arith_same` - * :ref:`IP:arith_scaler` - * :ref:`IP:arith_shifter_barrel` - * :ref:`IP:arith_sqrt` + * :ref:`IP/arith_addw` + * :ref:`IP/arith_carrychain_inc` + * :ref:`IP/arith_convert_bin2bcd` + * :ref:`IP/arith_counter_bcd` + * :ref:`IP/arith_counter_free` + * :ref:`IP/arith_counter_gray` + * :ref:`IP/arith_counter_ring` + * :ref:`IP/arith_div` + * :ref:`IP/arith_firstone` + * :ref:`IP/arith_muls_wide` + * :ref:`IP/arith_prefix_and` + * :ref:`IP/arith_prefix_or` + * :ref:`IP/arith_prng` + * :ref:`IP/arith_same` + * :ref:`IP/arith_scaler` + * :ref:`IP/arith_shifter_barrel` + * :ref:`IP/arith_sqrt` .. toctree:: diff --git a/docs/IPCores/bus/bus_Arbiter.rst b/docs/IPCores/bus/bus_Arbiter.rst index ffb9c88b5..ce545e673 100644 --- a/docs/IPCores/bus/bus_Arbiter.rst +++ b/docs/IPCores/bus/bus_Arbiter.rst @@ -1,4 +1,4 @@ -.. _IP:bus_Arbiter: +.. _IP/bus_Arbiter: PoC.bus.Arbiter ############### diff --git a/docs/IPCores/bus/index.rst b/docs/IPCores/bus/index.rst index ebda5e61f..6669071f1 100644 --- a/docs/IPCores/bus/index.rst +++ b/docs/IPCores/bus/index.rst @@ -1,4 +1,4 @@ -.. _NS:bus: +.. _NS/bus: PoC.bus ======== @@ -7,12 +7,12 @@ These are bus entities.... **Sub-namespaces** - * :ref:`NS:stream` - * :ref:`NS:wb` + * :ref:`NS/stream` + * :ref:`NS/wb` **Entities** - * :ref:`IP:bus_Arbiter` + * :ref:`IP/bus_Arbiter` .. toctree:: :hidden: diff --git a/docs/IPCores/bus/stream/index.rst b/docs/IPCores/bus/stream/index.rst index a39eaf75a..53621f51a 100644 --- a/docs/IPCores/bus/stream/index.rst +++ b/docs/IPCores/bus/stream/index.rst @@ -1,4 +1,4 @@ -.. _NS:stream: +.. _NS/stream: PoC.bus.stream ============== diff --git a/docs/IPCores/bus/stream/stream.pkg.rst b/docs/IPCores/bus/stream/stream.pkg.rst index 03161076c..dc875a127 100644 --- a/docs/IPCores/bus/stream/stream.pkg.rst +++ b/docs/IPCores/bus/stream/stream.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:stream: +.. _PKG/stream: PoC.bus.stream Package ====================== diff --git a/docs/IPCores/bus/stream/stream_DeMux.rst b/docs/IPCores/bus/stream/stream_DeMux.rst index 46a9f7470..412100b1e 100644 --- a/docs/IPCores/bus/stream/stream_DeMux.rst +++ b/docs/IPCores/bus/stream/stream_DeMux.rst @@ -1,4 +1,4 @@ -.. _IP:stream_DeMux: +.. _IP/stream_DeMux: PoC.bus.stream.DeMux #################### diff --git a/docs/IPCores/bus/stream/stream_FIFO.rst b/docs/IPCores/bus/stream/stream_FIFO.rst index 1f3040320..281afc289 100644 --- a/docs/IPCores/bus/stream/stream_FIFO.rst +++ b/docs/IPCores/bus/stream/stream_FIFO.rst @@ -1,4 +1,4 @@ -.. _IP:stream_Buffer: +.. _IP/stream_Buffer: PoC.bus.stream.Buffer ##################### diff --git a/docs/IPCores/bus/stream/stream_FrameGenerator.rst b/docs/IPCores/bus/stream/stream_FrameGenerator.rst index 9e4c36f52..030de6d77 100644 --- a/docs/IPCores/bus/stream/stream_FrameGenerator.rst +++ b/docs/IPCores/bus/stream/stream_FrameGenerator.rst @@ -1,4 +1,4 @@ -.. _IP:stream_FrameGenerator: +.. _IP/stream_FrameGenerator: PoC.bus.stream.FrameGenerator ############################# diff --git a/docs/IPCores/bus/stream/stream_Mirror.rst b/docs/IPCores/bus/stream/stream_Mirror.rst index c4796273c..8683c4602 100644 --- a/docs/IPCores/bus/stream/stream_Mirror.rst +++ b/docs/IPCores/bus/stream/stream_Mirror.rst @@ -1,4 +1,4 @@ -.. _IP:stream_Mirror: +.. _IP/stream_Mirror: PoC.bus.stream.Mirror ##################### diff --git a/docs/IPCores/bus/stream/stream_Mux.rst b/docs/IPCores/bus/stream/stream_Mux.rst index 0c08de950..824d92774 100644 --- a/docs/IPCores/bus/stream/stream_Mux.rst +++ b/docs/IPCores/bus/stream/stream_Mux.rst @@ -1,4 +1,4 @@ -.. _IP:stream_Mux: +.. _IP/stream_Mux: PoC.bus.stream.Mux ################## diff --git a/docs/IPCores/bus/stream/stream_Sink.rst b/docs/IPCores/bus/stream/stream_Sink.rst index 1066b091e..b67f481b3 100644 --- a/docs/IPCores/bus/stream/stream_Sink.rst +++ b/docs/IPCores/bus/stream/stream_Sink.rst @@ -1,4 +1,4 @@ -.. _IP:stream_Sink: +.. _IP/stream_Sink: PoC.bus.stream.Sink ################### diff --git a/docs/IPCores/bus/stream/stream_Source.rst b/docs/IPCores/bus/stream/stream_Source.rst index 1e3a5d766..723622a1e 100644 --- a/docs/IPCores/bus/stream/stream_Source.rst +++ b/docs/IPCores/bus/stream/stream_Source.rst @@ -1,4 +1,4 @@ -.. _IP:stream_Source: +.. _IP/stream_Source: PoC.bus.stream.Source ##################### diff --git a/docs/IPCores/bus/wb/index.rst b/docs/IPCores/bus/wb/index.rst index d3cf6e0d1..b4a8ec796 100644 --- a/docs/IPCores/bus/wb/index.rst +++ b/docs/IPCores/bus/wb/index.rst @@ -1,4 +1,4 @@ -.. _NS:wb: +.. _NS/wb: PoC.bus.wb ========== diff --git a/docs/IPCores/bus/wb/wb.pkg.rst b/docs/IPCores/bus/wb/wb.pkg.rst index 97492a802..cd2ee2b95 100644 --- a/docs/IPCores/bus/wb/wb.pkg.rst +++ b/docs/IPCores/bus/wb/wb.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:wb: +.. _PKG/wb: PoC.bus.wb Package ====================== diff --git a/docs/IPCores/bus/wb/wb_fifo_adapter.rst b/docs/IPCores/bus/wb/wb_fifo_adapter.rst index 52ef58e28..17b3ba42a 100644 --- a/docs/IPCores/bus/wb/wb_fifo_adapter.rst +++ b/docs/IPCores/bus/wb/wb_fifo_adapter.rst @@ -1,4 +1,4 @@ -.. _IP:wb_fifo_adapter: +.. _IP/wb_fifo_adapter: PoC.bus.wb.fifo_adapter ####################### diff --git a/docs/IPCores/bus/wb/wb_ocram.rst b/docs/IPCores/bus/wb/wb_ocram.rst index b6c3e2d86..8a03901bf 100644 --- a/docs/IPCores/bus/wb/wb_ocram.rst +++ b/docs/IPCores/bus/wb/wb_ocram.rst @@ -1,4 +1,4 @@ -.. _IP:ocram_wb: +.. _IP/ocram_wb: PoC.bus.wb.ocram ################ diff --git a/docs/IPCores/bus/wb/wb_uart_wrapper.rst b/docs/IPCores/bus/wb/wb_uart_wrapper.rst index 2036cff0c..78bdf6f69 100644 --- a/docs/IPCores/bus/wb/wb_uart_wrapper.rst +++ b/docs/IPCores/bus/wb/wb_uart_wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:uart_wb: +.. _IP/uart_wb: PoC.bus.wb.uart_wrapper ####################### diff --git a/docs/IPCores/cache/cache_cpu.rst b/docs/IPCores/cache/cache_cpu.rst index 55274fa1e..1663a2a18 100644 --- a/docs/IPCores/cache/cache_cpu.rst +++ b/docs/IPCores/cache/cache_cpu.rst @@ -1,4 +1,4 @@ -.. _IP:cache_cpu: +.. _IP/cache_cpu: PoC.cache.cpu ############# @@ -19,7 +19,7 @@ PoC.cache.cpu * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` -This unit provides a cache (:ref:`IP:cache_par2`) together +This unit provides a cache (:ref:`IP/cache_par2`) together with a cache controller which reads / writes cache lines from / to memory. The memory is accessed using a :ref:`INT:PoC.Mem` interfaces, the related ports and parameters are prefixed with ``mem_``. @@ -53,7 +53,7 @@ directly fed by the address caculator. But be aware of the high setup time of this unit and high propate time for ``cpu_got``. This unit supports only one outstanding CPU request. More outstanding -requests are provided by :ref:`IP:cache_mem`. +requests are provided by :ref:`IP/cache_mem`. Configuration @@ -167,7 +167,7 @@ cycles and acknowledged when the data has been issued to the memory. .. seealso:: - :ref:`IP:cache_mem` + :ref:`IP/cache_mem` diff --git a/docs/IPCores/cache/cache_mem.rst b/docs/IPCores/cache/cache_mem.rst index a0da1e10f..556d739c9 100644 --- a/docs/IPCores/cache/cache_mem.rst +++ b/docs/IPCores/cache/cache_mem.rst @@ -1,4 +1,4 @@ -.. _IP:cache_mem: +.. _IP/cache_mem: PoC.cache.mem ############# @@ -19,7 +19,7 @@ PoC.cache.mem * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` -This unit provides a cache (:ref:`IP:cache_par2`) together +This unit provides a cache (:ref:`IP/cache_par2`) together with a cache controller which reads / writes cache lines from / to memory. It has two :ref:`INT:PoC.Mem` interfaces: @@ -28,7 +28,7 @@ It has two :ref:`INT:PoC.Mem` interfaces: Thus, this unit can be placed into an already available memory path between the CPU and the memory (controller). If you want to plugin a cache into a -CPU pipeline, see :ref:`IP:cache_cpu`. +CPU pipeline, see :ref:`IP/cache_cpu`. Configuration @@ -77,10 +77,10 @@ If ``OUTSTANDING_REQ`` is: critical path (clock-to-output delay) for ``cpu_rdy``, the throughput is degraded to one request per 2 clock cycles at maximum. -* 2: then 2 requests are buffered by :ref:`IP:fifo_glue`. This setting has +* 2: then 2 requests are buffered by :ref:`IP/fifo_glue`. This setting has the lowest area requirements without degrading the performance. -* >2: then the requests are buffered by :ref:`IP:fifo_cc_got`. The number of +* >2: then the requests are buffered by :ref:`IP/fifo_cc_got`. The number of outstanding requests is rounded up to the next suitable value. This setting is useful in applications with out-of-order execution (of other operations). The CPU requests to the cache are always processed in-order. @@ -127,7 +127,7 @@ The interface is documented in detail :ref:`here `. .. seealso:: - :ref:`IP:cache_cpu` + :ref:`IP/cache_cpu` diff --git a/docs/IPCores/cache/cache_par.rst b/docs/IPCores/cache/cache_par.rst index 821b84f76..daa471d36 100644 --- a/docs/IPCores/cache/cache_par.rst +++ b/docs/IPCores/cache/cache_par.rst @@ -1,4 +1,4 @@ -.. _IP:cache_par: +.. _IP/cache_par: PoC.cache.par ############# diff --git a/docs/IPCores/cache/cache_par2.rst b/docs/IPCores/cache/cache_par2.rst index 1c45ad638..0bca93608 100644 --- a/docs/IPCores/cache/cache_par2.rst +++ b/docs/IPCores/cache/cache_par2.rst @@ -1,4 +1,4 @@ -.. _IP:cache_par2: +.. _IP/cache_par2: PoC.cache.par2 ############## @@ -20,7 +20,7 @@ PoC.cache.par2 * |gh-tb| :poctb:`Testbench ` Cache with parallel tag-unit and data memory. For the data memory, -:ref:`IP:ocram_sp` is used. +:ref:`IP/ocram_sp` is used. Configuration ************* diff --git a/docs/IPCores/cache/cache_replacement_policy.rst b/docs/IPCores/cache/cache_replacement_policy.rst index da989e775..36dc43c62 100644 --- a/docs/IPCores/cache/cache_replacement_policy.rst +++ b/docs/IPCores/cache/cache_replacement_policy.rst @@ -1,4 +1,4 @@ -.. _IP:cache_replacement_policy: +.. _IP/cache_replacement_policy: PoC.cache.replacement_policy ############################ diff --git a/docs/IPCores/cache/cache_tagunit_par.rst b/docs/IPCores/cache/cache_tagunit_par.rst index b0d9e6a8f..8d6470c4d 100644 --- a/docs/IPCores/cache/cache_tagunit_par.rst +++ b/docs/IPCores/cache/cache_tagunit_par.rst @@ -1,4 +1,4 @@ -.. _IP:cache_tagunit_par: +.. _IP/cache_tagunit_par: PoC.cache.tagunit_par ##################### diff --git a/docs/IPCores/cache/cache_tagunit_seq.rst b/docs/IPCores/cache/cache_tagunit_seq.rst index 3c6e0af99..de8fe6fbf 100644 --- a/docs/IPCores/cache/cache_tagunit_seq.rst +++ b/docs/IPCores/cache/cache_tagunit_seq.rst @@ -1,4 +1,4 @@ -.. _IP:cache_tagunit_seq: +.. _IP/cache_tagunit_seq: PoC.cache.tagunit_seq ##################### diff --git a/docs/IPCores/cache/index.rst b/docs/IPCores/cache/index.rst index ae107330d..a8fad4124 100644 --- a/docs/IPCores/cache/index.rst +++ b/docs/IPCores/cache/index.rst @@ -1,4 +1,4 @@ -.. _NS:cache: +.. _NS/cache: PoC.cache ========= @@ -7,24 +7,24 @@ The namespace `PoC.cache` offers different cache implementations. **Entities** - * :ref:`IP:cache_cpu`: Cache with cache controller to be used within a CPU. + * :ref:`IP/cache_cpu`: Cache with cache controller to be used within a CPU. - * :ref:`IP:cache_mem`: Cache with :ref:`INT:PoC.Mem` interface on the "CPU" side. + * :ref:`IP/cache_mem`: Cache with :ref:`INT:PoC.Mem` interface on the "CPU" side. - * :ref:`IP:cache_par`: Cache with parallel tag-unit and + * :ref:`IP/cache_par`: Cache with parallel tag-unit and data memory (using infered memory). - * :ref:`IP:cache_par2`: Cache with parallel tag-unit and - data memory (using :ref:`IP:ocram_sp`). + * :ref:`IP/cache_par2`: Cache with parallel tag-unit and + data memory (using :ref:`IP/ocram_sp`). - * :ref:`IP:cache_tagunit_par`: Tag-Unit with + * :ref:`IP/cache_tagunit_par`: Tag-Unit with parallel tag comparison. Configurable as: * Full-associative cache, * Direct-mapped cache, or * Set-associative cache. - * :ref:`IP:cache_tagunit_seq`: Tag-Unit with + * :ref:`IP/cache_tagunit_seq`: Tag-Unit with sequential tag comparison. Configurable as: * Full-associative cache, diff --git a/docs/IPCores/comm/comm.pkg.rst b/docs/IPCores/comm/comm.pkg.rst index 23080d59c..2d1134ccb 100644 --- a/docs/IPCores/comm/comm.pkg.rst +++ b/docs/IPCores/comm/comm.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:comm: +.. _PKG/comm: PoC.comm Package ================ diff --git a/docs/IPCores/comm/comm_crc.rst b/docs/IPCores/comm/comm_crc.rst index 29607682b..4977da3ff 100644 --- a/docs/IPCores/comm/comm_crc.rst +++ b/docs/IPCores/comm/comm_crc.rst @@ -1,4 +1,4 @@ -.. _IP:comm_crc: +.. _IP/comm_crc: PoC.comm.crc ############ diff --git a/docs/IPCores/comm/comm_scramble.rst b/docs/IPCores/comm/comm_scramble.rst index 031e60f7d..111afa020 100644 --- a/docs/IPCores/comm/comm_scramble.rst +++ b/docs/IPCores/comm/comm_scramble.rst @@ -1,4 +1,4 @@ -.. _IP:comm_scramble: +.. _IP/comm_scramble: PoC.comm.scramble ################# diff --git a/docs/IPCores/comm/index.rst b/docs/IPCores/comm/index.rst index 12fb724fc..49d75e876 100644 --- a/docs/IPCores/comm/index.rst +++ b/docs/IPCores/comm/index.rst @@ -1,4 +1,4 @@ -.. _NS:comm: +.. _NS/comm: PoC.comm ======== diff --git a/docs/IPCores/comm/remote/index.rst b/docs/IPCores/comm/remote/index.rst index 5528a3c4e..bce0b74ca 100644 --- a/docs/IPCores/comm/remote/index.rst +++ b/docs/IPCores/comm/remote/index.rst @@ -1,4 +1,4 @@ -.. _NS:comm:remote: +.. _NS/comm/remote: PoC.comm.remote =============== diff --git a/docs/IPCores/comm/remote/remote_terminal_control.rst b/docs/IPCores/comm/remote/remote_terminal_control.rst index 102ad4dd8..d989a67cf 100644 --- a/docs/IPCores/comm/remote/remote_terminal_control.rst +++ b/docs/IPCores/comm/remote/remote_terminal_control.rst @@ -1,4 +1,4 @@ -.. _IP:remote_terminal_control: +.. _IP/remote_terminal_control: PoC.comm.remote.terminal_control ################################ diff --git a/docs/IPCores/dstruct/dstruct_deque.rst b/docs/IPCores/dstruct/dstruct_deque.rst index 97f5e4d16..a916fb9a0 100644 --- a/docs/IPCores/dstruct/dstruct_deque.rst +++ b/docs/IPCores/dstruct/dstruct_deque.rst @@ -1,4 +1,4 @@ -.. _IP:dstruct_deque: +.. _IP/dstruct_deque: PoC.dstruct.deque ################# diff --git a/docs/IPCores/dstruct/dstruct_stack.rst b/docs/IPCores/dstruct/dstruct_stack.rst index 8410285ba..3ae960627 100644 --- a/docs/IPCores/dstruct/dstruct_stack.rst +++ b/docs/IPCores/dstruct/dstruct_stack.rst @@ -1,4 +1,4 @@ -.. _IP:dstruct_stack: +.. _IP/dstruct_stack: PoC.dstruct.stack ################# diff --git a/docs/IPCores/dstruct/index.rst b/docs/IPCores/dstruct/index.rst index 091326375..c858dbb1e 100644 --- a/docs/IPCores/dstruct/index.rst +++ b/docs/IPCores/dstruct/index.rst @@ -1,4 +1,4 @@ -.. _NS:dstruct: +.. _NS/dstruct: PoC.dstruct =========== @@ -7,12 +7,12 @@ The namespace `PoC.dstruct` offers different data structure implementations. **Package** -The package :ref:`NS:dstruct` holds all component declarations for this namespace. +The package :ref:`NS/dstruct` holds all component declarations for this namespace. **Entities** - * :ref:`IP:dstruct_deque` implements a deque (two-sided FIFO). - * :ref:`IP:dstruct_stack` implements a regular stack. + * :ref:`IP/dstruct_deque` implements a deque (two-sided FIFO). + * :ref:`IP/dstruct_stack` implements a regular stack. .. toctree:: :hidden: diff --git a/docs/IPCores/fifo/fifo.pkg.rst b/docs/IPCores/fifo/fifo.pkg.rst index 7a11a06c0..ecb872b7f 100644 --- a/docs/IPCores/fifo/fifo.pkg.rst +++ b/docs/IPCores/fifo/fifo.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:fifo: +.. _PKG/fifo: PoC.fifo Package ================ diff --git a/docs/IPCores/fifo/fifo_cc_got.rst b/docs/IPCores/fifo/fifo_cc_got.rst index 2e32c3632..faa9fdd96 100644 --- a/docs/IPCores/fifo/fifo_cc_got.rst +++ b/docs/IPCores/fifo/fifo_cc_got.rst @@ -1,4 +1,4 @@ -.. _IP:fifo_cc_got: +.. _IP/fifo_cc_got: PoC.fifo.cc_got ############### @@ -79,11 +79,11 @@ comparator (subtractor) in their path. .. seealso:: - :ref:`IP:fifo_dc_got` + :ref:`IP/fifo_dc_got` For a FIFO with dependent clocks. - :ref:`IP:fifo_ic_got` + :ref:`IP/fifo_ic_got` For a FIFO with independent clocks (cross-clock FIFO). - :ref:`IP:fifo_glue` + :ref:`IP/fifo_glue` For a minimal FIFO / pipeline decoupling. diff --git a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst index 804202777..005d743b0 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst @@ -1,4 +1,4 @@ -.. _IP:fifo_cc_got_tempgot: +.. _IP/fifo_cc_got_tempgot: PoC.fifo.cc_got_tempgot ####################### diff --git a/docs/IPCores/fifo/fifo_cc_got_tempput.rst b/docs/IPCores/fifo/fifo_cc_got_tempput.rst index 7035089d5..e2c082151 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempput.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempput.rst @@ -1,4 +1,4 @@ -.. _IP:fifo_cc_got_tempput: +.. _IP/fifo_cc_got_tempput: PoC.fifo.cc_got_tempput ####################### diff --git a/docs/IPCores/fifo/fifo_dc_got_sm.rst b/docs/IPCores/fifo/fifo_dc_got_sm.rst index 810f11c0c..10626bda9 100644 --- a/docs/IPCores/fifo/fifo_dc_got_sm.rst +++ b/docs/IPCores/fifo/fifo_dc_got_sm.rst @@ -1,4 +1,4 @@ -.. _IP:fifo_dc_got_sm: +.. _IP/fifo_dc_got_sm: PoC.fifo.dc_got_sm ################## diff --git a/docs/IPCores/fifo/fifo_ic_assembly.rst b/docs/IPCores/fifo/fifo_ic_assembly.rst index 66feb06ad..ca2f34238 100644 --- a/docs/IPCores/fifo/fifo_ic_assembly.rst +++ b/docs/IPCores/fifo/fifo_ic_assembly.rst @@ -1,4 +1,4 @@ -.. _IP:fifo_ic_assembly: +.. _IP/fifo_ic_assembly: PoC.fifo.ic_assembly #################### diff --git a/docs/IPCores/fifo/fifo_ic_got.rst b/docs/IPCores/fifo/fifo_ic_got.rst index 3a6e5dbc0..499ee6aec 100644 --- a/docs/IPCores/fifo/fifo_ic_got.rst +++ b/docs/IPCores/fifo/fifo_ic_got.rst @@ -1,4 +1,4 @@ -.. _IP:fifo_ic_got: +.. _IP/fifo_ic_got: PoC.fifo.ic_got ############### diff --git a/docs/IPCores/fifo/fifo_shift.rst b/docs/IPCores/fifo/fifo_shift.rst index 25f3162ba..9d5010f38 100644 --- a/docs/IPCores/fifo/fifo_shift.rst +++ b/docs/IPCores/fifo/fifo_shift.rst @@ -1,4 +1,4 @@ -.. _IP:fifo_shift: +.. _IP/fifo_shift: PoC.fifo.shift ############## diff --git a/docs/IPCores/fifo/fifo_stage.rst b/docs/IPCores/fifo/fifo_stage.rst index 9734977c5..80b3c1e22 100644 --- a/docs/IPCores/fifo/fifo_stage.rst +++ b/docs/IPCores/fifo/fifo_stage.rst @@ -1,4 +1,4 @@ -.. _IP:fifo_glue: +.. _IP/fifo_glue: PoC.fifo.glue ############# diff --git a/docs/IPCores/fifo/index.rst b/docs/IPCores/fifo/index.rst index 27ee6f03f..08248ab8d 100644 --- a/docs/IPCores/fifo/index.rst +++ b/docs/IPCores/fifo/index.rst @@ -1,4 +1,4 @@ -.. _NS:fifo: +.. _NS/fifo: PoC.fifo ======== @@ -7,7 +7,7 @@ The namespace `PoC.fifo` offers different :abbr:`FIFO (first-in, first-out)` imp **Package** -The package :ref:`NS:fifo` holds all component declarations for this namespace. +The package :ref:`NS/fifo` holds all component declarations for this namespace. **Entities** @@ -22,19 +22,19 @@ the current fill-state. The prefixes `cc_` (common clock), `dc_` (dependent clock) and `ic_` (independent clock) refer to the write- and read-side clock relationship. - * :ref:`IP:fifo_cc_got` implements a regular FIFO (one common clock, + * :ref:`IP/fifo_cc_got` implements a regular FIFO (one common clock, got-interface) - * :ref:`IP:fifo_cc_got_tempgot` implements a regular FIFO (one common clock, + * :ref:`IP/fifo_cc_got_tempgot` implements a regular FIFO (one common clock, got-interface), extended by a transactional `tempgot`-interface (read-side). - * :ref:`IP:fifo_cc_got_tempput` implements a regular FIFO (one common clock, + * :ref:`IP/fifo_cc_got_tempput` implements a regular FIFO (one common clock, got-interface), extended by a transactional `tempput`-interface (write-side). - * :ref:`IP:fifo_dc_got` implements a cross-clock FIFO (two related clocks, + * :ref:`IP/fifo_dc_got` implements a cross-clock FIFO (two related clocks, got-interface) - * :ref:`IP:fifo_ic_got` implements a cross-clock FIFO (two independent clocks, + * :ref:`IP/fifo_ic_got` implements a cross-clock FIFO (two independent clocks, got-interface) - * :ref:`IP:fifo_glue` implements a two-stage FIFO (one common clock, + * :ref:`IP/fifo_glue` implements a two-stage FIFO (one common clock, got-interface) - * :ref:`IP:fifo_shift` implements a regular FIFO (one common clock, + * :ref:`IP/fifo_shift` implements a regular FIFO (one common clock, got-interface, optimized for FPGAs with shifter primitives) .. toctree:: diff --git a/docs/IPCores/io/ddrio/ddrio.pkg.rst b/docs/IPCores/io/ddrio/ddrio.pkg.rst index ed54e5f3d..255361223 100644 --- a/docs/IPCores/io/ddrio/ddrio.pkg.rst +++ b/docs/IPCores/io/ddrio/ddrio.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:ddrio: +.. _PKG/ddrio: PoC.io.ddrio Package ==================== diff --git a/docs/IPCores/io/ddrio/ddrio_in.rst b/docs/IPCores/io/ddrio/ddrio_in.rst index 207118148..8f2478ae3 100644 --- a/docs/IPCores/io/ddrio/ddrio_in.rst +++ b/docs/IPCores/io/ddrio/ddrio_in.rst @@ -1,4 +1,4 @@ -.. _IP:ddrio_in: +.. _IP/ddrio_in: PoC.io.ddrio.in ############### diff --git a/docs/IPCores/io/ddrio/ddrio_inout.rst b/docs/IPCores/io/ddrio/ddrio_inout.rst index 56dfd31c1..65923d209 100644 --- a/docs/IPCores/io/ddrio/ddrio_inout.rst +++ b/docs/IPCores/io/ddrio/ddrio_inout.rst @@ -1,4 +1,4 @@ -.. _IP:ddrio_inout: +.. _IP/ddrio_inout: PoC.io.ddrio.inout ################## diff --git a/docs/IPCores/io/ddrio/ddrio_out.rst b/docs/IPCores/io/ddrio/ddrio_out.rst index 569ad84bc..f6e0b49e0 100644 --- a/docs/IPCores/io/ddrio/ddrio_out.rst +++ b/docs/IPCores/io/ddrio/ddrio_out.rst @@ -1,4 +1,4 @@ -.. _IP:ddrio_out: +.. _IP/ddrio_out: PoC.io.ddrio.out ################ diff --git a/docs/IPCores/io/ddrio/index.rst b/docs/IPCores/io/ddrio/index.rst index 0960d6073..79e1c84c7 100644 --- a/docs/IPCores/io/ddrio/index.rst +++ b/docs/IPCores/io/ddrio/index.rst @@ -1,4 +1,4 @@ -.. _NS:ddrio: +.. _NS/ddrio: PoC.io.ddrio ============ @@ -7,9 +7,9 @@ These are :abbr:`DDR-I/O (Double Data Rate - Input/Output)` entities.... **Entities** - * :ref:`IP:ddrio_in` - * :ref:`IP:ddrio_inout` - * :ref:`IP:ddrio_out` + * :ref:`IP/ddrio_in` + * :ref:`IP/ddrio_inout` + * :ref:`IP/ddrio_out` .. toctree:: diff --git a/docs/IPCores/io/iic/iic.pkg.rst b/docs/IPCores/io/iic/iic.pkg.rst index 32081b555..8bb9b6ecf 100644 --- a/docs/IPCores/io/iic/iic.pkg.rst +++ b/docs/IPCores/io/iic/iic.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:iic: +.. _PKG/iic: PoC.io.iic Package ================== diff --git a/docs/IPCores/io/iic/iic_BusController.rst b/docs/IPCores/io/iic/iic_BusController.rst index 170035e79..f4bbf319c 100644 --- a/docs/IPCores/io/iic/iic_BusController.rst +++ b/docs/IPCores/io/iic/iic_BusController.rst @@ -1,4 +1,4 @@ -.. _IP:iic_BusController: +.. _IP/iic_BusController: PoC.io.iic.BusController ######################## diff --git a/docs/IPCores/io/iic/iic_Controller.rst b/docs/IPCores/io/iic/iic_Controller.rst index cd76f285b..5a7b78cd4 100644 --- a/docs/IPCores/io/iic/iic_Controller.rst +++ b/docs/IPCores/io/iic/iic_Controller.rst @@ -1,4 +1,4 @@ -.. _IP:iic_Controller: +.. _IP/iic_Controller: PoC.io.iic.Controller ##################### diff --git a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst index 0504ccc81..ccff649ce 100644 --- a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst +++ b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst @@ -1,4 +1,4 @@ -.. _IP:IICController_SFF8431: +.. _IP/IICController_SFF8431: PoC.io.iic.Controller_SFF8431 ############################# diff --git a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst index cc16c51c7..efb8ea654 100644 --- a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst +++ b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst @@ -1,4 +1,4 @@ -.. _IP:iic_Switch_PCA9548A: +.. _IP/iic_Switch_PCA9548A: PoC.io.iic.Switch_PCA9548A ########################## diff --git a/docs/IPCores/io/iic/index.rst b/docs/IPCores/io/iic/index.rst index d0c7e20bd..d2c3f3775 100644 --- a/docs/IPCores/io/iic/index.rst +++ b/docs/IPCores/io/iic/index.rst @@ -1,4 +1,4 @@ -.. _NS:iic: +.. _NS/iic: PoC.io.iic ========== diff --git a/docs/IPCores/io/index.rst b/docs/IPCores/io/index.rst index 3723afcf8..351bf4a84 100644 --- a/docs/IPCores/io/index.rst +++ b/docs/IPCores/io/index.rst @@ -1,4 +1,4 @@ -.. _NS:io: +.. _NS/io: PoC.io ====== diff --git a/docs/IPCores/io/io.pkg.rst b/docs/IPCores/io/io.pkg.rst index 890688da9..a28733b7b 100644 --- a/docs/IPCores/io/io.pkg.rst +++ b/docs/IPCores/io/io.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:io: +.. _PKG/io: PoC.io Package ============== diff --git a/docs/IPCores/io/io_7SegmentMux_BCD.rst b/docs/IPCores/io/io_7SegmentMux_BCD.rst index fd9937241..8885df5a4 100644 --- a/docs/IPCores/io/io_7SegmentMux_BCD.rst +++ b/docs/IPCores/io/io_7SegmentMux_BCD.rst @@ -1,4 +1,4 @@ -.. _IP:io_7SegmentMux_BCD: +.. _IP/io_7SegmentMux_BCD: PoC.io.7SegmentMux_BCD ###################### diff --git a/docs/IPCores/io/io_7SegmentMux_HEX.rst b/docs/IPCores/io/io_7SegmentMux_HEX.rst index 10c2e5506..14801d529 100644 --- a/docs/IPCores/io/io_7SegmentMux_HEX.rst +++ b/docs/IPCores/io/io_7SegmentMux_HEX.rst @@ -1,4 +1,4 @@ -.. _IP:io_7SegmentMux_HEX: +.. _IP/io_7SegmentMux_HEX: PoC.io.7SegmentMux_HEX ###################### diff --git a/docs/IPCores/io/io_Debounce.rst b/docs/IPCores/io/io_Debounce.rst index 5258f5b55..a7c1d68f3 100644 --- a/docs/IPCores/io/io_Debounce.rst +++ b/docs/IPCores/io/io_Debounce.rst @@ -1,4 +1,4 @@ -.. _IP:io_Debounce: +.. _IP/io_Debounce: PoC.io.Debounce ############### diff --git a/docs/IPCores/io/io_FanControl.rst b/docs/IPCores/io/io_FanControl.rst index 46f5f999e..459f57563 100644 --- a/docs/IPCores/io/io_FanControl.rst +++ b/docs/IPCores/io/io_FanControl.rst @@ -1,4 +1,4 @@ -.. _IP:io_FanControl: +.. _IP/io_FanControl: PoC.io.FanControl ################# diff --git a/docs/IPCores/io/io_FrequencyCounter.rst b/docs/IPCores/io/io_FrequencyCounter.rst index 9156b66d1..68403b108 100644 --- a/docs/IPCores/io/io_FrequencyCounter.rst +++ b/docs/IPCores/io/io_FrequencyCounter.rst @@ -1,4 +1,4 @@ -.. _IP:io_FrequencyCounter: +.. _IP/io_FrequencyCounter: PoC.io.FrequencyCounter ####################### diff --git a/docs/IPCores/io/io_GlitchFilter.rst b/docs/IPCores/io/io_GlitchFilter.rst index 1c7f16254..fb53a7f17 100644 --- a/docs/IPCores/io/io_GlitchFilter.rst +++ b/docs/IPCores/io/io_GlitchFilter.rst @@ -1,4 +1,4 @@ -.. _IP:io_GlitchFilter: +.. _IP/io_GlitchFilter: PoC.io.GlitchFilter ################### diff --git a/docs/IPCores/io/io_KeyPadScanner.rst b/docs/IPCores/io/io_KeyPadScanner.rst index 1e2345815..e4287c011 100644 --- a/docs/IPCores/io/io_KeyPadScanner.rst +++ b/docs/IPCores/io/io_KeyPadScanner.rst @@ -1,4 +1,4 @@ -.. _IP:io_KeyPadScanner: +.. _IP/io_KeyPadScanner: PoC.io.KeyPadScanner #################### diff --git a/docs/IPCores/io/io_PulseWidthModulation.rst b/docs/IPCores/io/io_PulseWidthModulation.rst index d2311ed21..5aca56715 100644 --- a/docs/IPCores/io/io_PulseWidthModulation.rst +++ b/docs/IPCores/io/io_PulseWidthModulation.rst @@ -1,4 +1,4 @@ -.. _IP:io_PulseWidthModulation: +.. _IP/io_PulseWidthModulation: PoC.io.PulseWidthModulation ########################### diff --git a/docs/IPCores/io/io_TimingCounter.rst b/docs/IPCores/io/io_TimingCounter.rst index 2e6b9489b..ff02013bf 100644 --- a/docs/IPCores/io/io_TimingCounter.rst +++ b/docs/IPCores/io/io_TimingCounter.rst @@ -1,4 +1,4 @@ -.. _IP:io_TimingCounter: +.. _IP/io_TimingCounter: PoC.io.TimingCounter #################### diff --git a/docs/IPCores/io/jtag/index.rst b/docs/IPCores/io/jtag/index.rst index c5faf6d43..4c0e11043 100644 --- a/docs/IPCores/io/jtag/index.rst +++ b/docs/IPCores/io/jtag/index.rst @@ -1,4 +1,4 @@ -.. _NS:jtag: +.. _NS/jtag: PoC.io.jtag =========== diff --git a/docs/IPCores/io/lcd/index.rst b/docs/IPCores/io/lcd/index.rst index 6c4ac1334..24b62336c 100644 --- a/docs/IPCores/io/lcd/index.rst +++ b/docs/IPCores/io/lcd/index.rst @@ -1,4 +1,4 @@ -.. _NS:lcd: +.. _NS/lcd: PoC.io.lcd ========== diff --git a/docs/IPCores/io/lcd/lcd.pkg.rst b/docs/IPCores/io/lcd/lcd.pkg.rst index c0b93e55d..b171e296f 100644 --- a/docs/IPCores/io/lcd/lcd.pkg.rst +++ b/docs/IPCores/io/lcd/lcd.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:lcd: +.. _PKG/lcd: PoC.io.lcd Package ================== diff --git a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst index 4803a1560..9fefc5735 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst @@ -1,4 +1,4 @@ -.. _IP:lcd_LCDBuffer: +.. _IP/lcd_LCDBuffer: PoC.io.lcd.LCDBuffer #################### diff --git a/docs/IPCores/io/lcd/lcd_LCDBusController.rst b/docs/IPCores/io/lcd/lcd_LCDBusController.rst index 45d3a0ef3..b97c804e1 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBusController.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBusController.rst @@ -1,4 +1,4 @@ -.. _IP:lcd_LCDBusController: +.. _IP/lcd_LCDBusController: PoC.io.lcd.LCDBusController ########################### diff --git a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst index 9bc9f717a..d0b941e02 100644 --- a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst +++ b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst @@ -1,4 +1,4 @@ -.. _IP:lcd_LCDController_KS0066U: +.. _IP/lcd_LCDController_KS0066U: PoC.io.lcd.LCDController_KS0066U ################################ diff --git a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst index 576e9c3d2..c6c30ba83 100644 --- a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst @@ -1,4 +1,4 @@ -.. _IP:lcd_LCDSynchronizer: +.. _IP/lcd_LCDSynchronizer: PoC.io.lcd.LCDSynchronizer ########################## diff --git a/docs/IPCores/io/lcd/lcd_dotmatrix.rst b/docs/IPCores/io/lcd/lcd_dotmatrix.rst index 300ca5ffb..0c830d2ef 100644 --- a/docs/IPCores/io/lcd/lcd_dotmatrix.rst +++ b/docs/IPCores/io/lcd/lcd_dotmatrix.rst @@ -1,4 +1,4 @@ -.. _IP:lcd_dotmatrix: +.. _IP/lcd_dotmatrix: PoC.io.lcd.dotmatrix #################### diff --git a/docs/IPCores/io/mdio/index.rst b/docs/IPCores/io/mdio/index.rst index 24bb8c4ac..3c1b0b607 100644 --- a/docs/IPCores/io/mdio/index.rst +++ b/docs/IPCores/io/mdio/index.rst @@ -1,4 +1,4 @@ -.. _NS:mdio: +.. _NS/mdio: PoC.io.mdio =========== diff --git a/docs/IPCores/io/mdio/mdio_Controller.rst b/docs/IPCores/io/mdio/mdio_Controller.rst index c3b4c6544..1046036b1 100644 --- a/docs/IPCores/io/mdio/mdio_Controller.rst +++ b/docs/IPCores/io/mdio/mdio_Controller.rst @@ -1,4 +1,4 @@ -.. _IP:mdio_Controller: +.. _IP/mdio_Controller: PoC.io.mdio.Controller ###################### diff --git a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst index fea3d8dd4..d84bdc5d8 100644 --- a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst +++ b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst @@ -1,4 +1,4 @@ -.. _IP:mdio_IIC_Adapter: +.. _IP/mdio_IIC_Adapter: PoC.io.mdio.IIC_Adapter ####################### diff --git a/docs/IPCores/io/ow/index.rst b/docs/IPCores/io/ow/index.rst index 21e868f02..695edf21d 100644 --- a/docs/IPCores/io/ow/index.rst +++ b/docs/IPCores/io/ow/index.rst @@ -1,4 +1,4 @@ -.. _NS:ow: +.. _NS/ow: PoC.io.ow ========= diff --git a/docs/IPCores/io/pio/index.rst b/docs/IPCores/io/pio/index.rst index b66aca7cb..245010755 100644 --- a/docs/IPCores/io/pio/index.rst +++ b/docs/IPCores/io/pio/index.rst @@ -1,4 +1,4 @@ -.. _NS:pio: +.. _NS/pio: PoC.io.pio ========== diff --git a/docs/IPCores/io/pio/pio_fifo_in.rst b/docs/IPCores/io/pio/pio_fifo_in.rst index 3c1564a0f..32c77dd34 100644 --- a/docs/IPCores/io/pio/pio_fifo_in.rst +++ b/docs/IPCores/io/pio/pio_fifo_in.rst @@ -1,4 +1,4 @@ -.. _IP:pio_fifo_in: +.. _IP/pio_fifo_in: PoC.io.pio.fifo_in ################## diff --git a/docs/IPCores/io/pio/pio_fifo_out.rst b/docs/IPCores/io/pio/pio_fifo_out.rst index 7d7f7aa2d..e91c8a4e7 100644 --- a/docs/IPCores/io/pio/pio_fifo_out.rst +++ b/docs/IPCores/io/pio/pio_fifo_out.rst @@ -1,4 +1,4 @@ -.. _IP:pio_fifo_out: +.. _IP/pio_fifo_out: PoC.io.pio.fifo_out ################### diff --git a/docs/IPCores/io/pio/pio_in.rst b/docs/IPCores/io/pio/pio_in.rst index 89365672d..514ca3624 100644 --- a/docs/IPCores/io/pio/pio_in.rst +++ b/docs/IPCores/io/pio/pio_in.rst @@ -1,4 +1,4 @@ -.. _IP:pio_in: +.. _IP/pio_in: PoC.io.pio.in ############# diff --git a/docs/IPCores/io/pio/pio_out.rst b/docs/IPCores/io/pio/pio_out.rst index b9a8c6526..60e769d1b 100644 --- a/docs/IPCores/io/pio/pio_out.rst +++ b/docs/IPCores/io/pio/pio_out.rst @@ -1,4 +1,4 @@ -.. _IP:pio_out: +.. _IP/pio_out: PoC.io.pio.out ############## diff --git a/docs/IPCores/io/pmod/index.rst b/docs/IPCores/io/pmod/index.rst index 16a0ce73f..ca089a7b5 100644 --- a/docs/IPCores/io/pmod/index.rst +++ b/docs/IPCores/io/pmod/index.rst @@ -1,4 +1,4 @@ -.. _NS:pmod: +.. _NS/pmod: PoC.io.pmod =========== @@ -7,9 +7,9 @@ These are Pmod entities.... **Entities** - * :ref:`IP:pmod_KYPD` - * :ref:`IP:pmod_SSD` - * :ref:`IP:pmod_USBUART` + * :ref:`IP/pmod_KYPD` + * :ref:`IP/pmod_SSD` + * :ref:`IP/pmod_USBUART` .. toctree:: diff --git a/docs/IPCores/io/pmod/pmod.pkg.rst b/docs/IPCores/io/pmod/pmod.pkg.rst index c14884f63..bc99e8503 100644 --- a/docs/IPCores/io/pmod/pmod.pkg.rst +++ b/docs/IPCores/io/pmod/pmod.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:pmod: +.. _PKG/pmod: PoC.io.pmod Package =================== diff --git a/docs/IPCores/io/pmod/pmod_KYPD.rst b/docs/IPCores/io/pmod/pmod_KYPD.rst index 338a9e651..b53ace4df 100644 --- a/docs/IPCores/io/pmod/pmod_KYPD.rst +++ b/docs/IPCores/io/pmod/pmod_KYPD.rst @@ -1,4 +1,4 @@ -.. _IP:pmod_KYPD: +.. _IP/pmod_KYPD: PoC.io.pmod.KYPD ################ diff --git a/docs/IPCores/io/pmod/pmod_SSD.rst b/docs/IPCores/io/pmod/pmod_SSD.rst index f59e2f3d5..b3a5d211a 100644 --- a/docs/IPCores/io/pmod/pmod_SSD.rst +++ b/docs/IPCores/io/pmod/pmod_SSD.rst @@ -1,4 +1,4 @@ -.. _IP:pmod_SSD: +.. _IP/pmod_SSD: PoC.io.pmod.SSD ############### diff --git a/docs/IPCores/io/pmod/pmod_USBUART.rst b/docs/IPCores/io/pmod/pmod_USBUART.rst index db37da9d3..0f329ab24 100644 --- a/docs/IPCores/io/pmod/pmod_USBUART.rst +++ b/docs/IPCores/io/pmod/pmod_USBUART.rst @@ -1,4 +1,4 @@ -.. _IP:pmod_USBUART: +.. _IP/pmod_USBUART: PoC.io.pmod.USBUART ################### diff --git a/docs/IPCores/io/ps2/index.rst b/docs/IPCores/io/ps2/index.rst index 9cd1c3a2d..1697fe262 100644 --- a/docs/IPCores/io/ps2/index.rst +++ b/docs/IPCores/io/ps2/index.rst @@ -1,4 +1,4 @@ -.. _NS:ps2: +.. _NS/ps2: PoC.io.ps2 ========== diff --git a/docs/IPCores/io/uart/index.rst b/docs/IPCores/io/uart/index.rst index 45ed08f6f..f60888c91 100644 --- a/docs/IPCores/io/uart/index.rst +++ b/docs/IPCores/io/uart/index.rst @@ -1,4 +1,4 @@ -.. _NS:uart: +.. _NS/uart: PoC.io.uart =========== @@ -7,10 +7,10 @@ These are :abbr:`UART (Universal Asynchronous Receiver Transmitter)` entities... **Entities** - * :ref:`IP:uart_bclk` - * :ref:`IP:uart_rx` - * :ref:`IP:uart_tx` - * :ref:`IP:uart_fifo` + * :ref:`IP/uart_bclk` + * :ref:`IP/uart_rx` + * :ref:`IP/uart_tx` + * :ref:`IP/uart_fifo` .. toctree:: diff --git a/docs/IPCores/io/uart/uart.pkg.rst b/docs/IPCores/io/uart/uart.pkg.rst index 37d06f2a2..bc0e71e80 100644 --- a/docs/IPCores/io/uart/uart.pkg.rst +++ b/docs/IPCores/io/uart/uart.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:uart: +.. _PKG/uart: PoC.io.uart Package =================== diff --git a/docs/IPCores/io/uart/uart_bclk.rst b/docs/IPCores/io/uart/uart_bclk.rst index c4e848c36..404f1ef0f 100644 --- a/docs/IPCores/io/uart/uart_bclk.rst +++ b/docs/IPCores/io/uart/uart_bclk.rst @@ -1,4 +1,4 @@ -.. _IP:uart_bclk: +.. _IP/uart_bclk: PoC.io.uart.bclk ################ diff --git a/docs/IPCores/io/uart/uart_fifo.rst b/docs/IPCores/io/uart/uart_fifo.rst index 06d56bf33..0532934c8 100644 --- a/docs/IPCores/io/uart/uart_fifo.rst +++ b/docs/IPCores/io/uart/uart_fifo.rst @@ -1,4 +1,4 @@ -.. _IP:uart_fifo: +.. _IP/uart_fifo: PoC.io.uart.fifo ################ diff --git a/docs/IPCores/io/uart/uart_ft245.rst b/docs/IPCores/io/uart/uart_ft245.rst index 7ec4cb905..f61e3f853 100644 --- a/docs/IPCores/io/uart/uart_ft245.rst +++ b/docs/IPCores/io/uart/uart_ft245.rst @@ -1,4 +1,4 @@ -.. _IP:uart_ft245: +.. _IP/uart_ft245: PoC.io.uart.ft245 ################# diff --git a/docs/IPCores/io/uart/uart_rx.rst b/docs/IPCores/io/uart/uart_rx.rst index 90fba9c08..aef156fce 100644 --- a/docs/IPCores/io/uart/uart_rx.rst +++ b/docs/IPCores/io/uart/uart_rx.rst @@ -1,4 +1,4 @@ -.. _IP:uart_rx: +.. _IP/uart_rx: PoC.io.uart.rx ############## diff --git a/docs/IPCores/io/uart/uart_tx.rst b/docs/IPCores/io/uart/uart_tx.rst index 5ec05da99..84795387f 100644 --- a/docs/IPCores/io/uart/uart_tx.rst +++ b/docs/IPCores/io/uart/uart_tx.rst @@ -1,4 +1,4 @@ -.. _IP:uart_tx: +.. _IP/uart_tx: PoC.io.uart.tx ############## diff --git a/docs/IPCores/io/vga/index.rst b/docs/IPCores/io/vga/index.rst index 49c6c4215..77d611cda 100644 --- a/docs/IPCores/io/vga/index.rst +++ b/docs/IPCores/io/vga/index.rst @@ -1,4 +1,4 @@ -.. _NS:vga: +.. _NS/vga: PoC.io.vga ========== diff --git a/docs/IPCores/io/vga/vga.pkg.rst b/docs/IPCores/io/vga/vga.pkg.rst index d90f20412..ff3ff7e00 100644 --- a/docs/IPCores/io/vga/vga.pkg.rst +++ b/docs/IPCores/io/vga/vga.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:vga: +.. _PKG/vga: PoC.io.vga Package ================== diff --git a/docs/IPCores/io/vga/vga_phy.rst b/docs/IPCores/io/vga/vga_phy.rst index 1e08bc4d1..3aa8ef36b 100644 --- a/docs/IPCores/io/vga/vga_phy.rst +++ b/docs/IPCores/io/vga/vga_phy.rst @@ -1,4 +1,4 @@ -.. _IP:vga_phy: +.. _IP/vga_phy: PoC.io.vga.phy ############## diff --git a/docs/IPCores/io/vga/vga_phy_ch7301c.rst b/docs/IPCores/io/vga/vga_phy_ch7301c.rst index fc82c28fd..f585cd474 100644 --- a/docs/IPCores/io/vga/vga_phy_ch7301c.rst +++ b/docs/IPCores/io/vga/vga_phy_ch7301c.rst @@ -1,4 +1,4 @@ -.. _IP:vga_phy_ch7301c: +.. _IP/vga_phy_ch7301c: PoC.io.vga.phy_ch7301c ###################### diff --git a/docs/IPCores/io/vga/vga_timing.rst b/docs/IPCores/io/vga/vga_timing.rst index 4cff541fa..5694a0a52 100644 --- a/docs/IPCores/io/vga/vga_timing.rst +++ b/docs/IPCores/io/vga/vga_timing.rst @@ -1,4 +1,4 @@ -.. _IP:vga_timing: +.. _IP/vga_timing: PoC.io.vga.timing ################# diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst index 62ba441c8..985d66cd7 100644 --- a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst +++ b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -1,4 +1,4 @@ -.. _IP:ddr2_mem2mig_adapter_Spartan6: +.. _IP/ddr2_mem2mig_adapter_Spartan6: PoC.mem.ddr2.mem2mig_adapter_Spartan6 ##################################### diff --git a/docs/IPCores/mem/ddr2/index.rst b/docs/IPCores/mem/ddr2/index.rst index 1f98bb542..3f2fdbac7 100644 --- a/docs/IPCores/mem/ddr2/index.rst +++ b/docs/IPCores/mem/ddr2/index.rst @@ -1,4 +1,4 @@ -.. _NS:ddr2: +.. _NS/ddr2: PoC.mem.ddr2 ============ @@ -12,7 +12,7 @@ provide the same simple memory interface to the user application. **Entities** - * :ref:`IP:ddr2_mem2mig_adapter_Spartan6` - Adapter for the Xilinx MIG core + * :ref:`IP/ddr2_mem2mig_adapter_Spartan6` - Adapter for the Xilinx MIG core for Spartan-6 FPGAs diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst index f02332daf..a73799ca5 100644 --- a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst +++ b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -1,4 +1,4 @@ -.. _IP:ddr3_mem2mig_adapter_Series7: +.. _IP/ddr3_mem2mig_adapter_Series7: PoC.mem.ddr3.mem2mig_adapter_Series7 #################################### diff --git a/docs/IPCores/mem/ddr3/index.rst b/docs/IPCores/mem/ddr3/index.rst index f6232571b..a7b8c82cb 100644 --- a/docs/IPCores/mem/ddr3/index.rst +++ b/docs/IPCores/mem/ddr3/index.rst @@ -1,4 +1,4 @@ -.. _NS:ddr3: +.. _NS/ddr3: PoC.mem.ddr3 ============ @@ -12,7 +12,7 @@ provide the same simple memory interface to the user application. **Entities** - * :ref:`IP:ddr3_mem2mig_adapter_Series7` - Adapter for the Xilinx MIG core + * :ref:`IP/ddr3_mem2mig_adapter_Series7` - Adapter for the Xilinx MIG core for 7-Series FPGAs diff --git a/docs/IPCores/mem/index.rst b/docs/IPCores/mem/index.rst index 05a166f83..d6e93a07f 100644 --- a/docs/IPCores/mem/index.rst +++ b/docs/IPCores/mem/index.rst @@ -1,4 +1,4 @@ -.. _NS:mem: +.. _NS/mem: PoC.mem ======== @@ -9,16 +9,16 @@ implementations. **Sub-Namespaces** - * :ref:`NS:ddr2` - DDR2 memory controllers - * :ref:`NS:ddr3` - DDR3 memory controllers - * :ref:`NS:lut` - Lookup-Table (LUT) implementations - * :ref:`NS:ocram` - On-Chip RAM abstraction layer - * :ref:`NS:ocrom` - On-Chip ROM abstraction layer - * :ref:`NS:sdram` - SDRAM controllers + * :ref:`NS/ddr2` - DDR2 memory controllers + * :ref:`NS/ddr3` - DDR3 memory controllers + * :ref:`NS/lut` - Lookup-Table (LUT) implementations + * :ref:`NS/ocram` - On-Chip RAM abstraction layer + * :ref:`NS/ocrom` - On-Chip ROM abstraction layer + * :ref:`NS/sdram` - SDRAM controllers **Package** -:ref:`PoC.mem ` +:ref:`PoC.mem ` .. toctree:: diff --git a/docs/IPCores/mem/lut/index.rst b/docs/IPCores/mem/lut/index.rst index c714731c3..1a984953b 100644 --- a/docs/IPCores/mem/lut/index.rst +++ b/docs/IPCores/mem/lut/index.rst @@ -1,4 +1,4 @@ -.. _NS:lut: +.. _NS/lut: PoC.mem.lut =========== @@ -7,7 +7,7 @@ The namespace ``PoC.mem.lut`` offers different lookup-tables (LUTs). **Entities** - * :ref:`IP:lut_Sine` - a Sine implementation with 1,2 or 4 quadrants. + * :ref:`IP/lut_Sine` - a Sine implementation with 1,2 or 4 quadrants. .. toctree:: diff --git a/docs/IPCores/mem/lut/lut_Sine.rst b/docs/IPCores/mem/lut/lut_Sine.rst index 20d219367..7b33bd0e1 100644 --- a/docs/IPCores/mem/lut/lut_Sine.rst +++ b/docs/IPCores/mem/lut/lut_Sine.rst @@ -1,4 +1,4 @@ -.. _IP:lut_Sine: +.. _IP/lut_Sine: PoC.mem.lut.Sine ################ diff --git a/docs/IPCores/mem/mem.pkg.rst b/docs/IPCores/mem/mem.pkg.rst index 0d2a45db9..8abcee2b0 100644 --- a/docs/IPCores/mem/mem.pkg.rst +++ b/docs/IPCores/mem/mem.pkg.rst @@ -9,13 +9,13 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:mem: +.. _PKG/mem: PoC.mem Package =============== This package holds all component declarations, types and functions of the -:ref:`PoC.mem ` namespace. +:ref:`PoC.mem ` namespace. It provides the following enumerations: diff --git a/docs/IPCores/mem/ocram/index.rst b/docs/IPCores/mem/ocram/index.rst index c415e4385..36cce0e6c 100644 --- a/docs/IPCores/mem/ocram/index.rst +++ b/docs/IPCores/mem/ocram/index.rst @@ -1,4 +1,4 @@ -.. _NS:ocram: +.. _NS/ocram: PoC.mem.ocram ============= @@ -17,21 +17,21 @@ The package PoC.mem.ocram holds all component declarations for this namespace. **Entities** - * :ref:`IP:ocram_sp` - An on-chip RAM with a single port interface. - * :ref:`IP:ocram_sdp` - An on-chip RAM with a simple dual-port interface. - * :ref:`IP:ocram_sdp_wf` - An on-chip RAM with a simple dual-port + * :ref:`IP/ocram_sp` - An on-chip RAM with a single port interface. + * :ref:`IP/ocram_sdp` - An on-chip RAM with a simple dual-port interface. + * :ref:`IP/ocram_sdp_wf` - An on-chip RAM with a simple dual-port interface and write-first behavior. - * :ref:`IP:ocram_tdp` - An on-chip RAM with a true dual-port interface. - * :ref:`IP:ocram_tdp_wf` - An on-chip RAM with a true dual-port + * :ref:`IP/ocram_tdp` - An on-chip RAM with a true dual-port interface. + * :ref:`IP/ocram_tdp_wf` - An on-chip RAM with a true dual-port interface and write-first behavior. **Simulation Helper** - * :ref:`IP:ocram_tdp_sim` - Simulation model of on-chip RAM with a true dual port interface. + * :ref:`IP/ocram_tdp_sim` - Simulation model of on-chip RAM with a true dual port interface. **Deprecated Entities** - * :ref:`IP:ocram_esdp` - An on-chip RAM with an extended simple dual port interface. + * :ref:`IP/ocram_esdp` - An on-chip RAM with an extended simple dual port interface. .. toctree:: diff --git a/docs/IPCores/mem/ocram/ocram.pkg.rst b/docs/IPCores/mem/ocram/ocram.pkg.rst index cd8bcb34b..c919a5ea1 100644 --- a/docs/IPCores/mem/ocram/ocram.pkg.rst +++ b/docs/IPCores/mem/ocram/ocram.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:ocram: +.. _PKG/ocram: PoC.mem.ocram Package ===================== diff --git a/docs/IPCores/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst index e34c7bb52..1105fecef 100644 --- a/docs/IPCores/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -1,4 +1,4 @@ -.. _IP:ocram_esdp: +.. _IP/ocram_esdp: PoC.mem.ocram.esdp ################## @@ -26,7 +26,7 @@ Inferring / instantiating enhanced simple dual-port memory, with: .. deprecated:: 1.1 - **Please use** :ref:`IP:ocram_tdp` **for new designs. + **Please use** :ref:`IP/ocram_tdp` **for new designs. This component has been provided because older FPGA compilers where not able to infer true dual-port memory from an RTL description.** @@ -68,7 +68,7 @@ Mixed-Port Read-During-Write rising-edge of the write clock (``clk1``) and (in the worst case) extends until the next rising-edge of the write clock. -For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +For simulation, always our dedicated simulation model :ref:`IP/ocram_tdp_sim` is used. diff --git a/docs/IPCores/mem/ocram/ocram_sdp.rst b/docs/IPCores/mem/ocram/ocram_sdp.rst index a55989ebd..7c029c6f7 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp.rst @@ -1,4 +1,4 @@ -.. _IP:ocram_sdp: +.. _IP/ocram_sdp: PoC.mem.ocram.sdp ################# @@ -38,7 +38,7 @@ Mixed-Port Read-During-Write rising-edge of the write clock and (in the worst case) extends until the next rising-edge of the write clock. -For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +For simulation, always our dedicated simulation model :ref:`IP/ocram_tdp_sim` is used. diff --git a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst index 66561a396..3dd2a098a 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst @@ -1,4 +1,4 @@ -.. _IP:ocram_sdp_wf: +.. _IP/ocram_sdp_wf: PoC.mem.ocram.sdp_wf #################### diff --git a/docs/IPCores/mem/ocram/ocram_sp.rst b/docs/IPCores/mem/ocram/ocram_sp.rst index 8318520e9..07aa9bf3c 100644 --- a/docs/IPCores/mem/ocram/ocram_sp.rst +++ b/docs/IPCores/mem/ocram/ocram_sp.rst @@ -1,4 +1,4 @@ -.. _IP:ocram_sp: +.. _IP/ocram_sp: PoC.mem.ocram.sp ################ diff --git a/docs/IPCores/mem/ocram/ocram_tdp.rst b/docs/IPCores/mem/ocram/ocram_tdp.rst index 91bee648d..6764b0b52 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp.rst @@ -1,4 +1,4 @@ -.. _IP:ocram_tdp: +.. _IP/ocram_tdp: PoC.mem.ocram.tdp ################# @@ -55,7 +55,7 @@ Mixed-Port Read-During-Write rising-edge of the write clock and (in the worst case) extends until the next rising-edge of that write clock. -For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +For simulation, always our dedicated simulation model :ref:`IP/ocram_tdp_sim` is used. diff --git a/docs/IPCores/mem/ocram/ocram_tdp_sim.rst b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst index 050c01542..388e7d4eb 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp_sim.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst @@ -1,4 +1,4 @@ -.. _IP:ocram_tdp_sim: +.. _IP/ocram_tdp_sim: PoC.mem.ocram.tdp_sim ##################### diff --git a/docs/IPCores/mem/ocram/ocram_tdp_wf.rst b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst index 59f51b2ad..a7e1c1605 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp_wf.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst @@ -1,4 +1,4 @@ -.. _IP:ocram_tdp_wf: +.. _IP/ocram_tdp_wf: PoC.mem.ocram.tdp_wf #################### @@ -56,7 +56,7 @@ Mixed-Port Read-During-Write If a write is issued on both ports to the same address, then the output of this unit and the content of the addressed memory cell are undefined. -For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +For simulation, always our dedicated simulation model :ref:`IP/ocram_tdp_sim` is used. diff --git a/docs/IPCores/mem/ocrom/index.rst b/docs/IPCores/mem/ocrom/index.rst index f9453dae4..a34083624 100644 --- a/docs/IPCores/mem/ocrom/index.rst +++ b/docs/IPCores/mem/ocrom/index.rst @@ -1,4 +1,4 @@ -.. _NS:ocrom: +.. _NS/ocrom: PoC.mem.ocrom ============= @@ -17,8 +17,8 @@ The package PoC.mem.ocrom holds all component declarations for this namespace. **Entities** - - :ref:`ocrom_sp ` is a on-chip RAM with a single port interface. - - :ref:`ocrom_dp ` is a on-chip RAM with a dual port interface. + - :ref:`ocrom_sp ` is a on-chip RAM with a single port interface. + - :ref:`ocrom_dp ` is a on-chip RAM with a dual port interface. .. toctree:: diff --git a/docs/IPCores/mem/ocrom/ocrom.pkg.rst b/docs/IPCores/mem/ocrom/ocrom.pkg.rst index a1d7c0514..374c95b65 100644 --- a/docs/IPCores/mem/ocrom/ocrom.pkg.rst +++ b/docs/IPCores/mem/ocrom/ocrom.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:ocrom: +.. _PKG/ocrom: PoC.mem.ocrom Package ===================== diff --git a/docs/IPCores/mem/ocrom/ocrom_dp.rst b/docs/IPCores/mem/ocrom/ocrom_dp.rst index 53f67d78d..1d0c98b8d 100644 --- a/docs/IPCores/mem/ocrom/ocrom_dp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_dp.rst @@ -1,4 +1,4 @@ -.. _IP:ocrom_dp: +.. _IP/ocrom_dp: PoC.mem.ocrom.dp ################ diff --git a/docs/IPCores/mem/ocrom/ocrom_sp.rst b/docs/IPCores/mem/ocrom/ocrom_sp.rst index ae2e4ed3b..528bd18e6 100644 --- a/docs/IPCores/mem/ocrom/ocrom_sp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_sp.rst @@ -1,4 +1,4 @@ -.. _IP:ocrom_sp: +.. _IP/ocrom_sp: PoC.mem.ocrom.sp ################ diff --git a/docs/IPCores/mem/sdram/index.rst b/docs/IPCores/mem/sdram/index.rst index fafe582b8..f59a9321f 100644 --- a/docs/IPCores/mem/sdram/index.rst +++ b/docs/IPCores/mem/sdram/index.rst @@ -1,4 +1,4 @@ -.. _NS:sdram: +.. _NS/sdram: PoC.mem.sdram ============= @@ -11,23 +11,23 @@ module required by the FPGA board. .. rubric:: SDRAM Controller for the Altera DE0 Board -The module :ref:`sdram_ctrl_de0 ` combines the finite state machine -:ref:`sdram_ctrl_fsm ` and the DE0 specific physical layer -:ref:`sdram_ctrl_phy_de0 `. It has been tested with the +The module :ref:`sdram_ctrl_de0 ` combines the finite state machine +:ref:`sdram_ctrl_fsm ` and the DE0 specific physical layer +:ref:`sdram_ctrl_phy_de0 `. It has been tested with the IS42S16400F SDR memory at a frequency of 133 MHz. A usage example is given in PoC-Examples_. .. rubric:: SDRAM Controller for the Xilinx Spartan-3E Starter Kit (S3ESK) -The module :ref:`sdram_ctrl_s3esk ` combines the finite state -machine :ref:`sdram_ctrl_fsm ` and the S3ESK specific physical layer -:ref:`sdram_ctrl_phy_s3esk `. It has been tested with the +The module :ref:`sdram_ctrl_s3esk ` combines the finite state +machine :ref:`sdram_ctrl_fsm ` and the S3ESK specific physical layer +:ref:`sdram_ctrl_phy_s3esk `. It has been tested with the MT46V32M16-6T DDR memory at a frequency of 100 MHz (DDR-200). A usage example is given in PoC-Examples_. .. Note:: - See also :ref:`NS:mig` for board specific memory controller implementations + See also :ref:`NS/mig` for board specific memory controller implementations created by Xilinx's Memory Interface Generator (MIG). diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst index 854dbf14f..cde6c9ead 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst @@ -1,4 +1,4 @@ -.. _IP:sdram_ctrl_de0: +.. _IP/sdram_ctrl_de0: PoC.mem.sdram.ctrl_de0 ###################### @@ -47,7 +47,7 @@ Command, address and write data is sampled with ``clk``. Read data is also aligned with ``clk``. For description on ``clkout`` see -:ref:`sdram_ctrl_phy_de0 `. +:ref:`sdram_ctrl_phy_de0 `. Synchronous resets are used. diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst index 4641c2ebf..10049a6ae 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst @@ -1,4 +1,4 @@ -.. _IP:sdram_ctrl_fsm: +.. _IP/sdram_ctrl_fsm: PoC.mem.sdram.ctrl_fsm ###################### diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst index 8029a2d4c..a3acdab8b 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst @@ -1,4 +1,4 @@ -.. _IP:sdram_ctrl_phy_de0: +.. _IP/sdram_ctrl_phy_de0: PoC.mem.sdram.ctrl_phy_de0 ########################## @@ -19,7 +19,7 @@ PoC.mem.sdram.ctrl_phy_de0 * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` -Physical layer used by module :ref:`sdram_ctrl_de0 `. +Physical layer used by module :ref:`sdram_ctrl_de0 `. Instantiates input and output buffer components and adjusts the timing for the Altera DE0 board. diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst index 111958c11..aa28e6a82 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -1,4 +1,4 @@ -.. _IP:sdram_ctrl_phy_s3esk: +.. _IP/sdram_ctrl_phy_s3esk: PoC.mem.sdram.ctrl_phy_s3esk ############################ @@ -19,7 +19,7 @@ PoC.mem.sdram.ctrl_phy_s3esk * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` -Physical layer used by module :ref:`sdram_ctrl_s3esk `. +Physical layer used by module :ref:`sdram_ctrl_s3esk `. Instantiates input and output buffer components and adjusts the timing for the Spartan-3E Starter Kit Board. diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst index c4f927a23..01a374d16 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst @@ -1,4 +1,4 @@ -.. _IP:sdram_ctrl_s3esk: +.. _IP/sdram_ctrl_s3esk: PoC.mem.sdram.ctrl_s3esk ######################## diff --git a/docs/IPCores/misc/filter/filter_and.rst b/docs/IPCores/misc/filter/filter_and.rst index 3118b285c..b880c5242 100644 --- a/docs/IPCores/misc/filter/filter_and.rst +++ b/docs/IPCores/misc/filter/filter_and.rst @@ -1,4 +1,4 @@ -.. _IP:filter_and: +.. _IP/filter_and: PoC.misc.filter.and ################### diff --git a/docs/IPCores/misc/filter/filter_mean.rst b/docs/IPCores/misc/filter/filter_mean.rst index b1d4b66aa..42213f9ee 100644 --- a/docs/IPCores/misc/filter/filter_mean.rst +++ b/docs/IPCores/misc/filter/filter_mean.rst @@ -1,4 +1,4 @@ -.. _IP:filter_mean: +.. _IP/filter_mean: PoC.misc.filter.mean #################### diff --git a/docs/IPCores/misc/filter/filter_or.rst b/docs/IPCores/misc/filter/filter_or.rst index 6d3151eb8..2a6cbce9c 100644 --- a/docs/IPCores/misc/filter/filter_or.rst +++ b/docs/IPCores/misc/filter/filter_or.rst @@ -1,4 +1,4 @@ -.. _IP:filter_or: +.. _IP/filter_or: PoC.misc.filter.or ################## diff --git a/docs/IPCores/misc/filter/index.rst b/docs/IPCores/misc/filter/index.rst index a6bc70d6e..83cabd449 100644 --- a/docs/IPCores/misc/filter/index.rst +++ b/docs/IPCores/misc/filter/index.rst @@ -1,4 +1,4 @@ -.. _NS:filter: +.. _NS/filter: PoC.misc.filter =============== @@ -7,9 +7,9 @@ These are filter entities.... **Entities** - * :ref:`IP:filter_and` - * :ref:`IP:filter_mean` - * :ref:`IP:filter_or` + * :ref:`IP/filter_and` + * :ref:`IP/filter_mean` + * :ref:`IP/filter_or` .. toctree:: :hidden: diff --git a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst index 72eb096f8..1b7351dd7 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst @@ -1,4 +1,4 @@ -.. _IP:gearbox_down_cc: +.. _IP/gearbox_down_cc: PoC.misc.gearbox.down_cc ######################## diff --git a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst index 1470f504b..ed1929929 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst @@ -1,4 +1,4 @@ -.. _IP:gearbox_down_dc: +.. _IP/gearbox_down_dc: PoC.misc.gearbox.down_dc ######################## diff --git a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst index c76107e08..086b29adc 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst @@ -1,4 +1,4 @@ -.. _IP:gearbox_up_cc: +.. _IP/gearbox_up_cc: PoC.misc.gearbox.up_cc ###################### diff --git a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst index 2df5fef67..32f62a770 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst @@ -1,4 +1,4 @@ -.. _IP:gearbox_up_dc: +.. _IP/gearbox_up_dc: PoC.misc.gearbox.up_dc ###################### diff --git a/docs/IPCores/misc/gearbox/index.rst b/docs/IPCores/misc/gearbox/index.rst index b66ca2fe7..dceef97e6 100644 --- a/docs/IPCores/misc/gearbox/index.rst +++ b/docs/IPCores/misc/gearbox/index.rst @@ -1,4 +1,4 @@ -.. _NS:gearbox: +.. _NS/gearbox: PoC.misc.gearbox ================ @@ -7,10 +7,10 @@ These are gearbox entities.... **Entities** - * :ref:`IP:gearbox_down_cc` - * :ref:`IP:gearbox_down_dc` - * :ref:`IP:gearbox_up_cc` - * :ref:`IP:gearbox_up_dc` + * :ref:`IP/gearbox_down_cc` + * :ref:`IP/gearbox_down_dc` + * :ref:`IP/gearbox_up_cc` + * :ref:`IP/gearbox_up_dc` .. toctree:: :hidden: diff --git a/docs/IPCores/misc/index.rst b/docs/IPCores/misc/index.rst index d89205153..720e715cb 100644 --- a/docs/IPCores/misc/index.rst +++ b/docs/IPCores/misc/index.rst @@ -1,4 +1,4 @@ -.. _NS:misc: +.. _NS/misc: PoC.misc ======== @@ -7,23 +7,23 @@ The namespace ``PoC.misc`` offers different yet uncathegorized entities. **Sub-Namespaces** - * :ref:`NS:filter` contains 1-bit filter algorithms. - * :ref:`NS:stat` contains statistic modules. - * :ref:`NS:sync` offers clock-domain-crossing (CDC) modules. + * :ref:`NS/filter` contains 1-bit filter algorithms. + * :ref:`NS/stat` contains statistic modules. + * :ref:`NS/sync` offers clock-domain-crossing (CDC) modules. **Package** -The package :ref:`PoC.misc ` holds all component declarations for this namespace. +The package :ref:`PoC.misc ` holds all component declarations for this namespace. **Entities** - * :ref:`IP:misc_Delay` - * :ref:`IP:misc_FrequencyMeasurement` - * :ref:`IP:misc_PulseTrain` - * :ref:`IP:misc_Sequencer` - * :ref:`IP:misc_StrobeGenerator` - * :ref:`IP:misc_StrobeLimiter` - * :ref:`IP:misc_WordAligner` + * :ref:`IP/misc_Delay` + * :ref:`IP/misc_FrequencyMeasurement` + * :ref:`IP/misc_PulseTrain` + * :ref:`IP/misc_Sequencer` + * :ref:`IP/misc_StrobeGenerator` + * :ref:`IP/misc_StrobeLimiter` + * :ref:`IP/misc_WordAligner` .. toctree:: :hidden: diff --git a/docs/IPCores/misc/misc.pkg.rst b/docs/IPCores/misc/misc.pkg.rst index 77f5f7f55..0970eb13d 100644 --- a/docs/IPCores/misc/misc.pkg.rst +++ b/docs/IPCores/misc/misc.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:misc: +.. _PKG/misc: PoC.misc Package ================ diff --git a/docs/IPCores/misc/misc_BitwidthConverter.rst b/docs/IPCores/misc/misc_BitwidthConverter.rst index 77a1d6b99..0130973bc 100644 --- a/docs/IPCores/misc/misc_BitwidthConverter.rst +++ b/docs/IPCores/misc/misc_BitwidthConverter.rst @@ -1,4 +1,4 @@ -.. _IP:misc_BitwidthConverter: +.. _IP/misc_BitwidthConverter: PoC.misc.BitwidthConverter ########################## diff --git a/docs/IPCores/misc/misc_ByteAligner.rst b/docs/IPCores/misc/misc_ByteAligner.rst index 3352d216d..11434d66f 100644 --- a/docs/IPCores/misc/misc_ByteAligner.rst +++ b/docs/IPCores/misc/misc_ByteAligner.rst @@ -1,4 +1,4 @@ -.. _IP:misc_ByteAligner: +.. _IP/misc_ByteAligner: PoC.misc.ByteAligner #################### diff --git a/docs/IPCores/misc/misc_Delay.rst b/docs/IPCores/misc/misc_Delay.rst index f4fd8571a..2b1468908 100644 --- a/docs/IPCores/misc/misc_Delay.rst +++ b/docs/IPCores/misc/misc_Delay.rst @@ -1,4 +1,4 @@ -.. _IP:misc_Delay: +.. _IP/misc_Delay: PoC.misc.Delay ############## diff --git a/docs/IPCores/misc/misc_FrequencyMeasurement.rst b/docs/IPCores/misc/misc_FrequencyMeasurement.rst index abf4290a2..857373da9 100644 --- a/docs/IPCores/misc/misc_FrequencyMeasurement.rst +++ b/docs/IPCores/misc/misc_FrequencyMeasurement.rst @@ -1,4 +1,4 @@ -.. _IP:misc_FrequencyMeasurement: +.. _IP/misc_FrequencyMeasurement: PoC.misc.FrequencyMeasurement ############################# diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst index e5186ad5e..cb3c98812 100644 --- a/docs/IPCores/misc/misc_PulseTrain.rst +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -1,4 +1,4 @@ -.. _IP:misc_PulseTrain: +.. _IP/misc_PulseTrain: PoC.misc.PulseTrain ################### diff --git a/docs/IPCores/misc/misc_Sequencer.rst b/docs/IPCores/misc/misc_Sequencer.rst index 907e0535f..871dc4fb6 100644 --- a/docs/IPCores/misc/misc_Sequencer.rst +++ b/docs/IPCores/misc/misc_Sequencer.rst @@ -1,4 +1,4 @@ -.. _IP:misc_Sequencer: +.. _IP/misc_Sequencer: PoC.misc.Sequencer ################## diff --git a/docs/IPCores/misc/misc_StrobeGenerator.rst b/docs/IPCores/misc/misc_StrobeGenerator.rst index c7f802403..54a2fa38a 100644 --- a/docs/IPCores/misc/misc_StrobeGenerator.rst +++ b/docs/IPCores/misc/misc_StrobeGenerator.rst @@ -1,4 +1,4 @@ -.. _IP:misc_StrobeGenerator: +.. _IP/misc_StrobeGenerator: PoC.misc.StrobeGenerator ######################## diff --git a/docs/IPCores/misc/misc_StrobeLimiter.rst b/docs/IPCores/misc/misc_StrobeLimiter.rst index d5fe5d231..e21f3bd56 100644 --- a/docs/IPCores/misc/misc_StrobeLimiter.rst +++ b/docs/IPCores/misc/misc_StrobeLimiter.rst @@ -1,4 +1,4 @@ -.. _IP:misc_StrobeLimiter: +.. _IP/misc_StrobeLimiter: PoC.misc.StrobeLimiter ###################### diff --git a/docs/IPCores/misc/misc_WordAligner.rst b/docs/IPCores/misc/misc_WordAligner.rst index 4cb45c14f..1935ba6fd 100644 --- a/docs/IPCores/misc/misc_WordAligner.rst +++ b/docs/IPCores/misc/misc_WordAligner.rst @@ -1,4 +1,4 @@ -.. _IP:misc_WordAligner: +.. _IP/misc_WordAligner: WordAligner ########### diff --git a/docs/IPCores/misc/misc_bit_lz.rst b/docs/IPCores/misc/misc_bit_lz.rst index 61db582f7..9c854faa2 100644 --- a/docs/IPCores/misc/misc_bit_lz.rst +++ b/docs/IPCores/misc/misc_bit_lz.rst @@ -1,4 +1,4 @@ -.. _IP:misc_bit_lz: +.. _IP/misc_bit_lz: PoC.misc.bit_lz ############### diff --git a/docs/IPCores/misc/stat/index.rst b/docs/IPCores/misc/stat/index.rst index 72d742100..6988a8c01 100644 --- a/docs/IPCores/misc/stat/index.rst +++ b/docs/IPCores/misc/stat/index.rst @@ -1,4 +1,4 @@ -.. _NS:stat: +.. _NS/stat: PoC.misc.stat ============= @@ -7,10 +7,10 @@ These are stat entities.... **Entities** - * :ref:`IP:stat_Average` - * :ref:`IP:stat_Histogram` - * :ref:`IP:stat_Maximum` - * :ref:`IP:stat_Minimum` + * :ref:`IP/stat_Average` + * :ref:`IP/stat_Histogram` + * :ref:`IP/stat_Maximum` + * :ref:`IP/stat_Minimum` .. toctree:: diff --git a/docs/IPCores/misc/stat/stat_Average.rst b/docs/IPCores/misc/stat/stat_Average.rst index 163675348..bc17f5d12 100644 --- a/docs/IPCores/misc/stat/stat_Average.rst +++ b/docs/IPCores/misc/stat/stat_Average.rst @@ -1,4 +1,4 @@ -.. _IP:stat_Average: +.. _IP/stat_Average: PoC.misc.stat.Average ##################### diff --git a/docs/IPCores/misc/stat/stat_Histogram.rst b/docs/IPCores/misc/stat/stat_Histogram.rst index 55c90d0e9..5d1534613 100644 --- a/docs/IPCores/misc/stat/stat_Histogram.rst +++ b/docs/IPCores/misc/stat/stat_Histogram.rst @@ -1,4 +1,4 @@ -.. _IP:stat_Histogram: +.. _IP/stat_Histogram: PoC.misc.stat.Histogram ####################### diff --git a/docs/IPCores/misc/stat/stat_Maximum.rst b/docs/IPCores/misc/stat/stat_Maximum.rst index 555e7f26c..8b2b123a4 100644 --- a/docs/IPCores/misc/stat/stat_Maximum.rst +++ b/docs/IPCores/misc/stat/stat_Maximum.rst @@ -1,4 +1,4 @@ -.. _IP:stat_Maximum: +.. _IP/stat_Maximum: PoC.misc.stat.Maximum ##################### diff --git a/docs/IPCores/misc/stat/stat_Minimum.rst b/docs/IPCores/misc/stat/stat_Minimum.rst index b47d71a96..a3cdf81c3 100644 --- a/docs/IPCores/misc/stat/stat_Minimum.rst +++ b/docs/IPCores/misc/stat/stat_Minimum.rst @@ -1,4 +1,4 @@ -.. _IP:stat_Minimum: +.. _IP/stat_Minimum: PoC.misc.stat.Minimum ##################### diff --git a/docs/IPCores/misc/sync/index.rst b/docs/IPCores/misc/sync/index.rst index 06b7e8ff5..31901945e 100644 --- a/docs/IPCores/misc/sync/index.rst +++ b/docs/IPCores/misc/sync/index.rst @@ -1,11 +1,11 @@ -.. _NS:sync: +.. _NS/sync: PoC.misc.sync ============= The namespace ``PoC.misc.sync`` offers different clock-domain-crossing (CDC) synchronizer circuits. All synchronizers are based on the basic 2 flip-flop -synchonizer called :ref:`sync_Bits `. PoC has two +synchonizer called :ref:`sync_Bits `. PoC has two platform specific implementations for Altera and Xilinx, which are choosen, if the appropriate ``MY_DEVICE`` constant is configured in ``my_config.vhdl``. @@ -14,25 +14,25 @@ if the appropriate ``MY_DEVICE`` constant is configured in ``my_config.vhdl``. +----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ | Behavior | Flag [#f1]_ | Strobe [#f2]_ | Continuous Data | Reset [#f4]_ | Pulse [#f3]_ | +==========+=====================================+=======================================+====================+===================================+===================================+ -| 1 Bit | :ref:`sync_Bits ` | :ref:`sync_Strobe ` | fifo_ic_got [#f5]_ | :ref:`sync_Reset ` | :ref:`sync_Pulse ` | +| 1 Bit | :ref:`sync_Bits ` | :ref:`sync_Strobe ` | fifo_ic_got [#f5]_ | :ref:`sync_Reset ` | :ref:`sync_Pulse ` | +----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ -| n Bit | :ref:`sync_Vector ` | :ref:`sync_Command ` | fifo_ic_got [#f5]_ | | | +| n Bit | :ref:`sync_Vector ` | :ref:`sync_Command ` | fifo_ic_got [#f5]_ | | | +----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ .. rubric:: Basic 2 Flip-Flop Synchronizer -The basic 2 flip-flop synchronizer is called :ref:`sync_Bits `. It's +The basic 2 flip-flop synchronizer is called :ref:`sync_Bits `. It's possible to configure the bit count of indivital bits. If a vector shall be synchronized, use one of the special synchronizers like `sync_Vector`. The vendor specific implementations are named ``sync_Bits_Altera`` and ``sync_Bits_Xilinx`` respectivily. -A second variant of the 2-FF synchronizer is called :ref:`sync_Reset `. +A second variant of the 2-FF synchronizer is called :ref:`sync_Reset `. It's for ``Reset``-signals, implementing asynchronous assertion and synchronous deassertion. The vendor specific implementations are named ``sync_Reset_Altera`` and ``sync_Reset_Xilinx`` respectivily. -A third variant of a 2-FF synchronizer is called :ref:`sync_Pulse `. +A third variant of a 2-FF synchronizer is called :ref:`sync_Pulse `. It's for very short ``Pulsed``-signals. It uses an addition asynchronous capture FF to latch the very short pulse. The vendor specific implementations are named ``sync_Pulse_Altera`` and ``sync_Pulse_Xilinx`` respectivily. @@ -41,15 +41,15 @@ very short pulse. The vendor specific implementations are named ``sync_Pulse_Alt Based on the 2-FF synchronizer, several "high-level" synchronizers are build. -* :ref:`sync_Strobe ` synchronizer ``strobe``-signals +* :ref:`sync_Strobe ` synchronizer ``strobe``-signals across clock-domain-boundaries. A busy signal indicates the synchronization status and can be used as a internal gate-signal to disallow new incoming strobes. A ``strobe``-signal is only for one clock period active. -* :ref:`sync_Command ` like ``sync_Strobe``, it synchronizes +* :ref:`sync_Command ` like ``sync_Strobe``, it synchronizes a one clock period active signal across the clock-domain-boundary, but the input has multiple bits. After the multi bit strobe (Command) was transfered, the output goes to its idle value. -* :ref:`sync_Vector ` synchronizes a complete vector +* :ref:`sync_Vector ` synchronizes a complete vector across the clock-domain-boundary. A changed detection on the input vector causes a register to latch the current state. The changed event is transfered to the new clock-domain and triggers a register to store the latched content, @@ -57,7 +57,7 @@ Based on the 2-FF synchronizer, several "high-level" synchronizers are build. .. seealso:: - :ref:`IP:fifo_ic_got` + :ref:`IP/fifo_ic_got` For a cross-clock capable FIFO. .. rubric:: Footnotes diff --git a/docs/IPCores/misc/sync/sync.pkg.rst b/docs/IPCores/misc/sync/sync.pkg.rst index 87a92d03d..aed687edd 100644 --- a/docs/IPCores/misc/sync/sync.pkg.rst +++ b/docs/IPCores/misc/sync/sync.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:sync: +.. _PKG/sync: PoC.misc.sync Package ===================== diff --git a/docs/IPCores/misc/sync/sync_Bits.rst b/docs/IPCores/misc/sync/sync_Bits.rst index 9247b6d48..5b7f1bd67 100644 --- a/docs/IPCores/misc/sync/sync_Bits.rst +++ b/docs/IPCores/misc/sync/sync_Bits.rst @@ -1,4 +1,4 @@ -.. _IP:sync_Bits: +.. _IP/sync_Bits: PoC.misc.sync.Bits ################## diff --git a/docs/IPCores/misc/sync/sync_Command.rst b/docs/IPCores/misc/sync/sync_Command.rst index 47d983d6a..74fd2dba7 100644 --- a/docs/IPCores/misc/sync/sync_Command.rst +++ b/docs/IPCores/misc/sync/sync_Command.rst @@ -1,4 +1,4 @@ -.. _IP:sync_Command: +.. _IP/sync_Command: PoC.misc.sync.Command ##################### diff --git a/docs/IPCores/misc/sync/sync_Pulse.rst b/docs/IPCores/misc/sync/sync_Pulse.rst index 36015518c..e80f85f0d 100644 --- a/docs/IPCores/misc/sync/sync_Pulse.rst +++ b/docs/IPCores/misc/sync/sync_Pulse.rst @@ -1,4 +1,4 @@ -.. _IP:sync_Pulse: +.. _IP/sync_Pulse: PoC.misc.sync.Pulse ################### diff --git a/docs/IPCores/misc/sync/sync_Reset.rst b/docs/IPCores/misc/sync/sync_Reset.rst index aa6f170a0..62979945e 100644 --- a/docs/IPCores/misc/sync/sync_Reset.rst +++ b/docs/IPCores/misc/sync/sync_Reset.rst @@ -1,4 +1,4 @@ -.. _IP:sync_Reset: +.. _IP/sync_Reset: PoC.misc.sync.Reset ################### diff --git a/docs/IPCores/misc/sync/sync_Strobe.rst b/docs/IPCores/misc/sync/sync_Strobe.rst index 06ccf2929..fb58d9959 100644 --- a/docs/IPCores/misc/sync/sync_Strobe.rst +++ b/docs/IPCores/misc/sync/sync_Strobe.rst @@ -1,4 +1,4 @@ -.. _IP:sync_Strobe: +.. _IP/sync_Strobe: PoC.misc.sync.Strobe #################### diff --git a/docs/IPCores/misc/sync/sync_Vector.rst b/docs/IPCores/misc/sync/sync_Vector.rst index 10d478adb..6058ddb88 100644 --- a/docs/IPCores/misc/sync/sync_Vector.rst +++ b/docs/IPCores/misc/sync/sync_Vector.rst @@ -1,4 +1,4 @@ -.. _IP:sync_Vector: +.. _IP/sync_Vector: PoC.misc.sync.Vector #################### diff --git a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst index f59c31fdd..f3e200dc4 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst @@ -1,4 +1,4 @@ -.. _IP:arp_BroadCast_Receiver: +.. _IP/arp_BroadCast_Receiver: PoC.net.arp.BroadCast_Receiver ############################## diff --git a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst index 99d68b0d2..0fc6d86fc 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst @@ -1,4 +1,4 @@ -.. _IP:arp_BroadCast_Requester: +.. _IP/arp_BroadCast_Requester: PoC.net.arp.BroadCast_Requester ############################### diff --git a/docs/IPCores/net/arp/arp_Cache.rst b/docs/IPCores/net/arp/arp_Cache.rst index 27dccbf0c..0fbd274c6 100644 --- a/docs/IPCores/net/arp/arp_Cache.rst +++ b/docs/IPCores/net/arp/arp_Cache.rst @@ -1,4 +1,4 @@ -.. _IP:arp_Cache: +.. _IP/arp_Cache: PoC.net.arp.Cache ################# diff --git a/docs/IPCores/net/arp/arp_IPPool.rst b/docs/IPCores/net/arp/arp_IPPool.rst index ad6962244..ea8bc8168 100644 --- a/docs/IPCores/net/arp/arp_IPPool.rst +++ b/docs/IPCores/net/arp/arp_IPPool.rst @@ -1,4 +1,4 @@ -.. _IP:arp_IPPool: +.. _IP/arp_IPPool: PoC.net.arp.IPPool ################## diff --git a/docs/IPCores/net/arp/arp_Tester.rst b/docs/IPCores/net/arp/arp_Tester.rst index c179f6069..bc5d2f444 100644 --- a/docs/IPCores/net/arp/arp_Tester.rst +++ b/docs/IPCores/net/arp/arp_Tester.rst @@ -1,4 +1,4 @@ -.. _IP:arp_Tester: +.. _IP/arp_Tester: PoC.net.arp.Tester ################## diff --git a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst index 98180b978..9de1c9603 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst @@ -1,4 +1,4 @@ -.. _IP:arp_UniCast_Receiver: +.. _IP/arp_UniCast_Receiver: PoC.net.arp.UniCast_Receiver ############################ diff --git a/docs/IPCores/net/arp/arp_UniCast_Responder.rst b/docs/IPCores/net/arp/arp_UniCast_Responder.rst index ec4da49fe..7d6f6ae88 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Responder.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Responder.rst @@ -1,4 +1,4 @@ -.. _IP:arp_UniCast_Responder: +.. _IP/arp_UniCast_Responder: PoC.net.arp.UniCast_Responder ############################# diff --git a/docs/IPCores/net/arp/arp_Wrapper.rst b/docs/IPCores/net/arp/arp_Wrapper.rst index 58750f5ae..fbf63b875 100644 --- a/docs/IPCores/net/arp/arp_Wrapper.rst +++ b/docs/IPCores/net/arp/arp_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:arp_Wrapper: +.. _IP/arp_Wrapper: PoC.net.arp.Wrapper ################### diff --git a/docs/IPCores/net/arp/index.rst b/docs/IPCores/net/arp/index.rst index 05bd2b95f..f2388251d 100644 --- a/docs/IPCores/net/arp/index.rst +++ b/docs/IPCores/net/arp/index.rst @@ -1,4 +1,4 @@ -.. _NS:arp: +.. _NS/arp: PoC.net.arp =========== diff --git a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst index 59edd6082..68d767f8f 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst @@ -1,4 +1,4 @@ -.. _IP:eth_GEMAC_GMII: +.. _IP/eth_GEMAC_GMII: PoC.net.eth.GEMAC_GMII ###################### diff --git a/docs/IPCores/net/eth/eth_GEMAC_RX.rst b/docs/IPCores/net/eth/eth_GEMAC_RX.rst index a3a48f697..837cb94ee 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_RX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_RX.rst @@ -1,4 +1,4 @@ -.. _IP:Eth_GEMAC_RX: +.. _IP/Eth_GEMAC_RX: PoC.net.eth.GEMAC_RX #################### diff --git a/docs/IPCores/net/eth/eth_GEMAC_TX.rst b/docs/IPCores/net/eth/eth_GEMAC_TX.rst index 5a8e6e456..5ae2accbf 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_TX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_TX.rst @@ -1,4 +1,4 @@ -.. _IP:Eth_GEMAC_TX: +.. _IP/Eth_GEMAC_TX: PoC.net.eth.GEMAC_TX #################### diff --git a/docs/IPCores/net/eth/eth_PHYController.rst b/docs/IPCores/net/eth/eth_PHYController.rst index 45b6f121d..714f5c0a4 100644 --- a/docs/IPCores/net/eth/eth_PHYController.rst +++ b/docs/IPCores/net/eth/eth_PHYController.rst @@ -1,4 +1,4 @@ -.. _IP:Eth_PHYController: +.. _IP/Eth_PHYController: PoC.net.eth.PHYController ######################### diff --git a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst index 9912b632f..11446eff7 100644 --- a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst +++ b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst @@ -1,4 +1,4 @@ -.. _IP:Eth_PHYController_Marvell_88E1111: +.. _IP/Eth_PHYController_Marvell_88E1111: PoC.net.eth.PHYController_Marvell_88E1111 ######################################### diff --git a/docs/IPCores/net/eth/eth_Wrapper.rst b/docs/IPCores/net/eth/eth_Wrapper.rst index aebdc49d2..1da5c07f1 100644 --- a/docs/IPCores/net/eth/eth_Wrapper.rst +++ b/docs/IPCores/net/eth/eth_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:Eth_Wrapper: +.. _IP/Eth_Wrapper: PoC.net.eth.Wrapper ################### diff --git a/docs/IPCores/net/eth/index.rst b/docs/IPCores/net/eth/index.rst index d3d74f8e9..e8e4b89fa 100644 --- a/docs/IPCores/net/eth/index.rst +++ b/docs/IPCores/net/eth/index.rst @@ -1,4 +1,4 @@ -.. _NS:eth: +.. _NS/eth: PoC.net.eth =========== diff --git a/docs/IPCores/net/icmpv4/icmpv4_RX.rst b/docs/IPCores/net/icmpv4/icmpv4_RX.rst index 74acdffab..c109e221c 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_RX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_RX.rst @@ -1,4 +1,4 @@ -.. _IP:icmpv4_RX: +.. _IP/icmpv4_RX: PoC.net.icmpv4.RX ################# diff --git a/docs/IPCores/net/icmpv4/icmpv4_TX.rst b/docs/IPCores/net/icmpv4/icmpv4_TX.rst index 8ff373e73..bdb6a0a2c 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_TX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_TX.rst @@ -1,4 +1,4 @@ -.. _IP:icmpv4_TX: +.. _IP/icmpv4_TX: PoC.net.icmpv4.TX ################# diff --git a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst index 268f394a0..26d03fc82 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:icmpv4_Wrapper: +.. _IP/icmpv4_Wrapper: PoC.net.icmpv4.Wrapper ###################### diff --git a/docs/IPCores/net/icmpv4/index.rst b/docs/IPCores/net/icmpv4/index.rst index ab12b94ef..04d079a53 100644 --- a/docs/IPCores/net/icmpv4/index.rst +++ b/docs/IPCores/net/icmpv4/index.rst @@ -1,4 +1,4 @@ -.. _NS:icmpv4: +.. _NS/icmpv4: PoC.net.icmpv4 ============== diff --git a/docs/IPCores/net/icmpv6/icmpv6_RX.rst b/docs/IPCores/net/icmpv6/icmpv6_RX.rst index e08c5751c..c4ee75257 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_RX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_RX.rst @@ -1,4 +1,4 @@ -.. _IP:icmpv6_RX: +.. _IP/icmpv6_RX: PoC.net.icmpv6.RX ################# diff --git a/docs/IPCores/net/icmpv6/icmpv6_TX.rst b/docs/IPCores/net/icmpv6/icmpv6_TX.rst index cf1b6bc63..105e09ffe 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_TX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_TX.rst @@ -1,4 +1,4 @@ -.. _IP:icmpv6_TX: +.. _IP/icmpv6_TX: PoC.net.icmpv6.TX ################# diff --git a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst index 0c424ce02..319b04bf9 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:icmpv6_Wrapper: +.. _IP/icmpv6_Wrapper: PoC.net.icmpv6.Wrapper ###################### diff --git a/docs/IPCores/net/icmpv6/index.rst b/docs/IPCores/net/icmpv6/index.rst index 452d9eea8..9a5bec5b6 100644 --- a/docs/IPCores/net/icmpv6/index.rst +++ b/docs/IPCores/net/icmpv6/index.rst @@ -1,4 +1,4 @@ -.. _NS:icmpv6: +.. _NS/icmpv6: PoC.net.icmpv6 ============== diff --git a/docs/IPCores/net/index.rst b/docs/IPCores/net/index.rst index 259af5590..8d96bf36a 100644 --- a/docs/IPCores/net/index.rst +++ b/docs/IPCores/net/index.rst @@ -1,4 +1,4 @@ -.. _NS:net: +.. _NS/net: PoC.net ======== @@ -7,21 +7,21 @@ These are bus entities.... **Sub-Namespaces** - * :ref:`NS:arp` - * :ref:`NS:eth` - * :ref:`NS:icmpv4` - * :ref:`NS:icmpv6` - * :ref:`NS:ipv4` - * :ref:`NS:ipv6` - * :ref:`NS:mac` - * :ref:`NS:ndp` - * :ref:`NS:stack` - * :ref:`NS:udp` + * :ref:`NS/arp` + * :ref:`NS/eth` + * :ref:`NS/icmpv4` + * :ref:`NS/icmpv6` + * :ref:`NS/ipv4` + * :ref:`NS/ipv6` + * :ref:`NS/mac` + * :ref:`NS/ndp` + * :ref:`NS/stack` + * :ref:`NS/udp` **Entities** - * :ref:`IP:net_FrameChecksum` - * :ref:`IP:net_FrameLoopback` + * :ref:`IP/net_FrameChecksum` + * :ref:`IP/net_FrameLoopback` .. toctree:: :hidden: diff --git a/docs/IPCores/net/ipv4/index.rst b/docs/IPCores/net/ipv4/index.rst index 0aaec1253..3e564f5b1 100644 --- a/docs/IPCores/net/ipv4/index.rst +++ b/docs/IPCores/net/ipv4/index.rst @@ -1,4 +1,4 @@ -.. _NS:ipv4: +.. _NS/ipv4: PoC.net.ipv4 ============ diff --git a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst index 13779ba28..1bab4b963 100644 --- a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst +++ b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst @@ -1,4 +1,4 @@ -.. _IP:ipv4_FrameLoopback: +.. _IP/ipv4_FrameLoopback: PoC.net.ipv4.FrameLoopback ########################## diff --git a/docs/IPCores/net/ipv4/ipv4_RX.rst b/docs/IPCores/net/ipv4/ipv4_RX.rst index f665cd30a..5448effa7 100644 --- a/docs/IPCores/net/ipv4/ipv4_RX.rst +++ b/docs/IPCores/net/ipv4/ipv4_RX.rst @@ -1,4 +1,4 @@ -.. _IP:ipv4_RX: +.. _IP/ipv4_RX: PoC.net.ipv4.RX ############### diff --git a/docs/IPCores/net/ipv4/ipv4_TX.rst b/docs/IPCores/net/ipv4/ipv4_TX.rst index f0e4e3331..9dcced7e7 100644 --- a/docs/IPCores/net/ipv4/ipv4_TX.rst +++ b/docs/IPCores/net/ipv4/ipv4_TX.rst @@ -1,4 +1,4 @@ -.. _IP:ipv4_TX: +.. _IP/ipv4_TX: PoC.net.ipv4.TX ############### diff --git a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst index 6f9cf25d9..34a9d9d78 100644 --- a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst +++ b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:ipv4_Wrapper: +.. _IP/ipv4_Wrapper: PoC.net.ipv4.Wrapper #################### diff --git a/docs/IPCores/net/ipv6/index.rst b/docs/IPCores/net/ipv6/index.rst index 205edfb83..b1f4b3122 100644 --- a/docs/IPCores/net/ipv6/index.rst +++ b/docs/IPCores/net/ipv6/index.rst @@ -1,4 +1,4 @@ -.. _NS:ipv6: +.. _NS/ipv6: PoC.net.ipv6 ============ diff --git a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst index 0f2e6a9a5..1e48f71d4 100644 --- a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst +++ b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst @@ -1,4 +1,4 @@ -.. _IP:ipv6_FrameLoopback: +.. _IP/ipv6_FrameLoopback: PoC.net.ipv6.FrameLoopback ########################## diff --git a/docs/IPCores/net/ipv6/ipv6_RX.rst b/docs/IPCores/net/ipv6/ipv6_RX.rst index 6a8a7bea6..533571440 100644 --- a/docs/IPCores/net/ipv6/ipv6_RX.rst +++ b/docs/IPCores/net/ipv6/ipv6_RX.rst @@ -1,4 +1,4 @@ -.. _IP:ipv6_RX: +.. _IP/ipv6_RX: PoC.net.ipv6.RX ############### diff --git a/docs/IPCores/net/ipv6/ipv6_TX.rst b/docs/IPCores/net/ipv6/ipv6_TX.rst index 39ab179b0..b1fdb4b52 100644 --- a/docs/IPCores/net/ipv6/ipv6_TX.rst +++ b/docs/IPCores/net/ipv6/ipv6_TX.rst @@ -1,4 +1,4 @@ -.. _IP:ipv6_TX: +.. _IP/ipv6_TX: PoC.net.ipv6.TX ############### diff --git a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst index 7bce03cc7..004d10eee 100644 --- a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst +++ b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:ipv6_Wrapper: +.. _IP/ipv6_Wrapper: PoC.net.ipv6.Wrapper #################### diff --git a/docs/IPCores/net/mac/index.rst b/docs/IPCores/net/mac/index.rst index e4cf77049..65f3eb37f 100644 --- a/docs/IPCores/net/mac/index.rst +++ b/docs/IPCores/net/mac/index.rst @@ -1,4 +1,4 @@ -.. _NS:mac: +.. _NS/mac: PoC.net.mac =========== diff --git a/docs/IPCores/net/mac/mac_FrameLoopback.rst b/docs/IPCores/net/mac/mac_FrameLoopback.rst index 13950b616..3f658b0eb 100644 --- a/docs/IPCores/net/mac/mac_FrameLoopback.rst +++ b/docs/IPCores/net/mac/mac_FrameLoopback.rst @@ -1,4 +1,4 @@ -.. _IP:mac_FrameLoopback: +.. _IP/mac_FrameLoopback: PoC.net.mac.FrameLoopback ######################### diff --git a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst index a9d4decff..e8d76049f 100644 --- a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst @@ -1,4 +1,4 @@ -.. _IP:mac_RX_DestMAC_Switch: +.. _IP/mac_RX_DestMAC_Switch: PoC.net.mac.RX_DestMAC_Switch ############################# diff --git a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst index 798b3c628..5bbf885d7 100644 --- a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst +++ b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst @@ -1,4 +1,4 @@ -.. _IP:mac_RX_SrcMAC_Filter: +.. _IP/mac_RX_SrcMAC_Filter: PoC.net.mac.RX_SrcMAC_Filter ############################ diff --git a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst index 405916ff4..6c582ddc2 100644 --- a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst @@ -1,4 +1,4 @@ -.. _IP:mac_RX_Type_Switch: +.. _IP/mac_RX_Type_Switch: PoC.net.mac.RX_Type_Switch ########################## diff --git a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst index e1c35e1ca..b12a2ac75 100644 --- a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst @@ -1,4 +1,4 @@ -.. _IP:mac_TX_DestMAC_Prepender: +.. _IP/mac_TX_DestMAC_Prepender: PoC.net.mac.TX_DestMAC_Prepender ################################ diff --git a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst index 3d2bf0893..31cf44f09 100644 --- a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst @@ -1,4 +1,4 @@ -.. _IP:mac_TX_SrcMAC_Prepender: +.. _IP/mac_TX_SrcMAC_Prepender: PoC.net.mac.TX_SrcMAC_Prepender ############################### diff --git a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst index cba4445cf..fc20694df 100644 --- a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst @@ -1,4 +1,4 @@ -.. _IP:mac_TX_Type_Prepender: +.. _IP/mac_TX_Type_Prepender: PoC.net.mac.TX_Type_Prepender ############################# diff --git a/docs/IPCores/net/mac/mac_Wrapper.rst b/docs/IPCores/net/mac/mac_Wrapper.rst index b930cff86..1bcc82b88 100644 --- a/docs/IPCores/net/mac/mac_Wrapper.rst +++ b/docs/IPCores/net/mac/mac_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:mac_Wrapper: +.. _IP/mac_Wrapper: PoC.net.mac.Wrapper ################### diff --git a/docs/IPCores/net/ndp/index.rst b/docs/IPCores/net/ndp/index.rst index 5d718eae3..1fd732854 100644 --- a/docs/IPCores/net/ndp/index.rst +++ b/docs/IPCores/net/ndp/index.rst @@ -1,4 +1,4 @@ -.. _NS:ndp: +.. _NS/ndp: PoC.net.ndp =========== diff --git a/docs/IPCores/net/ndp/ndp_DestinationCache.rst b/docs/IPCores/net/ndp/ndp_DestinationCache.rst index ea92da577..155f0f986 100644 --- a/docs/IPCores/net/ndp/ndp_DestinationCache.rst +++ b/docs/IPCores/net/ndp/ndp_DestinationCache.rst @@ -1,4 +1,4 @@ -.. _IP:ndp_DestinationCache: +.. _IP/ndp_DestinationCache: PoC.net.ndp.DestinationCache ############################ diff --git a/docs/IPCores/net/ndp/ndp_FSMQuery.rst b/docs/IPCores/net/ndp/ndp_FSMQuery.rst index 22220f80f..c684d8431 100644 --- a/docs/IPCores/net/ndp/ndp_FSMQuery.rst +++ b/docs/IPCores/net/ndp/ndp_FSMQuery.rst @@ -1,4 +1,4 @@ -.. _IP:ndp_FSMQuery: +.. _IP/ndp_FSMQuery: PoC.net.ndp.FSMQuery #################### diff --git a/docs/IPCores/net/ndp/ndp_NeighborCache.rst b/docs/IPCores/net/ndp/ndp_NeighborCache.rst index b1dd16ee2..733632024 100644 --- a/docs/IPCores/net/ndp/ndp_NeighborCache.rst +++ b/docs/IPCores/net/ndp/ndp_NeighborCache.rst @@ -1,4 +1,4 @@ -.. _IP:ndp_NeighborCache: +.. _IP/ndp_NeighborCache: PoC.net.ndp.NeighborCache ######################### diff --git a/docs/IPCores/net/ndp/ndp_Wrapper.rst b/docs/IPCores/net/ndp/ndp_Wrapper.rst index 643a32c46..bdee23131 100644 --- a/docs/IPCores/net/ndp/ndp_Wrapper.rst +++ b/docs/IPCores/net/ndp/ndp_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:NDP_Wrapper: +.. _IP/NDP_Wrapper: PoC.net.ndp.Wrapper ################### diff --git a/docs/IPCores/net/net.pkg.rst b/docs/IPCores/net/net.pkg.rst index 02c86e0ea..aef13b1a7 100644 --- a/docs/IPCores/net/net.pkg.rst +++ b/docs/IPCores/net/net.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:net: +.. _PKG/net: PoC.net Package =============== diff --git a/docs/IPCores/net/net_FrameChecksum.rst b/docs/IPCores/net/net_FrameChecksum.rst index 067e2dbce..17654d230 100644 --- a/docs/IPCores/net/net_FrameChecksum.rst +++ b/docs/IPCores/net/net_FrameChecksum.rst @@ -1,4 +1,4 @@ -.. _IP:net_FrameChecksum: +.. _IP/net_FrameChecksum: PoC.net.FrameChecksum ##################### diff --git a/docs/IPCores/net/net_FrameLoopback.rst b/docs/IPCores/net/net_FrameLoopback.rst index a0b8ddb37..380a9483a 100644 --- a/docs/IPCores/net/net_FrameLoopback.rst +++ b/docs/IPCores/net/net_FrameLoopback.rst @@ -1,4 +1,4 @@ -.. _IP:FrameLoopback: +.. _IP/FrameLoopback: PoC.net.FrameLoopback ##################### diff --git a/docs/IPCores/net/net_FramePerformanceCounter.rst b/docs/IPCores/net/net_FramePerformanceCounter.rst index c6a6ae9a6..396ffaf49 100644 --- a/docs/IPCores/net/net_FramePerformanceCounter.rst +++ b/docs/IPCores/net/net_FramePerformanceCounter.rst @@ -1,4 +1,4 @@ -.. _IP:LocalLink_PerformanceCounter: +.. _IP/LocalLink_PerformanceCounter: PoC.net.FramePerformanceCounter ############################### diff --git a/docs/IPCores/net/stack/index.rst b/docs/IPCores/net/stack/index.rst index 2513173d7..52b749cb8 100644 --- a/docs/IPCores/net/stack/index.rst +++ b/docs/IPCores/net/stack/index.rst @@ -1,4 +1,4 @@ -.. _NS:stack: +.. _NS/stack: PoC.net.stack ============= diff --git a/docs/IPCores/net/stack/stack_UDPv4.rst b/docs/IPCores/net/stack/stack_UDPv4.rst index a9caf2ab0..67474b7b4 100644 --- a/docs/IPCores/net/stack/stack_UDPv4.rst +++ b/docs/IPCores/net/stack/stack_UDPv4.rst @@ -1,4 +1,4 @@ -.. _IP:stack_UDPv4: +.. _IP/stack_UDPv4: PoC.net.stack.UDPv4 ################### diff --git a/docs/IPCores/net/udp/index.rst b/docs/IPCores/net/udp/index.rst index bbc99c004..e3b501472 100644 --- a/docs/IPCores/net/udp/index.rst +++ b/docs/IPCores/net/udp/index.rst @@ -1,4 +1,4 @@ -.. _NS:udp: +.. _NS/udp: PoC.net.udp =========== diff --git a/docs/IPCores/net/udp/udp_FrameLoopback.rst b/docs/IPCores/net/udp/udp_FrameLoopback.rst index a2138d1ea..0e8bcbd42 100644 --- a/docs/IPCores/net/udp/udp_FrameLoopback.rst +++ b/docs/IPCores/net/udp/udp_FrameLoopback.rst @@ -1,4 +1,4 @@ -.. _IP:udp_FrameLoopback: +.. _IP/udp_FrameLoopback: PoC.net.udp.FrameLoopback ######################### diff --git a/docs/IPCores/net/udp/udp_RX.rst b/docs/IPCores/net/udp/udp_RX.rst index 35c2a6d5a..716d391a7 100644 --- a/docs/IPCores/net/udp/udp_RX.rst +++ b/docs/IPCores/net/udp/udp_RX.rst @@ -1,4 +1,4 @@ -.. _IP:udp_RX: +.. _IP/udp_RX: PoC.net.udp.RX ############## diff --git a/docs/IPCores/net/udp/udp_TX.rst b/docs/IPCores/net/udp/udp_TX.rst index c8be4697f..70a66ecb4 100644 --- a/docs/IPCores/net/udp/udp_TX.rst +++ b/docs/IPCores/net/udp/udp_TX.rst @@ -1,4 +1,4 @@ -.. _IP:udp_TX: +.. _IP/udp_TX: PoC.net.udp.TX ############## diff --git a/docs/IPCores/net/udp/udp_Wrapper.rst b/docs/IPCores/net/udp/udp_Wrapper.rst index 97d4cdb54..823bb5892 100644 --- a/docs/IPCores/net/udp/udp_Wrapper.rst +++ b/docs/IPCores/net/udp/udp_Wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:udp_Wrapper: +.. _IP/udp_Wrapper: PoC.net.udp.Wrapper ################### diff --git a/docs/IPCores/sort/index.rst b/docs/IPCores/sort/index.rst index 11139acc1..1746ea409 100644 --- a/docs/IPCores/sort/index.rst +++ b/docs/IPCores/sort/index.rst @@ -1,4 +1,4 @@ -.. _NS:sort: +.. _NS/sort: PoC.sort ======== @@ -7,15 +7,15 @@ These are sorting entities.... **Sub-Namespaces** - * :ref:`NS:sortnet` + * :ref:`NS/sortnet` **Entities** - * :ref:`IP:sort_ExpireList` - * :ref:`IP:sort_InsertSort` - * :ref:`IP:sort_LeastFrequentlyUsed` - * :ref:`IP:sort_lru_cache` - * :ref:`IP:sort_lru_list` + * :ref:`IP/sort_ExpireList` + * :ref:`IP/sort_InsertSort` + * :ref:`IP/sort_LeastFrequentlyUsed` + * :ref:`IP/sort_lru_cache` + * :ref:`IP/sort_lru_list` .. toctree:: :hidden: diff --git a/docs/IPCores/sort/sort_ExpireList.rst b/docs/IPCores/sort/sort_ExpireList.rst index 630ccea47..a4800d431 100644 --- a/docs/IPCores/sort/sort_ExpireList.rst +++ b/docs/IPCores/sort/sort_ExpireList.rst @@ -1,4 +1,4 @@ -.. _IP:sort_expirelist: +.. _IP/sort_expirelist: PoC.sort.ExpireList ################### diff --git a/docs/IPCores/sort/sort_InsertSort.rst b/docs/IPCores/sort/sort_InsertSort.rst index 1dd11515b..fc63b92f7 100644 --- a/docs/IPCores/sort/sort_InsertSort.rst +++ b/docs/IPCores/sort/sort_InsertSort.rst @@ -1,4 +1,4 @@ -.. _IP:sort_insertsort: +.. _IP/sort_insertsort: PoC.sort.InsertSort ################### diff --git a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst index 14227dff9..535019369 100644 --- a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst +++ b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst @@ -1,4 +1,4 @@ -.. _IP:sort_LeastFrequentlyUsed: +.. _IP/sort_LeastFrequentlyUsed: PoC.sort.LeastFrequentlyUsed ############################ diff --git a/docs/IPCores/sort/sort_lru_cache.rst b/docs/IPCores/sort/sort_lru_cache.rst index b97b72c2f..5eb05c37d 100644 --- a/docs/IPCores/sort/sort_lru_cache.rst +++ b/docs/IPCores/sort/sort_lru_cache.rst @@ -1,4 +1,4 @@ -.. _IP:sort_lru_cache: +.. _IP/sort_lru_cache: PoC.sort.lru_cache ################## diff --git a/docs/IPCores/sort/sort_lru_list.rst b/docs/IPCores/sort/sort_lru_list.rst index f61b148f3..765706784 100644 --- a/docs/IPCores/sort/sort_lru_list.rst +++ b/docs/IPCores/sort/sort_lru_list.rst @@ -1,4 +1,4 @@ -.. _IP:sort_lru_list: +.. _IP/sort_lru_list: PoC.sort.lru_list ################# diff --git a/docs/IPCores/sort/sortnet/index.rst b/docs/IPCores/sort/sortnet/index.rst index 5b25deb31..3c0bba3de 100644 --- a/docs/IPCores/sort/sortnet/index.rst +++ b/docs/IPCores/sort/sortnet/index.rst @@ -1,4 +1,4 @@ -.. _NS:sortnet: +.. _NS/sortnet: PoC.sort.sortnet ================ @@ -7,13 +7,13 @@ This sub-namespace contains sorting network implementations. **Entities** - * :ref:`IP:sortnet_BitonicSort` - * :ref:`IP:sortnet_MergeSort_Streamed` - * :ref:`IP:sortnet_OddEvenMergeSort` - * :ref:`IP:sortnet_OddEvenSort` - * :ref:`IP:sortnet_Stream_Adapter` - * :ref:`IP:sortnet_Stream_Adapter2` - * :ref:`IP:sortnet_Transform` + * :ref:`IP/sortnet_BitonicSort` + * :ref:`IP/sortnet_MergeSort_Streamed` + * :ref:`IP/sortnet_OddEvenMergeSort` + * :ref:`IP/sortnet_OddEvenSort` + * :ref:`IP/sortnet_Stream_Adapter` + * :ref:`IP/sortnet_Stream_Adapter2` + * :ref:`IP/sortnet_Transform` .. toctree:: diff --git a/docs/IPCores/sort/sortnet/sortnet.pkg.rst b/docs/IPCores/sort/sortnet/sortnet.pkg.rst index ed9f79f8e..5b43bde55 100644 --- a/docs/IPCores/sort/sortnet/sortnet.pkg.rst +++ b/docs/IPCores/sort/sortnet/sortnet.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:sortnet: +.. _PKG/sortnet: PoC.sort.sortnet Package ======================== @@ -25,13 +25,13 @@ PoC.sort.sortnet Package .. c:type:: T_SORTNET_IMPL SORT_SORTNET_IMPL_ODDEVEN_SORT - Instantiate a :ref:`IP:sortnet_OddEvenSort` sorting network. + Instantiate a :ref:`IP/sortnet_OddEvenSort` sorting network. SORT_SORTNET_IMPL_ODDEVEN_MERGESORT - Instantiate a :ref:`IP:sortnet_OddEvenMergeSort` sorting network. + Instantiate a :ref:`IP/sortnet_OddEvenMergeSort` sorting network. SORT_SORTNET_IMPL_BITONIC_SORT - Instantiate a :ref:`IP:sortnet_BitonicSort` sorting network. + Instantiate a :ref:`IP/sortnet_BitonicSort` sorting network. .. only:: latex diff --git a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst index 58274b6da..d53e71343 100644 --- a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst @@ -1,4 +1,4 @@ -.. _IP:sortnet_BitonicSort: +.. _IP/sortnet_BitonicSort: PoC.sort.sortnet.BitonicSort ############################ diff --git a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst index eaeb3c3fd..bb509e05b 100644 --- a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst +++ b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst @@ -1,4 +1,4 @@ -.. _IP:sortnet_MergeSort_Streamed: +.. _IP/sortnet_MergeSort_Streamed: PoC.sort.sortnet.MergeSort_Streamed ################################### diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst index 53ff38113..468c14060 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst @@ -1,4 +1,4 @@ -.. _IP:sortnet_OddEvenMergeSort: +.. _IP/sortnet_OddEvenMergeSort: PoC.sort.sortnet.OddEvenMergeSort ################################# diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst index 3b27af416..c33fffd0d 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst @@ -1,4 +1,4 @@ -.. _IP:sortnet_OddEvenSort: +.. _IP/sortnet_OddEvenSort: PoC.sort.sortnet.OddEvenSort ############################ diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst index a93306798..6e9278ae9 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst @@ -1,4 +1,4 @@ -.. _IP:sortnet_Stream_Adapter: +.. _IP/sortnet_Stream_Adapter: PoC.sort.sortnet.Stream_Adapter ############################### diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst index 3043097c8..26c1b1d0f 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst @@ -1,4 +1,4 @@ -.. _IP:sortnet_Stream_Adapter2: +.. _IP/sortnet_Stream_Adapter2: PoC.sort.sortnet.Stream_Adapter2 ################################ diff --git a/docs/IPCores/sort/sortnet/sortnet_Transform.rst b/docs/IPCores/sort/sortnet/sortnet_Transform.rst index cbb43a5f2..0abe6e479 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Transform.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Transform.rst @@ -1,4 +1,4 @@ -.. _IP:sortnet_Transform: +.. _IP/sortnet_Transform: PoC.sort.sortnet.Transform ########################## diff --git a/docs/IPCores/xil/index.rst b/docs/IPCores/xil/index.rst index ba93cb856..af1dc1c4a 100644 --- a/docs/IPCores/xil/index.rst +++ b/docs/IPCores/xil/index.rst @@ -1,4 +1,4 @@ -.. _NS:xil: +.. _NS/xil: PoC.xil ======== @@ -7,19 +7,18 @@ This namespace is for Xilinx specific modules. **Sub-Namespaces** - * :ref:`NS:mig` - * :ref:`NS:reconfig` + * :ref:`NS/mig` + * :ref:`NS/reconfig` **Entities** - * :ref:`IP:xil_BSCAN` - * :ref:`IP:xil_ChipScopeICON` - * :ref:`IP:xil_DRP_BusMux` - * :ref:`IP:xil_DRP_BusSync` - * :ref:`IP:xil_ICAP` - * :ref:`IP:xil_Reconfigurator` - * :ref:`IP:xil_SystemMonitor` - * :ref:`IP:xil_SystemMonitor` + * :ref:`IP/xil_BSCAN` + * :ref:`IP/xil_DRP_BusMux` + * :ref:`IP/xil_DRP_BusSync` + * :ref:`IP/xil_ICAP` + * :ref:`IP/xil_Reconfigurator` + * :ref:`IP/xil_SystemMonitor` + * :ref:`IP/xil_SystemMonitor` .. toctree:: @@ -37,7 +36,6 @@ This namespace is for Xilinx specific modules. :hidden: xil_BSCAN - xil_ChipScopeICON xil_DRP_BusMux xil_DRP_BusSync xil_ICAP diff --git a/docs/IPCores/xil/reconfig/index.rst b/docs/IPCores/xil/reconfig/index.rst index 079beba35..659d6b18e 100644 --- a/docs/IPCores/xil/reconfig/index.rst +++ b/docs/IPCores/xil/reconfig/index.rst @@ -1,4 +1,4 @@ -.. _NS:reconfig: +.. _NS/reconfig: PoC.xil.reconfig ================ @@ -7,8 +7,8 @@ These are reconfig entities.... **Entities** - * :ref:`IP:reconfig_icap_fsm` - * :ref:`IP:reconfig_icap_wrapper` + * :ref:`IP/reconfig_icap_fsm` + * :ref:`IP/reconfig_icap_wrapper` .. toctree:: :hidden: diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst index 5d9d25440..f063e7c03 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst @@ -1,4 +1,4 @@ -.. _IP:reconfig_icap_fsm: +.. _IP/reconfig_icap_fsm: PoC.xil.reconfig.icap_fsm ######################### diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst index 3bbfba70b..8a22b5dd1 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst @@ -1,4 +1,4 @@ -.. _IP:reconfig_icap_wrapper: +.. _IP/reconfig_icap_wrapper: PoC.xil.reconfig.icap_wrapper ############################# diff --git a/docs/IPCores/xil/xil.pkg.rst b/docs/IPCores/xil/xil.pkg.rst index a74bccdc6..d2e794084 100644 --- a/docs/IPCores/xil/xil.pkg.rst +++ b/docs/IPCores/xil/xil.pkg.rst @@ -9,7 +9,7 @@ |gh-src| :pocsrc:`Sourcecode ` -.. _PKG:xil: +.. _PKG/xil: PoC.xil Package ================ diff --git a/docs/IPCores/xil/xil_BSCAN.rst b/docs/IPCores/xil/xil_BSCAN.rst index 9d0063a89..33e316b13 100644 --- a/docs/IPCores/xil/xil_BSCAN.rst +++ b/docs/IPCores/xil/xil_BSCAN.rst @@ -1,4 +1,4 @@ -.. _IP:xil_BSCAN: +.. _IP/xil_BSCAN: PoC.xil.BSCAN ############# diff --git a/docs/IPCores/xil/xil_DRP_BusMux.rst b/docs/IPCores/xil/xil_DRP_BusMux.rst index 5f2182e7f..c05d89f00 100644 --- a/docs/IPCores/xil/xil_DRP_BusMux.rst +++ b/docs/IPCores/xil/xil_DRP_BusMux.rst @@ -1,4 +1,4 @@ -.. _IP:xil_DRP_BusMux: +.. _IP/xil_DRP_BusMux: PoC.xil.DRP_BusMux ################## diff --git a/docs/IPCores/xil/xil_DRP_BusSync.rst b/docs/IPCores/xil/xil_DRP_BusSync.rst index 431dfbe1d..fb494b452 100644 --- a/docs/IPCores/xil/xil_DRP_BusSync.rst +++ b/docs/IPCores/xil/xil_DRP_BusSync.rst @@ -1,4 +1,4 @@ -.. _IP:xil_DRP_BusSync: +.. _IP/xil_DRP_BusSync: PoC.xil.DRP_BusSync ################### diff --git a/docs/IPCores/xil/xil_ICAP.rst b/docs/IPCores/xil/xil_ICAP.rst index c084cd992..75cacfe48 100644 --- a/docs/IPCores/xil/xil_ICAP.rst +++ b/docs/IPCores/xil/xil_ICAP.rst @@ -1,4 +1,4 @@ -.. _IP:xil_ICAP: +.. _IP/xil_ICAP: PoC.xil.ICAP ############ diff --git a/docs/IPCores/xil/xil_Reconfigurator.rst b/docs/IPCores/xil/xil_Reconfigurator.rst index f1256b3fe..7c18df31b 100644 --- a/docs/IPCores/xil/xil_Reconfigurator.rst +++ b/docs/IPCores/xil/xil_Reconfigurator.rst @@ -1,4 +1,4 @@ -.. _IP:xil_Reconfigurator: +.. _IP/xil_Reconfigurator: PoC.xil.Reconfigurator ###################### diff --git a/docs/IPCores/xil/xil_SystemMonitor.rst b/docs/IPCores/xil/xil_SystemMonitor.rst index c8a40b4cb..1aabc349b 100644 --- a/docs/IPCores/xil/xil_SystemMonitor.rst +++ b/docs/IPCores/xil/xil_SystemMonitor.rst @@ -1,4 +1,4 @@ -.. _IP:xil_SystemMonitor: +.. _IP/xil_SystemMonitor: PoC.xil.SystemMonitor ##################### diff --git a/docs/Miscelaneous/ThirdParty.rst b/docs/Miscelaneous/ThirdParty.rst index 68b469c4e..1e5ae3245 100644 --- a/docs/Miscelaneous/ThirdParty.rst +++ b/docs/Miscelaneous/ThirdParty.rst @@ -16,7 +16,7 @@ libraries, their websites and licenses. .. index:: pair: Third-Party Libraries; OSVVM -.. _THIRD:OSVVM: +.. _THIRD/OSVVM: OSVVM ***** diff --git a/docs/QuickStart.rst b/docs/QuickStart.rst index 46343dfb0..5db085bf5 100644 --- a/docs/QuickStart.rst +++ b/docs/QuickStart.rst @@ -48,7 +48,7 @@ details and examples. :local: -.. _QUICK:Requirements: +.. _QUICK/Requirements: Requirements and Dependencies ***************************** @@ -57,13 +57,13 @@ The PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or generating IP cores. PoC uses Python 3 as a platform independent scripting environment. All Python scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. -See :ref:`USING:Require` for further details. +See :ref:`USING/Require` for further details. .. rubric:: PoC requires: -* A :ref:`supported synthesis tool chain `, if you want to synthezise IP cores. -* A :ref:`supported simulator too chain `, if you want to simulate IP cores. +* A :ref:`supported synthesis tool chain `, if you want to synthezise IP cores. +* A :ref:`supported simulator too chain `, if you want to simulate IP cores. * The **Python 3** programming language and runtime, if you want to use PoC's infrastructure. * A shell to execute shell scripts: @@ -84,7 +84,7 @@ See :ref:`USING:Require` for further details. :target: https://github.com/JimLewis/OSVVM :alt: Source Code on GitHub -* :ref:`THIRD:OSVVM` |gh-osvvm| |br| +* :ref:`THIRD/OSVVM` |gh-osvvm| |br| Open Source VHDL Verification Methodology. All dependencies are available as GitHub repositories and are linked to @@ -93,7 +93,7 @@ directory. See :ref:`Third Party Libraries ` for more details on these libraries. -.. _QUICK:Download: +.. _QUICK/Download: Download ******** @@ -101,7 +101,7 @@ Download The PoC-Library can be downloaded as a `zip-file `_ (latest 'master' branch), cloned with ``git clone`` or embedded with ``git submodule add`` from GitHub. GitHub offers HTTPS and SSH as transfer -protocols. See the :ref:`Download ` page for further +protocols. See the :ref:`Download ` page for further details. The installation directory is referred to as ``PoCRoot``. +----------+---------------------------------------------------------------------+ @@ -113,7 +113,7 @@ details. The installation directory is referred to as ``PoCRoot``. +----------+---------------------------------------------------------------------+ -.. _QUICK:Configuration: +.. _QUICK/Configuration: Configuring PoC on a Local System ********************************* @@ -122,7 +122,7 @@ To explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool chains. The following commands start a guided configuration process. Please follow the instructions on screen. It's possible to relaunch the process at any time, for example to register new tools or to -update tool versions. See :ref:`Configuration ` for +update tool versions. See :ref:`Configuration ` for more details. Run the following command line instructions to configure PoC on your local system: @@ -137,7 +137,7 @@ skip/pass a step and |kbd-Return| to accept a default value displayed in brackets. -.. _QUICK:Integration: +.. _QUICK/Integration: Integration *********** @@ -236,7 +236,7 @@ and if needed patch these IP cores. See :doc:`Synthesis ` for more details. -.. _QUICK:RunSimulation: +.. _QUICK/RunSimulation: Run a Simulation **************** @@ -274,7 +274,7 @@ status (``... ERROR``, ``FAILED``, ``NO ASSERTS`` or ``PASSED``). See :doc:`Simulation ` for more details. -.. _QUICK:RunSynthesis: +.. _QUICK/RunSynthesis: Run a Synthesis *************** @@ -303,7 +303,7 @@ synthesized to a netlist. :alt: PowerShell console output after running PoC.arith.prng with XST. -.. _QUICK:Updating: +.. _QUICK/Updating: Updating ******** diff --git a/docs/References/CmdRefs/Compile.rst b/docs/References/CmdRefs/Compile.rst index b0520690e..73829ae49 100644 --- a/docs/References/CmdRefs/Compile.rst +++ b/docs/References/CmdRefs/Compile.rst @@ -1,4 +1,4 @@ -.. _CmdRef:PreCompile: +.. _CmdRef/PreCompile: Pre-compile Scripts ################### @@ -14,7 +14,7 @@ Per simulator, one :file:`/` sub-directory is created. Each simulator directory in turn contains library directories, which may be grouped by the library vendor's name: :file:`[/]/`. -So for example: :ref:`THIRD:OSVVM` pre-compiled with GHDL is stored in +So for example: :ref:`THIRD/OSVVM` pre-compiled with GHDL is stored in :file:`/temp/precompiled/ghdl/osvvm/`. Note OSVVM is a single library and thus no vendor directory is used to group the generated files. GHDL will also create VHDL language revision sub-directories like :file:`v93/` or :file:`v08/`. diff --git a/docs/References/CmdRefs/PoC.rst b/docs/References/CmdRefs/PoC.rst index 99c9be030..265e5ed95 100644 --- a/docs/References/CmdRefs/PoC.rst +++ b/docs/References/CmdRefs/PoC.rst @@ -1,7 +1,7 @@ .. This files requires a Python module called 'PoCSphinx' to be located in the docs root folder. It expects a variable 'parser' of type ArgumentParser. -.. _CMDREF:PoC: +.. _CMDREF/PoC: Main Program (:file:`PoC.py`) ############################# diff --git a/docs/References/CmdRefs/Wrapper.rst b/docs/References/CmdRefs/Wrapper.rst index 705d9069c..d232a56ea 100644 --- a/docs/References/CmdRefs/Wrapper.rst +++ b/docs/References/CmdRefs/Wrapper.rst @@ -1,4 +1,4 @@ -.. _CmdRef:Wrapper: +.. _CmdRef/Wrapper: PoC Wrapper Scripts ################### diff --git a/docs/References/Database.rst b/docs/References/Database.rst index 21ef4b764..6b55de120 100644 --- a/docs/References/Database.rst +++ b/docs/References/Database.rst @@ -30,8 +30,8 @@ provided by ExtendedConfigParser_. The database consists of 5 *.ini files: Nodes in this file describe PoC's namespace tree and which IP cores are assigned to which namespace. -Additionally, the database refers to :ref:`*.files ` -and :ref:`*.rules ` files. The first file type describes, in +Additionally, the database refers to :ref:`*.files ` +and :ref:`*.rules ` files. The first file type describes, in an imperative language, which files are needed to compile a simulation or to run a synthesis. The latter file type contains patch instructions per IP core. See :ref:`Files Formats ` for more details. @@ -39,12 +39,12 @@ See :ref:`Files Formats ` for more details. .. _ExtendedConfigParser: https://github.com/Paebbels/ExtendedConfigParser -.. _IPDB:Structure: +.. _IPDB/Structure: Database Structure ****************** -The database is stored in multiple :ref:`INI files `, +The database is stored in multiple :ref:`INI files `, which are merged in memory to a single configuration database. Each INI file defines an associative array of *sections* and option lines. The content itself is an associative array of *options* and values. Section names are inclosed in @@ -127,7 +127,7 @@ context. uart_wrapper = Entity -.. _IPDB:Nodes: +.. _IPDB/Nodes: Nodes ===== @@ -206,7 +206,7 @@ hierarchical database. The parent node is ``PoC.bus`` and its grandparent is above.) -.. _IPDB:Refs: +.. _IPDB/Refs: References ========== @@ -216,31 +216,31 @@ References :Whatever: this is handy to create new field -.. _IPDB:Options: +.. _IPDB/Options: Options ======== -.. _IPDB:Values: +.. _IPDB/Values: Values ====== -.. _IPDB:ValueInterpol: +.. _IPDB/ValueInterpol: Value Interpolation =================== -.. _IPDB:NodeInterpol: +.. _IPDB/NodeInterpol: Node Interpolation ================== -.. _IPDB:Roots: +.. _IPDB/Roots: Root Nodes ========== @@ -254,40 +254,40 @@ Supported Options predefined variables, which can be used as a shortcut. -.. _IPDB:Files: +.. _IPDB/Files: Files in detail *************** -.. _IPDB:File:Structure: +.. _IPDB/File/Structure: config.structure.ini ==================== -.. _IPDB:File:Entity: +.. _IPDB/File/Entity: config.entity.ini ================= -.. _IPDB:File:Boards: +.. _IPDB/File/Boards: config.boards.ini ================= -.. _IPDB:File:Private: +.. _IPDB/File/Private: config.private.ini ================== -.. _IPDB:UserDefVar: +.. _IPDB/UserDefVar: User Defined Variables ********************** diff --git a/docs/References/FileFormats/FilesFormat.rst b/docs/References/FileFormats/FilesFormat.rst index 5187a0a21..dbfae96e4 100644 --- a/docs/References/FileFormats/FilesFormat.rst +++ b/docs/References/FileFormats/FilesFormat.rst @@ -1,4 +1,4 @@ -.. _FileFormat:files: +.. _FileFormat/files: *.files Format ############## diff --git a/docs/References/FileFormats/IniFormat.rst b/docs/References/FileFormats/IniFormat.rst index f41b787fa..18afd462b 100644 --- a/docs/References/FileFormats/IniFormat.rst +++ b/docs/References/FileFormats/IniFormat.rst @@ -1,4 +1,4 @@ -.. _FileFormat:ini: +.. _FileFormat/ini: .. raw:: html diff --git a/docs/References/FileFormats/RulesFormat.rst b/docs/References/FileFormats/RulesFormat.rst index 887683b6f..0c0c910ca 100644 --- a/docs/References/FileFormats/RulesFormat.rst +++ b/docs/References/FileFormats/RulesFormat.rst @@ -1,4 +1,4 @@ -.. _FileFormat:rules: +.. _FileFormat/rules: *.rules Format ############## diff --git a/docs/References/KnownIssues.rst b/docs/References/KnownIssues.rst index f56da0990..35e40d0eb 100644 --- a/docs/References/KnownIssues.rst +++ b/docs/References/KnownIssues.rst @@ -4,13 +4,13 @@ Known Issues ############ -.. _ISSUE:General: +.. _ISSUE/General: General ******* -.. _ISSUE:General:tristate: +.. _ISSUE/General/tristate: Synthesis of tri-state signals ============================== @@ -38,7 +38,7 @@ IP core description must instantiate the appropiate I/O block primitive of the target architecture like it is done by the Xilinx MIG. -.. _ISSUE:General:inout_records: +.. _ISSUE/General/inout_records: Synthesis of bidirectional records ================================== @@ -82,7 +82,7 @@ Use separate records for the input and output data flow instead. -------------------------------------------------------------------------------- -.. _ISSUE:Aldec:ActiveHDL: +.. _ISSUE/Aldec/ActiveHDL: Aldec Active-HDL **************** @@ -90,8 +90,8 @@ Aldec Active-HDL * Aliases to functions and protected type methods -.. _ISSUE:Altera:Quartus: -.. _ISSUE:Intel:Quartus: +.. _ISSUE/Altera/Quartus: +.. _ISSUE/Intel/Quartus: Altera Quartus-II / Intel Quartus Prime *************************************** @@ -99,7 +99,7 @@ Altera Quartus-II / Intel Quartus Prime * Generic types of type strings filled with NUL -.. _ISSUE:GHDL: +.. _ISSUE/GHDL: GHDL **** @@ -107,7 +107,7 @@ GHDL * Aliases to protected type methods -.. _ISSUE:Xilinx:ISE: +.. _ISSUE/Xilinx/ISE: Xilinx ISE ********** @@ -115,7 +115,7 @@ Xilinx ISE * Shared Variables in Simulation (VHDL-93) -.. _ISSUE:Xilinx:Vivado: +.. _ISSUE/Xilinx/Vivado: Xilinx Vivado ************* diff --git a/docs/UsingPoC/AddingIPCores.rst b/docs/UsingPoC/AddingIPCores.rst index 45a3ae661..04e1b67cf 100644 --- a/docs/UsingPoC/AddingIPCores.rst +++ b/docs/UsingPoC/AddingIPCores.rst @@ -1,4 +1,4 @@ -.. _USING:AddIP: +.. _USING/AddIP: Adding IP Cores to a Project ############################ diff --git a/docs/UsingPoC/Download.rst b/docs/UsingPoC/Download.rst index 4f4d9c316..aba43760c 100644 --- a/docs/UsingPoC/Download.rst +++ b/docs/UsingPoC/Download.rst @@ -1,4 +1,4 @@ -.. _USING:Download: +.. _USING/Download: Downloading PoC ############### @@ -7,7 +7,7 @@ Downloading PoC :local: -.. _USING:Zip: +.. _USING/Zip: Downloading from GitHub *********************** @@ -33,7 +33,7 @@ table, to choose your desired git branch. +----------+------------------------+ -.. _USING:GitClone: +.. _USING/GitClone: Downloading via ``git clone`` ***************************** @@ -93,7 +93,7 @@ On Windows All Windows command line instructions are intended for :program:`Windows PowerShell`, if not marked otherwise. So executing the following instructions in Windows Command Prompt (:program:`cmd.exe`) won't function or result in errors! See - the :ref:`Requirements section ` on where to + the :ref:`Requirements section ` on where to download or update PowerShell. Command line instructions to clone the PoC-Library onto a Windows machine with @@ -124,7 +124,7 @@ SSH protocol: needed anymore. -.. _USING:GitSubmodule: +.. _USING/GitSubmodule: Downloading via ``git submodule add`` ************************************* @@ -182,7 +182,7 @@ On Windows All Windows command line instructions are intended for :program:`Windows PowerShell`, if not marked otherwise. So executing the following instructions in Windows Command Prompt (:program:`cmd.exe`) won't function or result in errors! See - the :ref:`Requirements section ` on where to + the :ref:`Requirements section ` on where to download or update PowerShell. Command line instructions to clone the PoC-Library onto a Windows machine with diff --git a/docs/UsingPoC/Integration.rst b/docs/UsingPoC/Integration.rst index b5f9089ec..360eaed35 100644 --- a/docs/UsingPoC/Integration.rst +++ b/docs/UsingPoC/Integration.rst @@ -1,4 +1,4 @@ -.. _USING:Integration: +.. _USING/Integration: Integrating PoC into Projects ############################# @@ -8,7 +8,7 @@ Integrating PoC into Projects :depth: 2 -.. _USING:Integration:GitSubmodule: +.. _USING/Integration/GitSubmodule: As a Git submodule ****************** diff --git a/docs/UsingPoC/PoCConfiguration.rst b/docs/UsingPoC/PoCConfiguration.rst index 7c09d8cf5..993780c41 100644 --- a/docs/UsingPoC/PoCConfiguration.rst +++ b/docs/UsingPoC/PoCConfiguration.rst @@ -1,4 +1,4 @@ -.. _USING:PoCConfig: +.. _USING/PoCConfig: .. raw:: html @@ -49,7 +49,7 @@ at any time, for example to register new tools or to update tool versions. :depth: 2 -.. _USING:PoCConf:Over: +.. _USING/PoCConf/Over: Overview ======== @@ -113,7 +113,7 @@ Please see the Linux instructions. Installation directory: D:\git\PoC (found in environment variable) -.. _USING:PoCConf:PoC: +.. _USING/PoCConf/PoC: The PoC-Library =============== @@ -129,7 +129,7 @@ by ``PoC.ps1`` or ``poc.sh``. Installation directory: D:\git\PoC (found in environment variable) -.. _USING:PoCConf:Git: +.. _USING/PoCConf/Git: Git === @@ -149,7 +149,7 @@ Git Setting 'pre-commit' hook for PoC... -.. _USING:PoCConf:Aldec: +.. _USING/PoCConf/Aldec: Aldec ===== @@ -171,7 +171,7 @@ Active-HDL Aldec Active-HDL installation directory [C:\Aldec\Active-HDL]: C:\Aldec\Active-HDL-Student-Edition -.. _USING:PoCConf:Altera: +.. _USING/PoCConf/Altera: Altera ====== @@ -201,7 +201,7 @@ ModelSim Altera Edition ModelSim Altera Edition installation directory [C:\Altera\15.0\modelsim_ae]: C:\Altera\16.0\modelsim_ase -.. _USING:PoCConf:Lattice: +.. _USING/PoCConf/Lattice: Lattice ======== @@ -232,7 +232,7 @@ Active-HDL Lattice Edition Active-HDL Lattice Edition installation directory [D:\Lattice\Diamond\3.7_x64\active-hdl]: -.. _USING:PoCConf:Mentor: +.. _USING/PoCConf/Mentor: Mentor Graphics =============== @@ -254,7 +254,7 @@ QuestaSim Mentor QuestaSim installation directory [C:\Mentor\QuestaSim\10.4c]: C:\Mentor\QuestaSim64\10.4c -.. _USING:PoCConf:Xilinx: +.. _USING/PoCConf/Xilinx: Xilinx ====== @@ -283,7 +283,7 @@ answer the following questions: Vivado ------ -If an Xilinx ISE environment is available and shall be configured in PoC, then +If an Xilinx Vivado environment is available and shall be configured in PoC, then answer the following questions: .. code-block:: none @@ -294,7 +294,7 @@ answer the following questions: Xilinx Vivado installation directory [C:\Xilinx\Vivado\2016.2]: -.. _USING:PoCConf:GHDL: +.. _USING/PoCConf/GHDL: GHDL ==== @@ -305,7 +305,7 @@ GHDL GHDL installation directory [C:\Tools\GHDL\0.34dev]: -.. _USING:PoCConf:GTKWave: +.. _USING/PoCConf/GTKWave: GTKWave ======== @@ -316,7 +316,7 @@ GTKWave GTKWave installation directory [C:\Tools\GTKWave\3.3.71]: -.. _USING:PoCConf:HookFiles: +.. _USING/PoCConf/HookFiles: Hook Files ========== diff --git a/docs/UsingPoC/PrecompilingVendorLibraries.rst b/docs/UsingPoC/PrecompilingVendorLibraries.rst index b4e4f7760..35593b702 100644 --- a/docs/UsingPoC/PrecompilingVendorLibraries.rst +++ b/docs/UsingPoC/PrecompilingVendorLibraries.rst @@ -1,4 +1,4 @@ -.. _USING:PreCompile: +.. _USING/PreCompile: Pre-Compiling Vendor Libraries ############################## @@ -12,7 +12,7 @@ Pre-Compiling Vendor Libraries .. index:: single: Pre-compilation -.. _USING:PreCompile:Over: +.. _USING/PreCompile/Over: Overview ******** @@ -33,7 +33,7 @@ are located in ``\tools\precompile\`` and the output is stored in .. index:: pair: Pre-compilation; Supported Simulators -.. _USING:PreCompile:Simulators: +.. _USING/PreCompile/Simulators: Supported Simulators ******************** @@ -48,7 +48,7 @@ The current set of pre-compile scripts support these simulators: +------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ | Aldec |br| | Active-HDL (or Stududent Ed.) |br| | planned |br| | planned |br| | planned |br| | planned |br| | | |br| | Active-HDL Lattice Ed. |br| | planned |br| | shipped |br| | planned |br| | planned |br| | -| | Reviera-PRO | planned | planned | planned | planned | +| | Riviera-PRO | planned | planned | planned | planned | +------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ | Mentor |br| | ModelSim PE (or Stududent Ed.) |br| | yes |br| | yes |br| | yes |br| | yes |br| | | |br| | ModelSim SE |br| | yes |br| | yes |br| | yes |br| | yes |br| | @@ -63,7 +63,7 @@ The current set of pre-compile scripts support these simulators: .. index:: pair: Pre-compilation; Vendor Primitives -.. _USING:PreCompile:Primitives: +.. _USING/PreCompile/Primitives: FPGA Vendor's Primitive Libraries **************************************************************************************************************************************************************** @@ -72,14 +72,14 @@ FPGA Vendor's Primitive Libraries .. index:: pair: Pre-compilation; Altera -.. _USING:PreCompile:Primitives:Altera: +.. _USING/PreCompile/Primitives/Altera: Altera ====== .. note:: The Altera Quartus tool chain needs to be configured in PoC. |br| - See :ref:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -168,14 +168,14 @@ On Windows .. index:: pair: Pre-compilation; Lattice -.. _USING:PreCompile:Primitives:Lattice: +.. _USING/PreCompile/Primitives/Lattice: Lattice ======== .. note:: The Lattice Diamond tool chain needs to be configured in PoC. |br| - See :ref:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -360,14 +360,14 @@ On Windows .. index:: pair: Pre-compilation; Xilinx Vivado -.. _USING:PreCompile:Primitives:XilinxVivado +.. _USING/PreCompile/Primitives:XilinxVivado Xilinx Vivado ============= .. note:: The Xilinx Vivado tool chain needs to be configured in PoC. |br| - See :ref:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -456,7 +456,7 @@ On Windows .. index:: pair: Pre-compilation; Third-Party Libraries -.. _USING:PreCompile:ThirdParty: +.. _USING/PreCompile/ThirdParty: Third-Party Libraries **************************************************************************************************************************************************************** @@ -465,7 +465,7 @@ Third-Party Libraries .. index:: pair: Pre-compilation; OSVVM -.. _USING:PreCompile:ThirdParty:OSVVM: +.. _USING/PreCompile/ThirdParty/OSVVM: OSVVM ===== @@ -545,7 +545,7 @@ On Windows .. index:: pair: Pre-compilation; UVVM -.. _USING:PreCompile:ThirdParty:UVVM: +.. _USING/PreCompile/ThirdParty/UVVM: UVVM ==== @@ -625,7 +625,7 @@ On Windows .. index:: pair: Pre-compilation; VUnit - .. _USING:PreCompile:ThirdParty:VUnit: + .. _USING/PreCompile/ThirdParty/VUnit: VUnit ===== @@ -705,7 +705,7 @@ On Windows .. index:: pair: Pre-compilation; Simulator Adapters -.. _USING:PreCompile:Adapter: +.. _USING/PreCompile/Adapter: Simulator Adapters **************************************************************************************************************************************************************** @@ -713,7 +713,7 @@ Simulator Adapters .. index:: pair: Pre-compilation; Cocotb -.. _USING:PreCompile:Adapter:Cocotb: +.. _USING/PreCompile/Adapter/Cocotb: Cocotb ====== diff --git a/docs/UsingPoC/ProjectManagement.rst b/docs/UsingPoC/ProjectManagement.rst index bff3930a5..11871dbe3 100644 --- a/docs/UsingPoC/ProjectManagement.rst +++ b/docs/UsingPoC/ProjectManagement.rst @@ -1,4 +1,4 @@ -.. _USING:Project: +.. _USING/Project: Project Management ################## diff --git a/docs/UsingPoC/Requirements.rst b/docs/UsingPoC/Requirements.rst index 9691c9dd6..c7d59dca5 100644 --- a/docs/UsingPoC/Requirements.rst +++ b/docs/UsingPoC/Requirements.rst @@ -1,4 +1,4 @@ -.. _USING:Require: +.. _USING/Require: Requirements ############ @@ -12,7 +12,7 @@ platform independent scripting environment. All Python scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. -.. _USING:Require:Common: +.. _USING/Require/Common: Common requirements: ******************** @@ -41,10 +41,10 @@ Simulation tool chains * Mentor Graphics QuestaSim or * Xilinx ISE Simulator 14.7 or * Xilinx Vivado Simulator |geq| 2016.3 [#f3]_ or - * `GHDL `_ |geq| 0.34dev and `GTKWave `_ |geq| 3.3.70 + * `GHDL `_ |geq| 5.1.1 and `GTKWave `_ |geq| 3.3.70 -.. _USING:Require:Linux: +.. _USING/Require/Linux: Linux specific requirements: **************************** @@ -67,7 +67,7 @@ SmartGit The latest *.deb installation packages can be downloaded `here `_. -.. _USING:Require:MacOS: +.. _USING/Require/MacOS: Mac OS specific requirements: ***************************** @@ -94,7 +94,7 @@ SmartGit or SourceTree ``brew install Grc`` -.. _USING:Require:Windows: +.. _USING/Require/Windows: Windows specific requirements: ****************************** diff --git a/docs/UsingPoC/Simulation.rst b/docs/UsingPoC/Simulation.rst index 9a1c1fcfc..101f5cdad 100644 --- a/docs/UsingPoC/Simulation.rst +++ b/docs/UsingPoC/Simulation.rst @@ -1,4 +1,4 @@ -.. _USING:Sim: +.. _USING/Sim: Simulation ########## @@ -7,7 +7,7 @@ Simulation :local: -.. _USING:Sim:Over: +.. _USING/Sim/Over: Overview ******** @@ -37,7 +37,7 @@ frontend script: See the Intruction page for a list of supported simulators. -.. _USING:Sim:Quick: +.. _USING/Sim/Quick: Quick Example ************* @@ -91,7 +91,7 @@ The opened waveform viewer and displayed waveform should look like this: :alt: GTKWave waveform view of PoC.arith.prng. -.. _USING:Sim:Vendor: +.. _USING/Sim/Vendor: Vendor Specific Testbenches *************************** @@ -136,7 +136,7 @@ A vendor specific testbench can be launched by passing either ``--board=xxx`` or :doc:`Pre-Compiling Vendor Libraries `. -.. _USING:Sim:Single: +.. _USING/Sim/Single: Running a Single Testbench ************************** @@ -190,7 +190,7 @@ PoC runs multiple testbenches at once, all finished testbenches are reported wit there testbench result. The aborted testbench will be listed as errored. -.. _USING:Sim:Aldec-ActiveHDL: +.. _USING/Sim:Aldec-ActiveHDL: Aldec Active-HDL ================ @@ -219,7 +219,7 @@ PoC entities. The following options are supported for Active-HDL: .\poc.ps1 asim PoC.arith.prng --std=93 -.. _USING:Sim:Cocotb: +.. _USING/Sim/Cocotb: Cocotb with QuestaSim backend ============================= @@ -249,7 +249,7 @@ by a list of PoC entities. The following options are supported for Cocotb: .\poc.ps1 cocotb PoC.cache.par -.. _USING:Sim:GHDL: +.. _USING/Sim/GHDL: GHDL (plus GTKwave) =================== @@ -277,7 +277,7 @@ PoC entities. The following options are supported for GHDL: .\poc.ps1 ghdl PoC.arith.prng --board=Atlys -g -.. _USING:Sim:Mentor-QuestaSim: +.. _USING/Sim:Mentor-QuestaSim: Mentor Graphics QuestaSim ========================= @@ -377,7 +377,7 @@ Vivado Simulator: .\poc.ps1 xsim PoC.arith.prng --board=Atlys -g -.. _USING:Sim:Group: +.. _USING/Sim/Group: Running a Group of Testbenches ****************************** @@ -417,7 +417,7 @@ current namespace and all sub-namespaces. :alt: Report after running multiple testbenches in Active-HDL. -.. _USING:Sim:CI: +.. _USING/Sim/CI: Continuous Integration (CI) *************************** diff --git a/docs/UsingPoC/Synthesis.rst b/docs/UsingPoC/Synthesis.rst index 527cb89c0..19c5daa05 100644 --- a/docs/UsingPoC/Synthesis.rst +++ b/docs/UsingPoC/Synthesis.rst @@ -1,4 +1,4 @@ -.. _USING:Synth: +.. _USING/Synth: Synthesis ######### @@ -7,7 +7,7 @@ Synthesis :local: -.. _USING:Synth:Over: +.. _USING/Synth/Over: Overview ******** @@ -28,10 +28,10 @@ one of PoC's frontend script: .. seealso:: - :ref:`PoC Configuration ` + :ref:`PoC Configuration ` See the Configuration page on how to configure PoC and your installed synthesis tool chains. This is required to invoke the compilers. - :ref:`Supported Compiler ` + :ref:`Supported Compiler ` See the Intruction page for a list of supported compilers. @@ -42,7 +42,7 @@ one of PoC's frontend script: See this list to find a supported and well known development board. -.. _USING:Synth:Quick: +.. _USING/Synth/Quick: Quick Example ************* @@ -71,12 +71,12 @@ synthesized to a netlist. :alt: PowerShell console output after running PoC.arith.prng with XST. -.. _USING:Synth:Single: +.. _USING/Synth/Single: Running a single Synthesis ************************** -A synthesis run is supervised by PoC's :ref:`PoCRoot\\py\\PoC.py ` +A synthesis run is supervised by PoC's :ref:`PoCRoot\\py\\PoC.py ` service tool, which offers a consistent interface to all synthesizers. Unfortunately, every platform has it's specialties, so a wrapper script is needed as abstraction from the host's operating system. Depending on the choosen @@ -139,7 +139,7 @@ configured in PoC: +---------------------------------+--------------------------------------------+ -.. _USING:Synth:Altera-Quartus: +.. _USING/Synth:Altera-Quartus: Altera / Intel Quartus ====================== @@ -167,7 +167,7 @@ supported for Quartus: .\poc.ps1 quartus PoC.arith.prng --board=DE4 -.. _USING:Synth:Lattice-Diamond: +.. _USING/Synth:Lattice-Diamond: Lattice Diamond =============== @@ -195,7 +195,7 @@ Synthesis Engine (LSE): .\poc.ps1 lse PoC.arith.prng --board=ECP5Versa -.. _USING:Synth:Xilinx-ISE: +.. _USING/Synth:Xilinx-ISE: Xilinx ISE Synthesis Tool (XST) =============================== @@ -223,7 +223,7 @@ Synthesis Tool (XST): .\poc.ps1 xst PoC.arith.prng --board=KC705 -.. _USING:Synth:Xilinx-CoreGen: +.. _USING/Synth:Xilinx-CoreGen: Xilinx ISE Core Generator ========================= @@ -251,7 +251,7 @@ supported for Core Generator (CG): .\poc.ps1 coregen PoC.xil.mig.Atlys_1x128 --board=Atlys -.. _USING:Synth:Xilinx-Vivado: +.. _USING/Synth:Xilinx-Vivado: Xilinx Vivado Synthesis ======================= diff --git a/docs/UsingPoC/VHDLConfiguration.rst b/docs/UsingPoC/VHDLConfiguration.rst index f4bc72708..17388fdfa 100644 --- a/docs/UsingPoC/VHDLConfiguration.rst +++ b/docs/UsingPoC/VHDLConfiguration.rst @@ -1,4 +1,4 @@ -.. _USING:VHDLConf: +.. _USING/VHDLConf: Creating my_config/my_project.vhdl ################################## @@ -9,7 +9,7 @@ platform information. These files are also used to select appropiate work arounds. -.. _USING:VHDLConf:myconfig: +.. _USING/VHDLConf/myconfig: Create my_config.vhdl ********************* @@ -50,7 +50,7 @@ If the requested board is not known to PoC or it's custom made, then set constant MY_DEVICE : string := "XC6SLX45-3CSG324"; -.. _USING:VHDLConf:myproject: +.. _USING/VHDLConf/myproject: Create my_project.vhdl ********************** diff --git a/docs/UsingPoC/index.rst b/docs/UsingPoC/index.rst index 192719fb7..14805e3d8 100644 --- a/docs/UsingPoC/index.rst +++ b/docs/UsingPoC/index.rst @@ -3,7 +3,7 @@ Using PoC ######### -PoC can be used in several ways, if all :ref:`Requirements ` +PoC can be used in several ways, if all :ref:`Requirements ` are fulfilled. Chose one of the following integration kinds: * Stand-Alone IP Core Library: @@ -26,8 +26,8 @@ are fulfilled. Chose one of the following integration kinds: * No possibility to contribute bugfixes and extensions via Git pull requests. **Next steps:** |br| - 1. See :ref:`Downloads ` for how to download a stand-alone version (*.zip-file) of the PoC-Library. |br| - 2. See :ref:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Downloads ` for how to download a stand-alone version (*.zip-file) of the PoC-Library. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. * Stand-Alone IP Core Library cloned from Git: Download PoC via ``git clone`` from GitHub as latest branch copy. IP cores @@ -49,8 +49,8 @@ are fulfilled. Chose one of the following integration kinds: * Using different PoC versions in different projects is not possible **Next steps:** |br| - 1. See :ref:`Downloads ` for how to clone a stand-alone version of the PoC-Library. |br| - 2. See :ref:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Downloads ` for how to clone a stand-alone version of the PoC-Library. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. * Embedded IP Core Library as Git Submodule: Integrate PoC as a Git submodule into the destination projects Git repository. @@ -68,8 +68,8 @@ are fulfilled. Chose one of the following integration kinds: * Version linking between hosting Git and PoC. **Next steps:** |br| - 1. See :ref:`Integration ` for how to integrate PoC as a Git submodule into an existing Git. |br| - 2. See :ref:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Integration ` for how to integrate PoC as a Git submodule into an existing Git. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. .. toctree:: diff --git a/docs/WhatIsPoC/SupportedToolChains.rst b/docs/WhatIsPoC/SupportedToolChains.rst index 2af2d7da0..8a869c104 100644 --- a/docs/WhatIsPoC/SupportedToolChains.rst +++ b/docs/WhatIsPoC/SupportedToolChains.rst @@ -1,4 +1,4 @@ -.. _INTRO:ToolChains: +.. _INTRO/ToolChains: Which Tool Chains are supported? ################################ From 357c5eee8916982d678d4805e27d240be87cbb43 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 13 Oct 2025 16:05:06 +0200 Subject: [PATCH 02/56] Removed more ISE related documentation content. --- docs/ConstraintFiles/Altera/index.rst | 7 -- docs/ConstraintFiles/Xilinx/index.rst | 15 --- docs/ConstraintFiles/index.rst | 6 -- docs/IPCores/xil/mig/index.rst | 24 ----- docs/IPCores/xil/mig/mig_Atlys_1x128.rst | 20 ---- .../xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst | 21 ---- docs/IPCores/xil/xil_ChipScopeICON.rst | 56 ----------- docs/UsingPoC/AddingIPCores.rst | 5 - docs/UsingPoC/PoCConfiguration.rst | 10 -- docs/UsingPoC/PrecompilingVendorLibraries.rst | 98 +------------------ docs/UsingPoC/Requirements.rst | 3 - docs/UsingPoC/Simulation.rst | 31 +----- docs/UsingPoC/Synthesis.rst | 8 -- 13 files changed, 2 insertions(+), 302 deletions(-) delete mode 100644 docs/IPCores/xil/mig/index.rst delete mode 100644 docs/IPCores/xil/mig/mig_Atlys_1x128.rst delete mode 100644 docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst delete mode 100644 docs/IPCores/xil/xil_ChipScopeICON.rst diff --git a/docs/ConstraintFiles/Altera/index.rst b/docs/ConstraintFiles/Altera/index.rst index af7e06d73..4402ee8cb 100644 --- a/docs/ConstraintFiles/Altera/index.rst +++ b/docs/ConstraintFiles/Altera/index.rst @@ -2,17 +2,10 @@ Altera ###### - * Cyclone III - * DE0 - * DE0 nano - * Stratix IV - * DE4 * Stratix V * DE5 .. toctree:: :hidden: - CycloneIII/index - StratixIV/index StratixV/index diff --git a/docs/ConstraintFiles/Xilinx/index.rst b/docs/ConstraintFiles/Xilinx/index.rst index 27125f6c0..e696e3b11 100644 --- a/docs/ConstraintFiles/Xilinx/index.rst +++ b/docs/ConstraintFiles/Xilinx/index.rst @@ -2,21 +2,10 @@ Xilinx ###### - * Spartan-3 Boards - * Spartan-3 Starter Kit (S3SK) - * Spartan-3E Starter Kit (S3ESK) - * Spartan-6 Boards - * Atlys * Artix-7 * AC701 * Kintex-7 * KC705 - * Virtex-5 - * ML505 - * ML506 - * XUPV5 - * Virtex-6 - * ML605 * Virtex-7 * VC707 * Zynq-7000 @@ -26,11 +15,7 @@ Xilinx .. toctree:: :hidden: - Spartan3/index - Spartan6/index Artix7/index Kintex7/index - Virtex5/index - Virtex6/index Virtex7/index Zynq7000/index diff --git a/docs/ConstraintFiles/index.rst b/docs/ConstraintFiles/index.rst index 0f320f7a8..24789bbd9 100644 --- a/docs/ConstraintFiles/index.rst +++ b/docs/ConstraintFiles/index.rst @@ -26,8 +26,6 @@ Board Constraint Files * Altera Boards - * Cyclone III - * Stratix IV * Stratix V * Lattice Boards @@ -35,10 +33,6 @@ Board Constraint Files * Artix-7 * Kintex-7 - * Spartan-3 Boards - * Spartan-6 Boards - * Virtex-5 - * Virtex-6 * Virtex-7 * Zynq-7000 diff --git a/docs/IPCores/xil/mig/index.rst b/docs/IPCores/xil/mig/index.rst deleted file mode 100644 index bd2d99615..000000000 --- a/docs/IPCores/xil/mig/index.rst +++ /dev/null @@ -1,24 +0,0 @@ -.. _NS:mig: - -PoC.xil.mig -=========== - -The namespace ``PoC.xil.mig`` offers pre-configured memory controllers generated -with Xilinx's Memory Interface Generator (MIG). - -* **for Spartan-6 boards:** - - * :ref:`mig_Atlys_1x128 ` - A DDR2 memory controller for the Digilent Atlys board. - -* **for Kintex-7 boards:** - - * :ref:`mig_KC705_MT8JTF12864HZ_1G6 ` - A DDR3 memory controller for the Xilinx KC705 board. - -* **for Virtex-7 boards:** - - -.. toctree:: - :hidden: - - mig_Atlys_1x128 - mig_KC705_MT8JTF12864HZ_1G6 diff --git a/docs/IPCores/xil/mig/mig_Atlys_1x128.rst b/docs/IPCores/xil/mig/mig_Atlys_1x128.rst deleted file mode 100644 index 5acdcb4e5..000000000 --- a/docs/IPCores/xil/mig/mig_Atlys_1x128.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. _IP:mig_Atlys_1x128: - -mig_Atlys_1x128 -############### - -This DDR2 memory controller is pre-configured for the Digilent Atlys development -board. The board is equipped with a single 1 GiBit DDR2 memory chip (128 MiByte) -from MIRA (MIRA P3R1GE3EGF G8E DDR2). - -Run the following two steps to create the IP core: - -1. Generate the source files from the IP core using Xilinx MIG and afterwards patch them |br| - ``PS> .\poc.ps1 coregen PoC.xil.mig.Atlys_1x128 --board=Atlys`` - -2. Compile the patched sources into a ready to use netlist (\*.ngc) and constraint file (\*.ucf) |br| - ``PS> .\poc.ps1 xst PoC.xil.mig.Atlys_1x128 --board=Atlys`` - -.. seealso:: - :doc:`Using PoC -> Synthesis ` - For how to run Core Generator and XST from PoC. diff --git a/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst b/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst deleted file mode 100644 index 75f7caf44..000000000 --- a/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst +++ /dev/null @@ -1,21 +0,0 @@ -.. _IP:mig_KC705_MT8JTF12864HZ_1G6: - -mig_KC705_MT8JTF12864HZ_1G6 -########################### - -This DDR2 memory controller is pre-configured for the Xilinx KC705 development -board. The board is equipped with a single 1 GiBit DDR3 memory chip (128 MiByte) -from Micron Technology (MT8JTF12864HZ-1G6G1). - -Run the following two steps to create the IP core: - -1. Generate the source files from the IP core using Xilinx MIG and afterwards patch them |br| - ``PS> .\poc.ps1 coregen PoC.xil.mig.KC705_MT8JTF12864HZ_1G6 --board=KC705`` - -2. Compile the patched sources into a ready to use netlist (\*.ngc) and constraint file (\*.ucf) |br| - ``PS> .\poc.ps1 xst PoC.xil.mig.KC705_MT8JTF12864HZ_1G6 --board=KC705`` - -.. seealso:: - :doc:`Using PoC -> Synthesis ` - For how to run Core Generator and XST from PoC. - diff --git a/docs/IPCores/xil/xil_ChipScopeICON.rst b/docs/IPCores/xil/xil_ChipScopeICON.rst deleted file mode 100644 index 924e05616..000000000 --- a/docs/IPCores/xil/xil_ChipScopeICON.rst +++ /dev/null @@ -1,56 +0,0 @@ -.. _IP:xil_ChipScopeICON: - -PoC.xil.ChipScopeICON -##################### - -.. only:: html - - .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ChipScopeICON.vhdl - :alt: Source Code on GitHub - .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ChipScopeICON_tb.vhdl - :alt: Source Code on GitHub - - .. sidebar:: GitHub Links - - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` - -This module wraps 15 ChipScope ICON IP core netlists generated from ChipScope -ICON xco files. The generic parameter ``PORTS`` selects the apropriate ICON -instance with 1 to 15 ICON ``ControlBus`` ports. Each ``ControlBus`` port is -of type ``T_XIL_CHIPSCOPE_CONTROL`` and of mode ``inout``. - -.. rubric:: Compile required CoreGenerator IP Cores to Netlists with PoC - -Please use the provided Xilinx ISE compile command ``ise`` in PoC to recreate -the needed source and netlist files on your local machine. - -.. code-block:: PowerShell - - cd PoCRoot - .\poc.ps1 ise PoC.xil.ChipScopeICON --board=KC705 - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_ChipScopeICON.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 56-63 - -.. seealso:: - - :doc:`Using PoC -> Synthesis ` - For how to run synthesis with PoC and CoreGenerator. - - - -.. only:: latex - - Source file: :pocsrc:`xil/xil_ChipScopeICON.vhdl ` diff --git a/docs/UsingPoC/AddingIPCores.rst b/docs/UsingPoC/AddingIPCores.rst index 04e1b67cf..b6b0941f5 100644 --- a/docs/UsingPoC/AddingIPCores.rst +++ b/docs/UsingPoC/AddingIPCores.rst @@ -16,11 +16,6 @@ Adding IP Cores to Lattice Diamond .. TODO:: No documentation available. -Adding IP Cores to Xilinx ISE -============================= - -.. TODO:: No documentation available. - Adding IP Cores to Xilinx Vivado ================================ diff --git a/docs/UsingPoC/PoCConfiguration.rst b/docs/UsingPoC/PoCConfiguration.rst index 993780c41..2fa7340a2 100644 --- a/docs/UsingPoC/PoCConfiguration.rst +++ b/docs/UsingPoC/PoCConfiguration.rst @@ -270,16 +270,6 @@ Configure the installation directory for all Xilinx tools. Are Xilinx products installed on your system? [Y/n/p]: Y Xilinx installation directory [C:\Xilinx]: -ISE ---- -If an Xilinx ISE environment is available and shall be configured in PoC, then -answer the following questions: - -.. code-block:: none - - Configuring Xilinx ISE - Is Xilinx ISE installed on your system? [Y/n/p]: Y - Xilinx ISE installation directory [C:\Xilinx\14.7\ISE_DS]: Vivado ------ diff --git a/docs/UsingPoC/PrecompilingVendorLibraries.rst b/docs/UsingPoC/PrecompilingVendorLibraries.rst index 35593b702..54d930640 100644 --- a/docs/UsingPoC/PrecompilingVendorLibraries.rst +++ b/docs/UsingPoC/PrecompilingVendorLibraries.rst @@ -55,8 +55,7 @@ The current set of pre-compile scripts support these simulators: | |br| | ModelSim Altera Ed. |br| | shipped |br| | yes |br| | yes |br| | yes |br| | | | QuestaSim | yes | yes | yes | yes | +------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ -| Xilinx |br| | ISE Simulator |br| | | | shipped |br| | not supported |br| | -| | Vivado Simulator | | | not supported | shipped | +| Xilinx |br| | Vivado Simulator | | | not supported | shipped | +------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ @@ -260,101 +259,6 @@ On Windows | | |c-lattice-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | +-------------------+------------------------+-------------------------------------------------------------------------+ -.. # =========================================================================================================================================================== -.. index:: - pair: Pre-compilation; Xilinx ISE - -.. _USING:PreCompile:Primitives:XilinxISE: - -Xilinx ISE -========== - -.. note:: - The Xilinx ISE tool chain needs to be configured in PoC. |br| - See :ref:`Configuring PoC's Infrastruture ` for further details. - -On Linux --------- - -.. code-block:: Bash - - # Example 1 - Compile for all Simulators - ./tools/precompile/compile-xilinx-ise.sh --all - # Example 2 - Compile only for GHDL and VHDL-2008 - ./tools/precompile/compile-xilinx-ise.sh --ghdl --vhdl2008 - -**List of command line arguments:** - -.. |c-ise-sh-h| replace:: :option:`-h ` -.. |c-ise-sh-c| replace:: :option:`-c ` -.. |c-ise-sh-a| replace:: :option:`-a ` -.. |c-ise-sh-help| replace:: :option:`--help ` -.. |c-ise-sh-clean| replace:: :option:`--clean ` -.. |c-ise-sh-all| replace:: :option:`--all ` -.. |c-ise-sh-ghdl| replace:: :option:`--ghdl ` -.. |c-ise-sh-questa| replace:: :option:`--questa ` -.. |c-ise-sh-vhdl93| replace:: :option:`--vhdl93 ` -.. |c-ise-sh-vhdl08| replace:: :option:`--vhdl2008 ` - -+------------------------------------+---------------------------------------------------------------------------------+ -| Common Option | Parameter Description | -+===============+====================+=================================================================================+ -| |c-ise-sh-h| | |c-ise-sh-help| | Print embedded help page(s). | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| |c-ise-sh-c| | |c-ise-sh-clean| | Clean-up directories. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| |c-ise-sh-a| | |c-ise-sh-all| | Compile for all simulators. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| | |c-ise-sh-ghdl| | Compile for GHDL. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| | |c-ise-sh-questa| | Compile for QuestaSim. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| | |c-ise-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| | |c-ise-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | -+---------------+--------------------+---------------------------------------------------------------------------------+ - - -On Windows ----------- - -.. code-block:: PowerShell - - # Example 1 - Compile for all Simulators - .\tools\precompile\compile-xilinx-ise.ps1 -All - # Example 2 - Compile only for GHDL and VHDL-2008 - .\tools\precompile\compile-xilinx-ise.ps1 -GHDL -VHDL2008 - -**List of command line arguments:** - -.. |c-ise-ps-h| replace:: ``-h`` -.. |c-ise-ps-c| replace:: ``-c`` -.. |c-ise-ps-a| replace:: ``-a`` -.. |c-ise-ps-help| replace:: :option:`-Help ` -.. |c-ise-ps-clean| replace:: :option:`-Clean ` -.. |c-ise-ps-all| replace:: :option:`-All ` -.. |c-ise-ps-ghdl| replace:: :option:`-GHDL ` -.. |c-ise-ps-questa| replace:: :option:`-Questa ` -.. |c-ise-ps-vhdl93| replace:: :option:`-VHDL93 ` -.. |c-ise-ps-vhdl08| replace:: :option:`-VHDL2008 ` - -+------------------------------------+---------------------------------------------------------------------------------+ -| Common Option | Parameter Description | -+===============+====================+=================================================================================+ -| |c-ise-ps-h| | |c-ise-ps-help| | Print embedded help page(s). | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| |c-ise-ps-c| | |c-ise-ps-clean| | Clean-up directories. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| |c-ise-ps-a| | |c-ise-ps-all| | Compile for all simulators. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| | |c-ise-ps-ghdl| | Compile for GHDL. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| | |c-ise-ps-questa| | Compile for QuestaSim. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| | |c-ise-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | -+---------------+--------------------+---------------------------------------------------------------------------------+ -| | |c-ise-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | -+---------------+--------------------+---------------------------------------------------------------------------------+ .. # =========================================================================================================================================================== .. index:: diff --git a/docs/UsingPoC/Requirements.rst b/docs/UsingPoC/Requirements.rst index c7d59dca5..b2a9b58da 100644 --- a/docs/UsingPoC/Requirements.rst +++ b/docs/UsingPoC/Requirements.rst @@ -26,11 +26,9 @@ Programming Languages and Runtime Environments: All Python requirements are listed in `requirements.txt `_ and can be installed via: |br| ``sudo python3.5 -m pip install -r requirements.txt`` Synthesis tool chains: - * Altera Quartus II |geq| 13.0 or * Altera Quartus Prime |geq| 15.1 or * Intel Quartus Prime |geq| 16.1 or * Lattice Diamond |geq| 3.6 or - * Xilinx ISE 14.7 [#f1]_ or * Xilinx Vivado |geq| 2016.3 [#f2]_ Simulation tool chains * Aldec Active-HDL (or Student Edition) or @@ -39,7 +37,6 @@ Simulation tool chains * Mentor Graphics ModelSim SE or * Mentor Graphics ModelSim Altera Edition or * Mentor Graphics QuestaSim or - * Xilinx ISE Simulator 14.7 or * Xilinx Vivado Simulator |geq| 2016.3 [#f3]_ or * `GHDL `_ |geq| 5.1.1 and `GTKWave `_ |geq| 3.3.70 diff --git a/docs/UsingPoC/Simulation.rst b/docs/UsingPoC/Simulation.rst index 101f5cdad..4f780b4c8 100644 --- a/docs/UsingPoC/Simulation.rst +++ b/docs/UsingPoC/Simulation.rst @@ -177,8 +177,6 @@ configured in PoC: +-----------+---------------------------------------------+ | ghdl | GHDL Simulator | +-----------+---------------------------------------------+ -| isim | Xilinx ISE Simulator | -+-----------+---------------------------------------------+ | vsim | QuestaSim Simulator or ModelSim | +-----------+---------------------------------------------+ | xsim | Xilinx Vivado Simulator | @@ -321,34 +319,7 @@ IP core's run script, which may default to ``run -all``. +--------------------------+---------------------------------------------------------+ -.. _USING:Sim:Xilinx-iSim: - -Xilinx ISE Simulator -==================== - -The command to invoke a simulation using ISE Simulator (isim) is ``isim`` -followed by a list of PoC entities. The following options are supported for -ISE Simulator: - -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ -| -g | --gui | Start the simulation in the ISE Simulator GUI (iSim). | -+----+---------------------+---------------------------------------------------------+ - -.. rubric:: Example: - -.. code-block:: PowerShell - - cd PoCRoot - .\poc.ps1 isim PoC.arith.prng --board=Atlys -g - - -.. _USING:Sim:Xilinx-xSim: +.. _USING/Sim:Xilinx-xSim: Xilinx Vivado Simulator ======================= diff --git a/docs/UsingPoC/Synthesis.rst b/docs/UsingPoC/Synthesis.rst index 19c5daa05..b68a448c2 100644 --- a/docs/UsingPoC/Synthesis.rst +++ b/docs/UsingPoC/Synthesis.rst @@ -117,10 +117,6 @@ configured in PoC: .. |r-quartus| replace:: :ref:`PoC.py quartus ` .. |l-lse| replace:: :ref:`Lattice (Diamond) Synthesis Engine (LSE) ` .. |r-lse| replace:: :ref:`PoC.py lse ` -.. |l-xst| replace:: :ref:`Xilinx ISE Systhesis Tool (XST) ` -.. |r-xst| replace:: :ref:`PoC.py xst ` -.. |l-coregen| replace:: :ref:`Xilinx ISE Core Generator (CoreGen) ` -.. |r-coregen| replace:: :ref:`PoC.py coregen ` .. |l-vivado| replace:: :ref:`Xilinx Vivado Synthesis ` .. |r-vivado| replace:: :ref:`PoC.py vivado ` @@ -131,10 +127,6 @@ configured in PoC: +---------------------------------+--------------------------------------------+ | |l-lse| | |r-lse| | +---------------------------------+--------------------------------------------+ -| |l-xst| | |r-xst| | -+---------------------------------+--------------------------------------------+ -| |l-coregen| | |r-coregen| | -+---------------------------------+--------------------------------------------+ | |l-vivado| | |r-vivado| | +---------------------------------+--------------------------------------------+ From 1ad437f67f09e27eaadcd0b492c80e328bec4168 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 13 Oct 2025 16:08:32 +0200 Subject: [PATCH 03/56] Fixed typo in GitHub Action pipeline. --- .github/workflows/Pipeline.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml index 10f90df9e..7282cb052 100644 --- a/.github/workflows/Pipeline.yml +++ b/.github/workflows/Pipeline.yml @@ -123,7 +123,7 @@ jobs: contents: write # required for create tag actions: write # required for trigger workflow with: - version: ${{ needs.Prepare.output.version }} + version: ${{ needs.Prepare.outputs.version }} auto_tag: ${{ needs.Prepare.outputs.is_release_commit }} Release: From e6b25a4bd7718c13aca2a811c13bf5b5b0f367b4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 13 Oct 2025 17:27:01 +0200 Subject: [PATCH 04/56] Fixed more documentation pages because sync.* was moved. --- docs/IPCores/arith/arith_muls_wide.rst | 40 ------------ docs/IPCores/bus/stream/index.rst | 2 +- docs/IPCores/bus/stream/stream_FIFO.rst | 18 +++--- docs/IPCores/fifo/fifo_dc_got_sm.rst | 61 ------------------- docs/IPCores/fifo/fifo_stage.rst | 18 +++--- docs/IPCores/fifo/index.rst | 6 +- docs/IPCores/index.rst | 1 + .../ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 60 ------------------ docs/IPCores/mem/ddr2/index.rst | 22 ------- .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 59 ------------------ docs/IPCores/mem/ddr3/index.rst | 22 ------- docs/IPCores/mem/index.rst | 4 -- docs/IPCores/misc/index.rst | 2 - docs/IPCores/net/net_FrameLoopback.rst | 2 +- docs/IPCores/{misc => }/sync/index.rst | 6 +- docs/IPCores/{misc => }/sync/sync.pkg.rst | 10 +-- docs/IPCores/{misc => }/sync/sync_Bits.rst | 24 ++++---- docs/IPCores/{misc => }/sync/sync_Command.rst | 16 ++--- docs/IPCores/{misc => }/sync/sync_Pulse.rst | 24 ++++---- docs/IPCores/{misc => }/sync/sync_Reset.rst | 16 ++--- docs/IPCores/{misc => }/sync/sync_Strobe.rst | 20 +++--- docs/IPCores/{misc => }/sync/sync_Vector.rst | 16 ++--- docs/IPCores/xil/index.rst | 1 - 23 files changed, 89 insertions(+), 361 deletions(-) delete mode 100644 docs/IPCores/arith/arith_muls_wide.rst delete mode 100644 docs/IPCores/fifo/fifo_dc_got_sm.rst delete mode 100644 docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst delete mode 100644 docs/IPCores/mem/ddr2/index.rst delete mode 100644 docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst delete mode 100644 docs/IPCores/mem/ddr3/index.rst rename docs/IPCores/{misc => }/sync/index.rst (97%) rename docs/IPCores/{misc => }/sync/sync.pkg.rst (57%) rename docs/IPCores/{misc => }/sync/sync_Bits.rst (70%) rename docs/IPCores/{misc => }/sync/sync_Command.rst (74%) rename docs/IPCores/{misc => }/sync/sync_Pulse.rst (70%) rename docs/IPCores/{misc => }/sync/sync_Reset.rst (77%) rename docs/IPCores/{misc => }/sync/sync_Strobe.rst (71%) rename docs/IPCores/{misc => }/sync/sync_Vector.rst (73%) diff --git a/docs/IPCores/arith/arith_muls_wide.rst b/docs/IPCores/arith/arith_muls_wide.rst deleted file mode 100644 index 11d78bef8..000000000 --- a/docs/IPCores/arith/arith_muls_wide.rst +++ /dev/null @@ -1,40 +0,0 @@ -.. _IP/arith_muls_wide: - -PoC.arith.muls_wide -################### - -.. only:: html - - .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_muls_wide.vhdl - :alt: Source Code on GitHub - .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_muls_wide_tb.vhdl - :alt: Source Code on GitHub - - .. sidebar:: GitHub Links - - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` - -Signed wide multiplication spanning multiple DSP or MULT blocks. -Small partial products are calculated through LUTs. -For detailed documentation see below. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_muls_wide.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 38-49 - - - -.. only:: latex - - Source file: :pocsrc:`arith/arith_muls_wide.vhdl ` diff --git a/docs/IPCores/bus/stream/index.rst b/docs/IPCores/bus/stream/index.rst index 53621f51a..d1bf1f255 100644 --- a/docs/IPCores/bus/stream/index.rst +++ b/docs/IPCores/bus/stream/index.rst @@ -13,7 +13,7 @@ PoC.Stream modules ... .. toctree:: :hidden: - stream_Buffer + stream_FIFO stream_DeMux stream_Mux stream_Mirror diff --git a/docs/IPCores/bus/stream/stream_FIFO.rst b/docs/IPCores/bus/stream/stream_FIFO.rst index 281afc289..48779a136 100644 --- a/docs/IPCores/bus/stream/stream_FIFO.rst +++ b/docs/IPCores/bus/stream/stream_FIFO.rst @@ -1,23 +1,23 @@ -.. _IP/stream_Buffer: +.. _IP/stream_FIFO: -PoC.bus.stream.Buffer -##################### +PoC.bus.stream.FIFO +################### .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Buffer.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_FIFO.vhdl :alt: Source Code on GitHub .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Buffer_tb.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_FIFO_tb.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module implements a generic buffer (FIFO) for the :doc:`PoC.Stream ` protocol. It is generic in @@ -28,7 +28,7 @@ meta information. .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/bus/stream/stream_Buffer.vhdl +.. literalinclude:: ../../../../src/bus/stream/stream_FIFO.vhdl :language: vhdl :tab-width: 2 :linenos: @@ -38,4 +38,4 @@ meta information. .. only:: latex - Source file: :pocsrc:`bus/stream/stream_Buffer.vhdl ` + Source file: :pocsrc:`bus/stream/stream_FIFO.vhdl ` diff --git a/docs/IPCores/fifo/fifo_dc_got_sm.rst b/docs/IPCores/fifo/fifo_dc_got_sm.rst deleted file mode 100644 index 10626bda9..000000000 --- a/docs/IPCores/fifo/fifo_dc_got_sm.rst +++ /dev/null @@ -1,61 +0,0 @@ -.. _IP/fifo_dc_got_sm: - -PoC.fifo.dc_got_sm -################## - -.. only:: html - - .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_dc_got_sm.vhdl - :alt: Source Code on GitHub - .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_dc_got_sm_tb.vhdl - :alt: Source Code on GitHub - - .. sidebar:: GitHub Links - - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` - -Dependent clocks meens, that one clock must be a multiple of the other one. -And your synthesis tool must check for setup- and hold-time violations. - -This implementation uses a small register-file for storing data. Your -synthesis tool might infer memory. This memory must -- either support asynchronous reads (as an register-file) -- or a synchronous read with mixed-port read-during-write (write-first). - -First-word-fall-through (FWFT) mode is implemented, so data can be read out -as soon as 'valid' goes high. After the data has been captured, then the -signal 'got' must be asserted. - -The advantage of the register file is, that data is available at the read -port after the rising edge of the write clock it has been written to. - -Because implementing register-files onto a FPGA might require a lot of LUT -logic, use this implementation only for small FIFOs. - -Another disadvantage is, that the signals 'full' and -'valid' are combinatorial and include an adress comparator in their path. - -The specified depth (MIN_DEPTH) is rounded up to the next suitable value. - -Synchronous reset is used. Both resets must overlap. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/fifo/fifo_dc_got_sm.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 62-85 - - - -.. only:: latex - - Source file: :pocsrc:`fifo/fifo_dc_got_sm.vhdl ` diff --git a/docs/IPCores/fifo/fifo_stage.rst b/docs/IPCores/fifo/fifo_stage.rst index 80b3c1e22..440df8333 100644 --- a/docs/IPCores/fifo/fifo_stage.rst +++ b/docs/IPCores/fifo/fifo_stage.rst @@ -1,23 +1,23 @@ -.. _IP/fifo_glue: +.. _IP/fifo_Stage: -PoC.fifo.glue -############# +PoC.fifo.Stage +############## .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_glue.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_stage.vhdl :alt: Source Code on GitHub .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_glue_tb.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_stage_tb.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` Its primary use is the decoupling of enable domains in a processing pipeline. Data storage is limited to two words only so as to allow both @@ -27,7 +27,7 @@ the ``ful`` and the ``vld`` indicators to be driven by registers. .. rubric:: Entity Declaration: -.. literalinclude:: ../../../src/fifo/fifo_glue.vhdl +.. literalinclude:: ../../../src/fifo/fifo_stage.vhdl :language: vhdl :tab-width: 2 :linenos: @@ -37,4 +37,4 @@ the ``ful`` and the ``vld`` indicators to be driven by registers. .. only:: latex - Source file: :pocsrc:`fifo/fifo_glue.vhdl ` + Source file: :pocsrc:`fifo/fifo_stage.vhdl ` diff --git a/docs/IPCores/fifo/index.rst b/docs/IPCores/fifo/index.rst index 08248ab8d..9339f4a2c 100644 --- a/docs/IPCores/fifo/index.rst +++ b/docs/IPCores/fifo/index.rst @@ -28,11 +28,9 @@ clock) refer to the write- and read-side clock relationship. got-interface), extended by a transactional `tempgot`-interface (read-side). * :ref:`IP/fifo_cc_got_tempput` implements a regular FIFO (one common clock, got-interface), extended by a transactional `tempput`-interface (write-side). - * :ref:`IP/fifo_dc_got` implements a cross-clock FIFO (two related clocks, - got-interface) * :ref:`IP/fifo_ic_got` implements a cross-clock FIFO (two independent clocks, got-interface) - * :ref:`IP/fifo_glue` implements a two-stage FIFO (one common clock, + * :ref:`IP/fifo_stage` implements a two-stage FIFO (one common clock, got-interface) * :ref:`IP/fifo_shift` implements a regular FIFO (one common clock, got-interface, optimized for FPGAs with shifter primitives) @@ -48,7 +46,7 @@ clock) refer to the write- and read-side clock relationship. fifo_cc_got fifo_cc_got_tempgot fifo_cc_got_tempput - fifo_glue + fifo_stage fifo_ic_assembly fifo_ic_got fifo_shift diff --git a/docs/IPCores/index.rst b/docs/IPCores/index.rst index 4ecd9237d..66849a03e 100644 --- a/docs/IPCores/index.rst +++ b/docs/IPCores/index.rst @@ -26,4 +26,5 @@ Namespaces for Entities: misc net sort + sync xil diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst deleted file mode 100644 index 985d66cd7..000000000 --- a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst +++ /dev/null @@ -1,60 +0,0 @@ -.. _IP/ddr2_mem2mig_adapter_Spartan6: - -PoC.mem.ddr2.mem2mig_adapter_Spartan6 -##################################### - -.. only:: html - - .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl - :alt: Source Code on GitHub - .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr2/ddr2_mem2mig_adapter_Spartan6_tb.vhdl - :alt: Source Code on GitHub - - .. sidebar:: GitHub Links - - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` - -Adapter between the :ref:`PoC.Mem ` -interface and the User Interface of the Xilinx MIG IP core for the -Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to -have multiple ports. One instance of this adapter is required for every -port. The control signals for one port of the MIG IP core are prefixed by -"cX_pY", meaning port Y on controller X. - -Simplifies the User Interface ("user") of the Xilinx MIG IP core (UG388). -The PoC.Mem interface provides single-cycle fully pipelined read/write access -to the memory. All accesses are word-aligned. Always all bytes of a word are -written to the memory. More details can be found -:ref:`here `. - -Generic parameters: - -* D_BITS: Data bus width of the PoC.Mem and MIG / MCBinterface. Also size of - one word in bits. - -* MEM_A_BITS: Address bus width of the PoC.Mem interface. - -* APP_A_BTIS: Address bus width of the MIG / MCB interface. - -Containts only combinational logic. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 61-96 - - - -.. only:: latex - - Source file: :pocsrc:`mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl ` diff --git a/docs/IPCores/mem/ddr2/index.rst b/docs/IPCores/mem/ddr2/index.rst deleted file mode 100644 index 3f2fdbac7..000000000 --- a/docs/IPCores/mem/ddr2/index.rst +++ /dev/null @@ -1,22 +0,0 @@ -.. _NS/ddr2: - -PoC.mem.ddr2 -============ - -The namespace ``PoC.mem.ddr2`` is designated for own implementations of -DDR2 memory controllers as well as for adapters for vendor-specific -implementations. At the top-level, all controllers and adapters -provide the same simple memory interface to the user application. - -.. **Package** - -**Entities** - - * :ref:`IP/ddr2_mem2mig_adapter_Spartan6` - Adapter for the Xilinx MIG core - for Spartan-6 FPGAs - - -.. toctree:: - :hidden: - - ddr2_mem2mig_adapter_Spartan6 diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst deleted file mode 100644 index a73799ca5..000000000 --- a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst +++ /dev/null @@ -1,59 +0,0 @@ -.. _IP/ddr3_mem2mig_adapter_Series7: - -PoC.mem.ddr3.mem2mig_adapter_Series7 -#################################### - -.. only:: html - - .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl - :alt: Source Code on GitHub - .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr3/ddr3_mem2mig_adapter_Series7_tb.vhdl - :alt: Source Code on GitHub - - .. sidebar:: GitHub Links - - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` - -Adapter between the :ref:`PoC.Mem ` interface and the -application interface ("app") of the Xilinx MIG IP core for 7-Series FPGAs. - -Simplifies the application interface ("app") of the Xilinx MIG IP core. -The PoC.Mem interface provides single-cycle fully pipelined read/write access -to the memory. All accesses are word-aligned. Always all bytes of a word are -written to the memory. More details can be found -:ref:`here `. - -Generic parameters: - -* D_BITS: Data bus width of the PoC.Mem and "app" interface. Also size of one - word in bits. - -* DQ_BITS: Size of data bus between memory controller and external memory - (DIMM, SoDIMM). - -* MEM_A_BITS: Address bus width of the PoC.Mem interface. - -* APP_A_BTIS: Address bus width of the "app" interface. - -Containts only combinational logic. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 60-96 - - - -.. only:: latex - - Source file: :pocsrc:`mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl ` diff --git a/docs/IPCores/mem/ddr3/index.rst b/docs/IPCores/mem/ddr3/index.rst deleted file mode 100644 index a7b8c82cb..000000000 --- a/docs/IPCores/mem/ddr3/index.rst +++ /dev/null @@ -1,22 +0,0 @@ -.. _NS/ddr3: - -PoC.mem.ddr3 -============ - -The namespace ``PoC.mem.ddr3`` is designated for own implementations of -DDR3 memory controllers as well as for adapters for vendor-specific -implementations. At the top-level, all controllers and adapters -provide the same simple memory interface to the user application. - -.. **Package** - -**Entities** - - * :ref:`IP/ddr3_mem2mig_adapter_Series7` - Adapter for the Xilinx MIG core - for 7-Series FPGAs - - -.. toctree:: - :hidden: - - ddr3_mem2mig_adapter_Series7 diff --git a/docs/IPCores/mem/index.rst b/docs/IPCores/mem/index.rst index d6e93a07f..4f3b95c2a 100644 --- a/docs/IPCores/mem/index.rst +++ b/docs/IPCores/mem/index.rst @@ -9,8 +9,6 @@ implementations. **Sub-Namespaces** - * :ref:`NS/ddr2` - DDR2 memory controllers - * :ref:`NS/ddr3` - DDR3 memory controllers * :ref:`NS/lut` - Lookup-Table (LUT) implementations * :ref:`NS/ocram` - On-Chip RAM abstraction layer * :ref:`NS/ocrom` - On-Chip ROM abstraction layer @@ -29,8 +27,6 @@ implementations. .. toctree:: :hidden: - ddr2 - ddr3 lut ocram ocrom diff --git a/docs/IPCores/misc/index.rst b/docs/IPCores/misc/index.rst index 720e715cb..c6da9f120 100644 --- a/docs/IPCores/misc/index.rst +++ b/docs/IPCores/misc/index.rst @@ -9,7 +9,6 @@ The namespace ``PoC.misc`` offers different yet uncathegorized entities. * :ref:`NS/filter` contains 1-bit filter algorithms. * :ref:`NS/stat` contains statistic modules. - * :ref:`NS/sync` offers clock-domain-crossing (CDC) modules. **Package** @@ -31,7 +30,6 @@ The package :ref:`PoC.misc ` holds all component declarations for this filter gearbox stat - sync .. toctree:: :hidden: diff --git a/docs/IPCores/net/net_FrameLoopback.rst b/docs/IPCores/net/net_FrameLoopback.rst index 380a9483a..074e435d0 100644 --- a/docs/IPCores/net/net_FrameLoopback.rst +++ b/docs/IPCores/net/net_FrameLoopback.rst @@ -1,4 +1,4 @@ -.. _IP/FrameLoopback: +.. _IP/net_FrameLoopback: PoC.net.FrameLoopback ##################### diff --git a/docs/IPCores/misc/sync/index.rst b/docs/IPCores/sync/index.rst similarity index 97% rename from docs/IPCores/misc/sync/index.rst rename to docs/IPCores/sync/index.rst index 31901945e..f4b4ffad4 100644 --- a/docs/IPCores/misc/sync/index.rst +++ b/docs/IPCores/sync/index.rst @@ -1,9 +1,9 @@ .. _NS/sync: -PoC.misc.sync -============= +PoC.sync +======== -The namespace ``PoC.misc.sync`` offers different clock-domain-crossing (CDC) +The namespace ``PoC.sync`` offers different clock-domain-crossing (CDC) synchronizer circuits. All synchronizers are based on the basic 2 flip-flop synchonizer called :ref:`sync_Bits `. PoC has two platform specific implementations for Altera and Xilinx, which are choosen, diff --git a/docs/IPCores/misc/sync/sync.pkg.rst b/docs/IPCores/sync/sync.pkg.rst similarity index 57% rename from docs/IPCores/misc/sync/sync.pkg.rst rename to docs/IPCores/sync/sync.pkg.rst index aed687edd..994fc861d 100644 --- a/docs/IPCores/misc/sync/sync.pkg.rst +++ b/docs/IPCores/sync/sync.pkg.rst @@ -2,18 +2,18 @@ .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync.pkg.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sync/sync.pkg.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - |gh-src| :pocsrc:`Sourcecode ` + |gh-src| :pocsrc:`Sourcecode ` .. _PKG/sync: -PoC.misc.sync Package -===================== +PoC.sync Package +================ .. only:: latex - Source file: :pocsrc:`sync.pkg.vhdl ` + Source file: :pocsrc:`sync.pkg.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Bits.rst b/docs/IPCores/sync/sync_Bits.rst similarity index 70% rename from docs/IPCores/misc/sync/sync_Bits.rst rename to docs/IPCores/sync/sync_Bits.rst index 5b7f1bd67..0ebca478e 100644 --- a/docs/IPCores/misc/sync/sync_Bits.rst +++ b/docs/IPCores/sync/sync_Bits.rst @@ -1,23 +1,23 @@ .. _IP/sync_Bits: -PoC.misc.sync.Bits -################## +PoC.sync.Bits +############# .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Bits.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sync/sync_Bits.vhdl :alt: Source Code on GitHub .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Bits_tb.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sync/sync_Bits_tb.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module synchronizes multiple flag bits into clock-domain ``Clock``. The clock-domain boundary crossing is done by two synchronizer D-FFs. All @@ -43,7 +43,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/misc/sync/sync_Bits.vhdl +.. literalinclude:: ../../../../src/sync/sync_Bits.vhdl :language: vhdl :tab-width: 2 :linenos: @@ -51,17 +51,17 @@ Constraints: .. seealso:: - :doc:`PoC.misc.sync.Reset ` + :doc:`PoC.sync.Reset ` For a special 2 D-FF synchronizer for *reset*-signals. - :doc:`PoC.misc.sync.Pulse ` + :doc:`PoC.sync.Pulse ` For a special 1+2 D-FF synchronizer for *pulse*-signals. - :doc:`PoC.misc.sync.Strobe ` + :doc:`PoC.sync.Strobe ` For a synchronizer for *strobe*-signals. - :doc:`PoC.misc.sync.Vector ` + :doc:`PoC.sync.Vector ` For a multiple bits capable synchronizer. .. only:: latex - Source file: :pocsrc:`misc/sync/sync_Bits.vhdl ` + Source file: :pocsrc:`sync/sync_Bits.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Command.rst b/docs/IPCores/sync/sync_Command.rst similarity index 74% rename from docs/IPCores/misc/sync/sync_Command.rst rename to docs/IPCores/sync/sync_Command.rst index 74fd2dba7..82b1700b7 100644 --- a/docs/IPCores/misc/sync/sync_Command.rst +++ b/docs/IPCores/sync/sync_Command.rst @@ -1,23 +1,23 @@ .. _IP/sync_Command: -PoC.misc.sync.Command -##################### +PoC.sync.Command +################ .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Command.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sync/sync_Command.vhdl :alt: Source Code on GitHub .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Command_tb.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sync/sync_Command_tb.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module synchronizes a vector of bits from clock-domain ``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is done by a @@ -35,7 +35,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/misc/sync/sync_Command.vhdl +.. literalinclude:: ../../../../src/sync/sync_Command.vhdl :language: vhdl :tab-width: 2 :linenos: @@ -45,4 +45,4 @@ Constraints: .. only:: latex - Source file: :pocsrc:`misc/sync/sync_Command.vhdl ` + Source file: :pocsrc:`sync/sync_Command.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Pulse.rst b/docs/IPCores/sync/sync_Pulse.rst similarity index 70% rename from docs/IPCores/misc/sync/sync_Pulse.rst rename to docs/IPCores/sync/sync_Pulse.rst index e80f85f0d..e60ebfd00 100644 --- a/docs/IPCores/misc/sync/sync_Pulse.rst +++ b/docs/IPCores/sync/sync_Pulse.rst @@ -1,23 +1,23 @@ .. _IP/sync_Pulse: -PoC.misc.sync.Pulse -################### +PoC.sync.Pulse +############## .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Pulse.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sync/sync_Pulse.vhdl :alt: Source Code on GitHub .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Pulse_tb.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sync/sync_Pulse_tb.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module synchronizes multiple pulsed bits into the clock-domain ``Clock``. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits @@ -43,7 +43,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/misc/sync/sync_Pulse.vhdl +.. literalinclude:: ../../../../src/sync/sync_Pulse.vhdl :language: vhdl :tab-width: 2 :linenos: @@ -51,17 +51,17 @@ Constraints: .. seealso:: - :doc:`PoC.misc.sync.Bits ` + :doc:`PoC.sync.Bits ` For a common 2 D-FF synchronizer for *flag*-signals. - :doc:`PoC.misc.sync.Reset ` + :doc:`PoC.sync.Reset ` For a special 2 D-FF synchronizer for *reset*-signals. - :doc:`PoC.misc.sync.Strobe ` + :doc:`PoC.sync.Strobe ` For a synchronizer for *strobe*-signals. - :doc:`PoC.misc.sync.Vector ` + :doc:`PoC.sync.Vector ` For a multiple bits capable synchronizer. .. only:: latex - Source file: :pocsrc:`misc/sync/sync_Pulse.vhdl ` + Source file: :pocsrc:`sync/sync_Pulse.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Reset.rst b/docs/IPCores/sync/sync_Reset.rst similarity index 77% rename from docs/IPCores/misc/sync/sync_Reset.rst rename to docs/IPCores/sync/sync_Reset.rst index 62979945e..6cbd9de6c 100644 --- a/docs/IPCores/misc/sync/sync_Reset.rst +++ b/docs/IPCores/sync/sync_Reset.rst @@ -1,23 +1,23 @@ .. _IP/sync_Reset: -PoC.misc.sync.Reset -################### +PoC.sync.Reset +############## .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Reset.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sync/sync_Reset.vhdl :alt: Source Code on GitHub .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Reset_tb.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sync/sync_Reset_tb.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module synchronizes an asynchronous reset signal to the clock ``Clock``. The ``Input`` can be asserted and de-asserted at any time. @@ -45,7 +45,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/misc/sync/sync_Reset.vhdl +.. literalinclude:: ../../../../src/sync/sync_Reset.vhdl :language: vhdl :tab-width: 2 :linenos: @@ -55,4 +55,4 @@ Constraints: .. only:: latex - Source file: :pocsrc:`misc/sync/sync_Reset.vhdl ` + Source file: :pocsrc:`sync/sync_Reset.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Strobe.rst b/docs/IPCores/sync/sync_Strobe.rst similarity index 71% rename from docs/IPCores/misc/sync/sync_Strobe.rst rename to docs/IPCores/sync/sync_Strobe.rst index fb58d9959..b895f1052 100644 --- a/docs/IPCores/misc/sync/sync_Strobe.rst +++ b/docs/IPCores/sync/sync_Strobe.rst @@ -1,23 +1,23 @@ .. _IP/sync_Strobe: -PoC.misc.sync.Strobe -#################### +PoC.sync.Strobe +############### .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Strobe.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sync/sync_Strobe.vhdl :alt: Source Code on GitHub .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Strobe_tb.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sync/sync_Strobe_tb.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module synchronizes multiple high-active bits from clock-domain ``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is @@ -29,8 +29,8 @@ suppressed by a rising edge detection. .. ATTENTION:: Use this synchronizer only for one-cycle high-active signals (strobes). -.. image:: /_static/misc/sync/sync_Strobe.* - :target: ../../../_static/misc/sync/sync_Strobe.svg +.. image:: /_static/sync/sync_Strobe.* + :target: ../../../_static/sync/sync_Strobe.svg Constraints: This module uses sub modules which need to be constrained. Please @@ -40,7 +40,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/misc/sync/sync_Strobe.vhdl +.. literalinclude:: ../../../../src/sync/sync_Strobe.vhdl :language: vhdl :tab-width: 2 :linenos: @@ -50,4 +50,4 @@ Constraints: .. only:: latex - Source file: :pocsrc:`misc/sync/sync_Strobe.vhdl ` + Source file: :pocsrc:`sync/sync_Strobe.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Vector.rst b/docs/IPCores/sync/sync_Vector.rst similarity index 73% rename from docs/IPCores/misc/sync/sync_Vector.rst rename to docs/IPCores/sync/sync_Vector.rst index 6058ddb88..b44159bca 100644 --- a/docs/IPCores/misc/sync/sync_Vector.rst +++ b/docs/IPCores/sync/sync_Vector.rst @@ -1,23 +1,23 @@ .. _IP/sync_Vector: -PoC.misc.sync.Vector -#################### +PoC.sync.Vector +############### .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Vector.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sync/sync_Vector.vhdl :alt: Source Code on GitHub .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Vector_tb.vhdl + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sync/sync_Vector_tb.vhdl :alt: Source Code on GitHub .. sidebar:: GitHub Links - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module synchronizes a vector of bits from clock-domain ``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is done by a @@ -34,7 +34,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/misc/sync/sync_Vector.vhdl +.. literalinclude:: ../../../../src/sync/sync_Vector.vhdl :language: vhdl :tab-width: 2 :linenos: @@ -44,4 +44,4 @@ Constraints: .. only:: latex - Source file: :pocsrc:`misc/sync/sync_Vector.vhdl ` + Source file: :pocsrc:`sync/sync_Vector.vhdl ` diff --git a/docs/IPCores/xil/index.rst b/docs/IPCores/xil/index.rst index af1dc1c4a..70be4ace2 100644 --- a/docs/IPCores/xil/index.rst +++ b/docs/IPCores/xil/index.rst @@ -7,7 +7,6 @@ This namespace is for Xilinx specific modules. **Sub-Namespaces** - * :ref:`NS/mig` * :ref:`NS/reconfig` **Entities** From fc5778006fb74b7c69858800c280d45736d614d6 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 13 Oct 2025 17:46:28 +0200 Subject: [PATCH 05/56] Fixed relative paths to sources. --- docs/IPCores/sync/sync_Bits.rst | 2 +- docs/IPCores/sync/sync_Command.rst | 2 +- docs/IPCores/sync/sync_Pulse.rst | 2 +- docs/IPCores/sync/sync_Reset.rst | 2 +- docs/IPCores/sync/sync_Strobe.rst | 2 +- docs/IPCores/sync/sync_Vector.rst | 2 +- docs/_static/{misc => }/sync/sync_Strobe.png | Bin docs/_static/{misc => }/sync/sync_Strobe.svg | 0 docs/conf.py | 10 +++++----- 9 files changed, 11 insertions(+), 11 deletions(-) rename docs/_static/{misc => }/sync/sync_Strobe.png (100%) rename docs/_static/{misc => }/sync/sync_Strobe.svg (100%) diff --git a/docs/IPCores/sync/sync_Bits.rst b/docs/IPCores/sync/sync_Bits.rst index 0ebca478e..b9b951201 100644 --- a/docs/IPCores/sync/sync_Bits.rst +++ b/docs/IPCores/sync/sync_Bits.rst @@ -43,7 +43,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/sync/sync_Bits.vhdl +.. literalinclude:: ../../../src/sync/sync_Bits.vhdl :language: vhdl :tab-width: 2 :linenos: diff --git a/docs/IPCores/sync/sync_Command.rst b/docs/IPCores/sync/sync_Command.rst index 82b1700b7..c83359b7e 100644 --- a/docs/IPCores/sync/sync_Command.rst +++ b/docs/IPCores/sync/sync_Command.rst @@ -35,7 +35,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/sync/sync_Command.vhdl +.. literalinclude:: ../../../src/sync/sync_Command.vhdl :language: vhdl :tab-width: 2 :linenos: diff --git a/docs/IPCores/sync/sync_Pulse.rst b/docs/IPCores/sync/sync_Pulse.rst index e60ebfd00..7dcd0fc56 100644 --- a/docs/IPCores/sync/sync_Pulse.rst +++ b/docs/IPCores/sync/sync_Pulse.rst @@ -43,7 +43,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/sync/sync_Pulse.vhdl +.. literalinclude:: ../../../src/sync/sync_Pulse.vhdl :language: vhdl :tab-width: 2 :linenos: diff --git a/docs/IPCores/sync/sync_Reset.rst b/docs/IPCores/sync/sync_Reset.rst index 6cbd9de6c..8fceeff98 100644 --- a/docs/IPCores/sync/sync_Reset.rst +++ b/docs/IPCores/sync/sync_Reset.rst @@ -45,7 +45,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/sync/sync_Reset.vhdl +.. literalinclude:: ../../../src/sync/sync_Reset.vhdl :language: vhdl :tab-width: 2 :linenos: diff --git a/docs/IPCores/sync/sync_Strobe.rst b/docs/IPCores/sync/sync_Strobe.rst index b895f1052..42d1448d0 100644 --- a/docs/IPCores/sync/sync_Strobe.rst +++ b/docs/IPCores/sync/sync_Strobe.rst @@ -40,7 +40,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/sync/sync_Strobe.vhdl +.. literalinclude:: ../../../src/sync/sync_Strobe.vhdl :language: vhdl :tab-width: 2 :linenos: diff --git a/docs/IPCores/sync/sync_Vector.rst b/docs/IPCores/sync/sync_Vector.rst index b44159bca..c858c4737 100644 --- a/docs/IPCores/sync/sync_Vector.rst +++ b/docs/IPCores/sync/sync_Vector.rst @@ -34,7 +34,7 @@ Constraints: .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/sync/sync_Vector.vhdl +.. literalinclude:: ../../../src/sync/sync_Vector.vhdl :language: vhdl :tab-width: 2 :linenos: diff --git a/docs/_static/misc/sync/sync_Strobe.png b/docs/_static/sync/sync_Strobe.png similarity index 100% rename from docs/_static/misc/sync/sync_Strobe.png rename to docs/_static/sync/sync_Strobe.png diff --git a/docs/_static/misc/sync/sync_Strobe.svg b/docs/_static/sync/sync_Strobe.svg similarity index 100% rename from docs/_static/misc/sync/sync_Strobe.svg rename to docs/_static/sync/sync_Strobe.svg diff --git a/docs/conf.py b/docs/conf.py index 84786ba07..f7a7aff47 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -33,10 +33,10 @@ # release = versionInformation.Version project = 'The PoC-Library' copyright = '2007-2016 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture' -author = 'Patrick Lehmann, Thomas B. Preusser, Martin Zabel' +author = 'The PoC-Library Authors' -version = "1.1" # The short X.Y version. -release = "1.1.1" # The full version, including alpha/beta/rc tags. +version = "2.1" # The short X.Y version. +release = "2.1.0" # The full version, including alpha/beta/rc tags. from subprocess import check_output @@ -268,8 +268,8 @@ def _LatestTagName(): "ghsrc": (f"https://GitHub.com/{githubNamespace}/{project}/blob/master/%s", None), "wiki": (f"https://en.wikipedia.org/wiki/%s", None), - "pocissue": (f"https://github.com/{githubNamespace}/{project}/issues/%s", 'issue #'), # => replace by ghissue - "pocpull": (f"https://github.com/{githubNamespace}/{project}/pull/%s", 'pull request #'), # => replace by ghpull + "pocissue": (f"https://github.com/{githubNamespace}/{project}/issues/%s", 'issue #%s'), # => replace by ghissue + "pocpull": (f"https://github.com/{githubNamespace}/{project}/pull/%s", 'pull request #%s'), # => replace by ghpull "pocsrc": (f"https://github.com/{githubNamespace}/{project}/blob/master/src/%s?ts=2", None), # => replace by ghsrc "poctb": (f"https://github.com/{githubNamespace}/{project}/blob/master/tb/%s?ts=2", None) } From 652c32a751f4e79dfa82fa8c559a62ec43d669ab Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 13 Oct 2025 17:48:19 +0200 Subject: [PATCH 06/56] Initial documentation from Markdown. --- .../axi4lite/axi4lite_GitVersionRegister.rst | 44 ++ .../bus/axi4/axi4lite/axi4lite_Register.rst | 424 ++++++++++++++++++ 2 files changed, 468 insertions(+) create mode 100644 docs/IPCores/bus/axi4/axi4lite/axi4lite_GitVersionRegister.rst create mode 100644 docs/IPCores/bus/axi4/axi4lite/axi4lite_Register.rst diff --git a/docs/IPCores/bus/axi4/axi4lite/axi4lite_GitVersionRegister.rst b/docs/IPCores/bus/axi4/axi4lite/axi4lite_GitVersionRegister.rst new file mode 100644 index 000000000..6b50226ba --- /dev/null +++ b/docs/IPCores/bus/axi4/axi4lite/axi4lite_GitVersionRegister.rst @@ -0,0 +1,44 @@ +axi4lite_GitVersionRegister +########################### + + +Current version of this version Reg is `1`. Use this tcl script for Vivado synth-pre-tcl: [set_BuildVersion.tcl](/uploads/9fdf1898a1797857e11889134c5179d0/set_BuildVersion.tcl) + +Generics +******** + +| Name | Description | +|-------|----------| +| VERSION_FILE_NAME | Path to the Version-mem-file created by `set_BuildVersion.tcl`. Relative to `constant MY_PROJECT_DIR` in `src/PoC/my_project.vhdl` | +| HEADER_FILE_NAME | If csv-file with all register spaces is needed, put here the name/path of csv-file. Relative to `constant MY_PROJECT_DIR` in `src/PoC/my_project.vhdl` | +| INCLUDE_XIL_DNA | Includes Xilinx-DNA-Port. Working for 7-Series and US/US+ Devices. Note: 7-Series has 32 times this "unique" ID. | +| INCLUDE_XIL_USR_EFUSE | Includes Usr-EFuse. {-Currently not Implemented-} | +| USER_ID | 96bit ID, which can be set through PL in synthesis. | + +Register Map +************ + +All Registers are Read-only. Version Register should always start with offset `0x80000000` (First PL Address). + +| Offset | Name | Description | +|---------|-------|----------| +| 0x000 | Common.BuildDate | 31:24 Day
23:16 Month
15:0 Year | +| 0x004 | Common.NumberModule_VersionOfVersionReg | 31:8 Reserved
7:0 Version-of-Version-Reg (`1`) | +| 0x008 | Common.VivadoVersion | 31:16 Major
15:8 Minor
7:0 Patch | +| 0x00C | Common.ProjektName | `String` Project-Name (20Byte) | +| 0x020 | Top.Version | 31:24 Major
23:16 Minor
15:8 Patch
7:2 Commits-to-Tag(dev-build)
1 Dirty_untracked
0 Dirty_modified | +| 0x024 | Top.GitHash | Git-Hash 20Bytes. Endianess is reversed in the registers. The order of the registers is reversed as well. | +| 0x038 | Top.GitDate | Commit-Date: 31:24 Day
23:16 Month
15:0 Year | +| 0x03C | Top.GitTime | Commit-Time: 31:24 Hour
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7:0 Time-Zone as signed| +| 0x040 | Top.BranchName_Tag | Branch-Name 64Byte | +| 0x080 | Top.GitURL | Git-URL starting after `gitlab.plc2.de/` (128Byte) | +| 0x100 | UID.UID | Only present if `INCLUDE_XIL_DNA` is enabled (16Byte)
For US/US+ lower 96bit valid, for Series-7 64bit valid | +| 0x110 | UID.User_eFuse | Only present if `INCLUDE_XIL_USR_EFUSE` is enabled | +| 0x114 | UID.User_ID | 96-bit User_ID set by PL | + +Files +***** + +Current implementations gives these *.csv and converted *.h files: +* [Version_Register.csv](/uploads/2f25caea1127e08aa8a2306504199476/Version_Register.csv) +* [Version_Register.h](/uploads/58cae3f86d3ab4da98094b09a6d9ae39/Version_Register.h) diff --git a/docs/IPCores/bus/axi4/axi4lite/axi4lite_Register.rst b/docs/IPCores/bus/axi4/axi4lite/axi4lite_Register.rst new file mode 100644 index 000000000..96f9b8de3 --- /dev/null +++ b/docs/IPCores/bus/axi4/axi4lite/axi4lite_Register.rst @@ -0,0 +1,424 @@ + + +axi4lite_Register +################# + +This issue documents the functionality and usage of the `AXI4Lite_Register` module located at `src\bus\axi4\AXI4Lite\AXI4Lite_Register.vhdl`. + +Overview +******** + +The `AXI4Lite-Register` is a generic implementation of a register interface for access of software via the AXI4Lite protocol. It uses a `Config` record vector to describe the registers. It was designed to work for all purposes as `Eierlegende Wollmilchsau`. + +Interface +********* +The interface of the PL-side is named from the PL point-of-view, the configuration is named from the software point-of-view! + +Generics +======== + +| Name | Type | Default | Description | +|------|-------|---------|-------------| +| MARK_DEBUG_SIGNALS | boolean | false | If set to true, the module sets specific internal signals as mark-debug. These signals are the hit-vectors, decoded addresses, and interrupt signals. | +| VERBOSE | boolean | false | If set to true, the module will print the configuration and settings into the synthesis-log with `assert`. | +| IGNORE_HIGH_ADDRESS | boolean | true | The module will calculate based on the configuration how many bits are needed to address every specified register. If this generic is set, it will ignore every bit which is coming after the needed address-bits. These bits are considered as base address. By setting this value, you can pass the full 40/32bit from Zynq, and it will filter out the base address for it. | +| DISABLE_ADDRESS_CHECK | boolean | false | The module is internally calculating if any registers have overlapping addresses and will create an error if so. This check takes a bit of synthesis time that depends on the size of `Config`. This check can be disabled. **This is not recommended!** | +| INIT_ON_RESET | boolean | true | The Init-value of the registers, that is set by the `Config`, is set by default with the Reset. This can be disabled here. This helps with reducing control-sets and therefore helps by CLB utilization. | +| INTERRUPT_IS_STROBE | boolean | true | With this generic, it can be selected if the Interrupt-pin should through an interrupt as `Strobe` or `Value`. With selecting `Strobe`, the module will block a new interrupt until the `INTERRUPT_MATCH_REGISTER`is read out. | +| INTERRUPT_ENABLE_REGISTER_ADDRESS | unsigned | 0x0 | If Interrupts are used, this generic selects the address of the internal `INTERRUPT_ENABLE_REGISTER`. | +| INTERRUPT_MATCH_REGISTER_ADDRESS | unsigned | 0x4 | If Interrupts are used, this generic selects the address of the internal `INTERRUPT_MATCH_REGISTER`. | +| RESPONSE_ON_ERROR | AXI4Lite.pkg:
T_AXI4_Response | C_AXI4_RESPONSE_
DECODE_ERROR | With this generic can be selected which response code should be sent out if an address is accessed that is not handled by `Config`. Possible Values are: `C_AXI4_RESPONSE_OKAY`, `C_AXI4_RESPONSE_EX_OKAY`, `C_AXI4_RESPONSE_SLAVE_ERROR` or `C_AXI4_RESPONSE_DECODE_ERROR`. | +| CONFIG | AXI4Lite.pkg:
T_AXI4_Register_
Description_Vector | - | This generic holds the Register-Configuration. It is explained later in more detail. | + +Ports +===== + +| Name | Dir | Type | Description | +|------|-----|------|--------------| +| S_AXI_ACLK | in | std_logic | Module Clock | +| S_AXI_ARESETN | in | std_logic | synchronous Reset | +| S_AXI_m2s | in | T_AXI4Lite_BUS_M2S | AXI4Lite master-to-slave record. From AXI4Lite.pkg. | +| S_AXI_s2m | out | T_AXI4Lite_BUS_S2M | Axi4-Lite slave-to-master record. From AXI4Lite.pkg. | +| S_AXI_IRQ | out | std_logic | Module Interrupt Pin. Functionality depends on `Generics`. | +| RegisterFile_ReadPort | out | T_SLVV(0 to CONFIG'Length - 1)(31 downto 0) | Read-Port to PL of the Register Values. Two-dimensional-array. | +| RegisterFile_ReadPort_hit | out | std_logic_vector(0 to CONFIG'Length - 1) | Hit-Vector to PL. A one is generated if the Software has written a specific register and therefore changed the value in RegisterFile_ReadPort. | +| RegisterFile_WritePort | in | T_SLVV(0 to CONFIG'Length - 1)(31 downto 0) | Write-Port from PL. This Port is used to write into the internal registers from PL. | +| RegisterFile_WritePort_hit | out | std_logic_vector(0 to CONFIG'Length - 1) | Hit-Vector to PL. A one is generated if the Software has read out a specific register and therefore got the value from the register. | +| RegisterFile_WritePort_strobe | in | std_logic_vector(0 to CONFIG'Length - 1) | By setting a bit to one, the corresponding value at `RegisterFile_WritePort` is written into its register. The default value is set by the function `get_strobeVector(CONFIG)` and can be let like this. Overwrite is mostly needed if `rw_config` is set to `readWriteable`. | + +Configuration +************* + +The Configuration put into the generic `Config` determines the functionality of this register. It is an vector of the record-type `AXI4Lite.pkg:T_AXI4_Register_Description`. This record has the following fields/elements: +| Field | Type | Description | +|------|---------|----------| +| Name | string(1 to 64) | A Name as string can be selected for this register. | +| Address | unsigned(31 downto 0) | The Address of this register. | +| rw_config | T_ReadWrite_Config | See chapter `Register Mode (ReadWrite-Config)` | +| Init_Value | std_logic_vector(31 downto 0) | The initial value after reset or boot-up of the register. | +| Auto_Clear_Mask | std_logic_vector(31 downto 0) | Auto-clear-mask if rw_config is `readWriteable`. Bits set in this maks are given out only as a strobe and cleared with the next clock-cycle. | +| Is_Interrupt_Register | boolean | Selects if this register can create and interrupt or not. See section `Interrupt`. | + +Register Mode (ReadWrite-Config) +================================ + +For each register, a mode can be selected with the field `rw_config`. This mode depends on the functionality that should be achieved. Possible modes are: +| Mode | Used for | Description | +|------|----------|--------------| +| constant_fromInit | constant | This Mode connects the `Init_Value` directly to the read-mux. No Flip-Flop is created and the Read and Write Port is unconnected. | +| readable | Read-only-Reg | This Mode is used to provide a Status register. | +| readable_non_reg | Read-only-Reg | As `readable` but does not create flip-flops internally. The WritePort is directly connected to the read-mux. Can be used if data is already driven by registers or if path is not time-critical. | +| readWriteable | Read-Write-Reg | This Mode can be used to configure or control the PL form SW. Software can write into this register, and it will be visible through `RegisterFile_ReadPort`. The PL can also overwrite the Value by setting the corresponding bit in port `RegisterFile_WritePort_strobe`. In this mode, the field `Auto_Clear_Mask` is active. It can be used to control FSM's with a command, that is set only for one CC. | +| readWriteable_non_reg | Special | This mode is used only for special use-cases. It provides the internal read- and write-mux connections directly to the ports, so any external functionality can be implemented. **Data on the `RegisterFile_ReadPort` is only valid if `RegisterFile_WritePort_strobe` is set!** See also chapter `Special Functionality`. | +| latchValue_clearOnRead | Status/Error | `Interrupt Capable` After Reset or boot-up, this latch is cleared and can accept new data. If Stobe is then set, the data from `RegisterFile_WritePort` is saved. If this value is unequal to `Init_Value`, the value can not be overwritten until the SW reads it out. If latching condition is met and register is set as `Is_Interrupt_Register`, and interrupt is thrown. | +| latchValue_clearOnWrite | Status/Error | `Interrupt Capable` Same as `latchValue_clearOnRead`, but it is only cleared by actively writing into this register. The written value is ignored. | +| latchHighBit_clearOnRead | Status/Error | `Interrupt Capable` By setting `Strobe`, the value of `RegisterFile_WritePort` is logically or-red together with the current register content. So a one-bit is always added to the value. By reading this register out, the software gets the value and clears it as well. | +| latchHighBit_clearOnWrite | Status/Error | `Interrupt Capable` Same as `latchHighBit_clearOnRead `, but it is only cleared by actively writing into this register. The written value is ignored. | +| latchLowBit_clearOnRead | Status/Error | `Interrupt Capable` For low-active signals. By setting `Strobe`, the value of `RegisterFile_WritePort` is logically and-ed together with the current register content. So a zero-bit is always added to the value. By reading this register out, the software gets the value and sets all bits as well. | +| latchLowBit_clearOnWrite | Status/Error | `Interrupt Capable` Same as `latchLowBit_clearOnRead `, but it is only cleared by actively writing into this register. The written value is ignored. | + +Usage +***** + +Instantiation +============= + +A minimal config with instance can look like this: +```vhdl +my_Reg_blk : block + constant CONFIG : T_AXI4_Register_Description_Vector := gen_config; + + signal RegisterFile_ReadPort : T_SLVV(0 to CONFIG'Length - 1)(31 downto 0); + --signal RegisterFile_ReadPort_hit : std_logic_vector(0 to CONFIG'Length - 1); + signal RegisterFile_WritePort : T_SLVV(0 to CONFIG'Length - 1)(31 downto 0); + --signal RegisterFile_WritePort_hit : std_logic_vector(0 to CONFIG'Length - 1); + --signal RegisterFile_WritePort_strobe : std_logic_vector(0 to CONFIG'Length - 1) := get_strobeVector(CONFIG); +begin + + Reg : entity PoC.AXI4Lite_Register + generic map( + CONFIG => ( + 0 => to_AXI4_Register_Description(Address => 32x"0", rw_config => readWriteable), + 1 => to_AXI4_Register_Description(Address => 32x"4", rw_config => readable), + ) + ) + port map( + S_AXI_ACLK => Clock, + S_AXI_ARESETN => not Reset, + + S_AXI_m2s => M00_AXI4L_m2s, + S_AXI_s2m => M00_AXI4L_s2m, + S_AXI_IRQ => open, + + RegisterFile_ReadPort => RegisterFile_ReadPort , + --RegisterFile_ReadPort_hit => RegisterFile_ReadPort_hit , + RegisterFile_WritePort => RegisterFile_WritePort + --RegisterFile_WritePort_hit => RegisterFile_WritePort_hit, + --RegisterFile_WritePort_strobe => RegisterFile_WritePort_strobe + ); +``` + +For the basic usage, only the `RegisterFile_ReadPort` and `RegisterFile_WritePort` is needed. + +Read to PL can be acheaved like this: +```vhdl +my_slv_32_signal <= RegisterFile_ReadPort(0); +``` + +To write into the register, this is enough: +```vhdl +RegisterFile_WritePort(1) <= my_slv_32_status; +``` + +Creation of Config +================== + +The configuration can be created in many different ways. If the register is small, it can be done like above by directly setting the register in the generic. This approach has the disadvantage that the index of the read and write port is changing if an register is added later. This can easily create errors inside the design, if not each and every index is checked and updated if needed. This is why this approach **is not recomanded**. + +The next step is to save the Config inside a constant. If done like this, the register can also use the `Name`-field. If all register are named, the index of the register can be calculated by helper-functions with its specific name (See next section `Helper Functions`). This helps to prevent from errors and allows easily to extend the register because the index is calculated new and updated apropriate. This approach is only suatable for mid-complex registers. + +If big or complex registers should use a function to create the description-vector. An example for such a function is given here: +```vhdl +function gen_config return T_AXI4_Register_Description_Vector is + variable temp : T_AXI4_Register_Description_Vector(0 to 511); + variable addr : natural := 0; + variable pos : natural := 0; +begin + temp(pos) := to_AXI4_Register_Description(Name => "System.Version", Address => to_unsigned(addr, 32), Init_Value => std_logic_vector(to_unsigned(3, 32)), rw_config => constant_fromInit); + addr := addr +4; pos := pos +1; + temp(pos) := to_AXI4_Register_Description(Name => "System.Status",Address => to_unsigned(addr, 32), rw_config => readable); + addr := addr +4; pos := pos +1; + + addr := 256; + temp(pos) := to_AXI4_Register_Description(Name => "System.Command",Address => to_unsigned(addr, 32), rw_config => readWriteable, Auto_Clear_Mask => x"FFFFFFFF"); + addr := addr +4; pos := pos +1; + return temp(0 to pos -1); +end function; + +constant CONFIG : T_AXI4_Register_Description_Vector := gen_config; +``` + +This example configuration creates a total of three registers. After one register is created the index/position is incremented by one and the address by 4. The addresses are adapting automatically. As can be seen, the third register is shifted to address 0x100 by overwriting the addr variable. This creates an empty space between 0x4 and 0x100, which is creating a `RESPONSE_ON_ERROR` code while read or write access. + +In this function registers can be created also as a loop: +```vhdl + + for i in 0 to Num_RTT -1 loop + temp(pos) := to_AXI4_Register_Description(Name => "Data_Value(" & integer'image(i) & ")", Address => to_unsigned(addr, 32), rw_config => readable); + pos := pos +1; addr := addr +4; + end loop; +``` +By givingeach loop-register a different name dependent on the constant `i`, it can be refferenzed separately. + +Helper Functions +================ + +For ease of use, functions are created to help for basic modifications of the configuration. +filter_Register_Description_Vector +---------------------------------- + +```vhdl +function filter_Register_Description_Vector(str : string; description_vector : T_AXI4_Register_Description_Vector) return T_AXI4_Register_Description_Vector; +``` +Removes all elements of `description_vector` where `description_vector(i).name(str'range) /= str`. + +```vhdl +function filter_Register_Description_Vector(char : character; description_vector : T_AXI4_Register_Description_Vector) return T_AXI4_Register_Description_Vector +``` +Removes all elements of `description_vector` where `description_vector(i).name(1) /= char`. + +add_Prefix +---------- + +```vhdl +function add_Prefix(prefix : string; Config : T_AXI4_Register_Description_Vector; offset : unsigned(Address_Width -1 downto 0) := (others => '0')) return T_AXI4_Register_Description_Vector; +``` +Adds the string prefix `prefix` to each Config(x).Name and adds the `offset` value to the Config(x).Address. This function can be used if multiple standerdized (as constant) register need to be put with a prefix into the big register. Here is an example: + +```vhdl +constant Config_Packetizer : T_AXI4_Register_Description_Vector := ( + 0 => to_AXI4_Register_Description(Name => "CMD", Address => to_unsigned(0, 32), rw_config => readWriteable) + 1 => to_AXI4_Register_Description(Name => "CMD2", Address => to_unsigned(4, 32), rw_config => readWriteable) + 2 => to_AXI4_Register_Description(Name => "STATUS", Address => to_unsigned(8, 32), rw_config => readable)); + +function gen_config return T_AXI4_Register_Description_Vector is + variable temp : T_AXI4_Register_Description_Vector(0 to 511); + variable addr : natural := 0; + variable pos : natural := 0; +begin + for i in 0 to 1 loop + temp(pos to pos + Config_Packetizer'length -1) := add_prefix("Packetizer(" & integer'image(i) & ").", Config_Packetizer, to_unsigned(addr, 32)); + pos := pos + Config_Packetizer'length; + addr := addr + Config_Packetizer'length *4; + end loop; + return temp(0 to pos -1); +end function; +``` + +This will result in a config that looks like this: +```vhdl +0 => (Name => "Packetizer(0).CMD", Address => 32x"0", rw_config => readWriteable), +1 => (Name => "Packetizer(0).CMD2", Address => 32x"4", rw_config => readWriteable), +2 => (Name => "Packetizer(0).STATUS", Address => 32x"8", rw_config => readable), +3 => (Name => "Packetizer(1).CMD", Address => 32x"C", rw_config => readWriteable), +4 => (Name => "Packetizer(1).CMD2", Address => 32x"10", rw_config => readWriteable), +5 => (Name => "Packetizer(1).STATUS", Address => 32x"14", rw_config => readable), +``` + +to_AXI4_Register_Description +---------------------------- + +{-TODO-} + +get_addresses +------------- +{-TODO-} + +get_InitValue +------------- +{-TODO-} + +get_AutoClearMask +----------------- +{-TODO-} + +get_index +--------- +{-TODO-} + +get_NumberOfIndexes +------------------- +{-TODO-} + +get_indexRange +-------------- +{-TODO-} + +get_Address +----------- +{-TODO-} + +get_Name +-------- +{-TODO-} + +get_strobeVector +---------------- +{-TODO-} + +## Write Register CSV File +A csv file can be written out of the configuration with the function `write_csv_file`. It is recomanded to use it with an enabled `assert` statement or writing it into a constant. With assert, you can also see in the synthesis log if everithing was successfull. `PROJECT_DIR` is a constant inside `my_project.vhdl` normaly located at `src/PoC/`. +```vhdl +constant success : boolean := write_csv_file(PROJECT_DIR & "gen/Sampling_Register.csv", config); +--or-- +assert write_csv_file(PROJECT_DIR & "gen/Sampling_Register.csv", config) report "Error in writing csv-File!" severity warning; +``` + +## Create C-Header File from CSV +A big advantage of this register is the automatic register handover to the Software. This is done by converting the freshly generaded csv file and converting it into a C-Header file. The registers specified in the config are combined into struct's. The final struct can than be layed over the AXI4Lite-Register Address. + +The conversion is done by a python-script from `git@gitlab.plc2.de:PLC2Design/Tools/Vivado-PostProcessing/c-header-csv-register-parser.git`. This python script works but has currently a lot of limitations. **It is planed to extend this script and make it accessable to the CI-Runners for automatic conversions.** + + +## Naming of Registers +The Name field of the configuration is limmited to 64-characters. This needs to be a constant and was defined like this. The conversion to the C-Header file needs some properties to work. These properties are therefore defined gloabaly. + +1. Each register needs to be named. +1. Eacht register needs to have a unique name. +1. The Addresses should monotonically increasing (Only for C-Header File). +1. Multiple Registers can be grouped together with a prefix. The prefix is separated by a dot. +1. ~~Multiple Prefixes can be made~~ {-This is currently not possible with the script.-} +1. A array of registers can be defined with parenthesis `(i)`. This will create and array in C-Header file. +1. ~~A array can be done as well on prefixes~~ {-This is currently not possible with the script.-} + +Special Functionality +********************* + +64-bit Mode +=========== +The register has a 64-bit mode. If the Data-Size of the AXI4Lite record is 64-bit wide, the AXI4Lite-Register will automatically put into 64-bit mode. The SW can then write 64-bit alligned into two 32-bit register at once. + + +**IMPORTANT NOTE: The definition in the config is still done with 32-bit registers. Two 32-bit register are combined to one 64-bit register. The read and write is done in the same CC and is consistant. Note that two Hits will be set for both 32-bit register. If the software is making a read_32 it is not possible to know from PL which of these two registers was actually read out (or written to).** + +## Interrupt +The `AXI4Lite-Register` is capable of creating interrupts. The `rw_config` needs to be a latch type to be interrupt capable (See section Register Mode (ReadWrite-Config)). In total, 32 registers can be set as interrupt register. This limitation is due to the `interrupt match register` width of 32 bits. If an interrupt register is latched, the interrupt is thrown. If the software registers an interrupt, it needs to read out the `interrupt match register` to figure out which interrupt occured. The order of the bits here is equal to the order of the interrupt registers in the config. + +E.g: +``` +Config(i) ; Name ; Address ; Init_Value ; Auto_Clear_Mask ; rw_config ; Is_Interrupt_Register +0 ; System.Version ; 0x00000000 ; 0x00000003 ; 0x00000000 ; constant_fromInit ; false +1 ; System.Test; 0x00000004 ; 0x00000000 ; 0x00000000 ; latchLowBit_clearOnRead ; true +2 ; System.Command ; 0x00000028 ; 0x00000000 ; 0xFFFFFFFF ; readWriteable ; false +3 ; System.Status ; 0x0000002C ; 0x00000000 ; 0x00000000 ; latchLowBit_clearOnRead ; true +``` +This configuration will create in total four registers of which two are interrupt registers. The `interrupt match register` bit zero is mapped to `System.Test`, bit one is mapped to `System.Status`. If one of these bits is set, the SW needs to look into the correct address for the value. This means, if after an interrupt bit zero is set from in the `interrupt match register`, the SW needs to read address `0x00000004` afterwards to get the interrupt-causing-value and clear the interrupt reason. + +Beside the `interrupt match register`, there is also the `Interrupt enable register`. With this, you can switch on and off one specific register to through interrupts. The bit will still be set inside `interrupt match register`, but it will not create an interrupt. + +The addresses of both registers are set through generics. See section Interface.Generics. + +By using this feature, the internal configuration will add both registers in this configuration: +``` +Config(i) ; Name ; Address ; Init_Value ; Auto_Clear_Mask ; rw_config ; Is_Interrupt_Register +N ; Interrupt_Enable_Register ; INTERRUPT_ENABLE_REGISTER_ADDRESS ; 0xFFFFFFFF ; 0x00000000 ; readWriteable; false +N+1 ; Interrupt_Match_Register; INTERRUPT_MATCH_REGISTER_ADDRESS ; 0x00000000 ; 0x00000000 ; latchHighBit_clearOnRead; true +``` + +Atomic Register +=============== + +An `Atomic Register` is an external wiring. This is used to avoid read-modify-write opperations from software by introducing a `clear-bit-register`, `set-bit-register` and `toggle-bit-register`. A constant is prepared for this register inside `AXI4Lite.pkg.vhdl` called `Atomic_RegisterDescription_Vector`. It can be mapped/created inside of the `gen_config` function like this: +```vhdl +temp(pos to pos + Atomic_RegisterDescription_Vector'length -1) := add_prefix("My_Atomic_reg.", Atomic_RegisterDescription_Vector, to_unsigned(addr *4, 32)); + pos := pos + Atomic_RegisterDescription_Vector'length; + addr := addr + Atomic_RegisterDescription_Vector'length; +``` +**Note: the Atomic Register should be at least 64bit alligned. If this is true, the set- and clear- mask can be written at the same time.** + +Afterwords, the wiring needs to be created in the pl like this: +```vhdl +atomic_blk : block + constant low : natural := get_index("My_Atomic_reg.ATOMIC_Value", config); + constant high : natural := get_index("My_Atomic_reg.ATOMIC_BitClr", config); + signal Atomic_Value : std_logic_vector(31 downto 0) := (others => '0'); + signal nextAtomic_Value : std_logic_vector(31 downto 0); +begin + procedure Make_AtomicRegister( + Reset => Reset, + RegisterFile_ReadPort => RegisterFile_ReadPort(low to high), + RegisterFile_WritePort => RegisterFile_WritePort(low to high), + RegisterFile_ReadPort_hit => RegisterFile_ReadPort_hit(low to high), + PL_WriteValue => Overwrite_from_PL_slv, + PL_WriteStrobe => Overwrite_from_PL_strb, + Value_reg => Atomic_Value, + nextValue_reg => nextAtomic_Value + ); + Atomic_Value <= nextAtomic_Value when rising_edge(Clock); +end block; +``` + +I/O Register +============ + +The `IO Register` is used to connect a tri-state buffer directly to the register. It consists of two `atomic registers`. The first one for `IO` (Input/Output) and the second one for `T` (Tristate). + +To add it into config: +```vhdl +temp(pos to pos + IO_RegisterDescription_Vector'length -1) := add_prefix("My_IO_reg.", IO_RegisterDescription_Vector, to_unsigned(addr *4, 32)); + pos := pos + IO_RegisterDescription_Vector'length; + addr := addr + IO_RegisterDescription_Vector'length; +``` + +Afterwords, the wiring needs to be created in the pl like this: +```vhdl +io_reg_blk : block + constant low : natural := get_index("My_IO_reg.IO.ATOMIC_Value", config); + constant high : natural := get_index("My_IO_reg.T.ATOMIC_BitClr", config); + signal IO_Value : std_logic_vector(31 downto 0) := (others => '0'); + signal nextIO_Value : std_logic_vector(31 downto 0); + signal T_Value : std_logic_vector(31 downto 0) := (others => '0'); + signal nextT_Value : std_logic_vector(31 downto 0); +begin + procedure Make_IORegister( + Reset => Reset, + RegisterFile_ReadPort => RegisterFile_ReadPort(low to high), + RegisterFile_WritePort => RegisterFile_WritePort(low to high), + RegisterFile_ReadPort_hit => RegisterFile_ReadPort_hit(low to high), + Input => Buffe_I_slv, + Output => Buffe_O_slv, + Tristate => Buffe_T_slv, + IO_reg => IO_Value, + nextIO_reg => nextIO_Value, + T_reg => T_Value, + nextT_reg => nextT_Value, + ); + IO_Value <= nextIO_Value when rising_edge(Clock); + T_Value <= nextT_Value when rising_edge(Clock); +end block; +``` + +AXI4Lite Register Split +======================= +The moduel `AXI4Lite_Register_split` is an addition to the normal register. It splits up a big register into multiple smaller ones, that can then better acheave timing. This is done by the Address-Demultiplexer `AXI4Lite_DeMux`. + +This module adds the following generics: +| Name | Type | Default | Description | +|------|-------|---------|-------------| +| SPLIT_ON_ADDRESSBIT | natural | 0 | Split the register on this address-bit. If default (zero), it will split it up on address bit 6. This means every 0x40 will be split up. | +| PIPELINE_IN| natural | 0 | Adds N many pipeline-stages before the De-Mux | +| PIPELINE_OUT| natural | 0 | Adds N many pipeline-stages between De-Mux and all registers. | + +{-Interrupts are currently not working for this module fully! It is only working if all interrupt-registers are in one sub-register and the Interrupt match and enable register addresses are located in the same sub-register.-} + + +## AXI4Lite Register Single-Access (BRAM AXI4Lite Register) +{-Experimental Module-} +This module is a variant with singel access from PL instead parallel. With this restriction, it is possible to put the register completally into Lut-Ram or BRAM and save a lot of ressources. 1 BRAM can store in total 1k registers without timing problems. + +Because it uses a dual-port-ram it has a shared access with the PL-read/write and AXI4L-read/write. To simplify the access for an potential FSM out of the PL, the access for PL is prioritized. The first port is fully reservated for the read access out of PL. The Port `RegisterFile_ReadData` shows always the value of address `RegisterFile_ReadAddress`. The second port is shared and has the following prioritization: +1. PL Write +1. AXI4L Write +1. AXI4L Read + +Currently it is not selectable if Lut-RAM or BRAM should be used. If this is needed, ask @sunrein for this feature. From c04804d878b0dfaf2f2a072fa953aa2575590f70 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 14 Oct 2025 07:10:25 +0200 Subject: [PATCH 07/56] Fixed shields. --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 1d79874d2..1e8a6638a 100644 --- a/README.md +++ b/README.md @@ -5,8 +5,8 @@ [![Sourcecode License](https://img.shields.io/badge/code-Apache%202.0-97CA00?longCache=true&style=flat-square&longCache=true&logo=Apache)](LICENSE.md) [![Documentation](https://img.shields.io/website?longCache=true&style=flat-square&label=VHDL.github.io%2FPoC&logo=GitHub&logoColor=fff&up_color=blueviolet&up_message=Read%20now%20%E2%9E%9A&url=https%3A%2F%2FVHDL.github.io%2FPoC%2Findex.html)](https://VHDL.github.io/PoC/) [![Documentation License](https://img.shields.io/badge/doc-CC--BY%204.0-green?longCache=true&style=flat-square&logo=CreativeCommons&logoColor=fff)](docs/Doc-License.rst) -![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) -[![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) +![Latest tag](https://img.shields.io/github/tag/VHDL/PoC.svg?style=flat) +[![Latest release](https://img.shields.io/github/release/VHDL/PoC.svg?style=flat)](https://github.com/VHDL/PoC/releases)