diff --git a/src/Makefile b/src/Makefile
index c7ad75ff..cf6dd96e 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 
-VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/counter.v $(PWD)/decoder.v
+VERILOG_SOURCES += $(wildcard $(PWD)/*.v)
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
 TOPLEVEL = tb