|
| 1 | +Metric,Value |
| 2 | +design__lint_error__count,0 |
| 3 | +design__lint_timing_construct__count,0 |
| 4 | +design__lint_warning__count,4 |
| 5 | +design__inferred_latch__count,0 |
| 6 | +design__instance__count,781 |
| 7 | +design__instance__area,5433.96 |
| 8 | +design__instance_unmapped__count,0 |
| 9 | +synthesis__check_error__count,0 |
| 10 | +design__max_slew_violation__count__corner:nom_tt_025C_1v80,0 |
| 11 | +design__max_fanout_violation__count__corner:nom_tt_025C_1v80,3 |
| 12 | +design__max_cap_violation__count__corner:nom_tt_025C_1v80,0 |
| 13 | +power__internal__total,0.0003932536346837878 |
| 14 | +power__switching__total,0.00023121328558772802 |
| 15 | +power__leakage__total,6.580490374830106E-9 |
| 16 | +power__total,0.0006244734977371991 |
| 17 | +clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.256476597219624 |
| 18 | +clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.25649713634616045 |
| 19 | +timing__hold__ws__corner:nom_tt_025C_1v80,0.33963549600713827 |
| 20 | +timing__setup__ws__corner:nom_tt_025C_1v80,14.316426671599018 |
| 21 | +timing__hold__tns__corner:nom_tt_025C_1v80,0.0 |
| 22 | +timing__setup__tns__corner:nom_tt_025C_1v80,0.0 |
| 23 | +timing__hold__wns__corner:nom_tt_025C_1v80,0 |
| 24 | +timing__setup__wns__corner:nom_tt_025C_1v80,0.0 |
| 25 | +timing__hold_vio__count__corner:nom_tt_025C_1v80,0 |
| 26 | +timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.339635 |
| 27 | +timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0 |
| 28 | +timing__setup_vio__count__corner:nom_tt_025C_1v80,0 |
| 29 | +timing__setup_r2r__ws__corner:nom_tt_025C_1v80,14.516183 |
| 30 | +timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0 |
| 31 | +design__max_slew_violation__count__corner:nom_ss_100C_1v60,0 |
| 32 | +design__max_fanout_violation__count__corner:nom_ss_100C_1v60,3 |
| 33 | +design__max_cap_violation__count__corner:nom_ss_100C_1v60,0 |
| 34 | +clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.26007649547878314 |
| 35 | +clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.26010919154778306 |
| 36 | +timing__hold__ws__corner:nom_ss_100C_1v60,0.9376858444006844 |
| 37 | +timing__setup__ws__corner:nom_ss_100C_1v60,8.293066912366431 |
| 38 | +timing__hold__tns__corner:nom_ss_100C_1v60,0.0 |
| 39 | +timing__setup__tns__corner:nom_ss_100C_1v60,0.0 |
| 40 | +timing__hold__wns__corner:nom_ss_100C_1v60,0 |
| 41 | +timing__setup__wns__corner:nom_ss_100C_1v60,0.0 |
| 42 | +timing__hold_vio__count__corner:nom_ss_100C_1v60,0 |
| 43 | +timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.937686 |
| 44 | +timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0 |
| 45 | +timing__setup_vio__count__corner:nom_ss_100C_1v60,0 |
| 46 | +timing__setup_r2r__ws__corner:nom_ss_100C_1v60,8.293067 |
| 47 | +timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0 |
| 48 | +design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0 |
| 49 | +design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,3 |
| 50 | +design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0 |
| 51 | +clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.2551905425871017 |
| 52 | +clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.25520489222010084 |
| 53 | +timing__hold__ws__corner:nom_ff_n40C_1v95,0.11866208351786166 |
| 54 | +timing__setup__ws__corner:nom_ff_n40C_1v95,14.852757666395513 |
| 55 | +timing__hold__tns__corner:nom_ff_n40C_1v95,0.0 |
| 56 | +timing__setup__tns__corner:nom_ff_n40C_1v95,0.0 |
| 57 | +timing__hold__wns__corner:nom_ff_n40C_1v95,0 |
| 58 | +timing__setup__wns__corner:nom_ff_n40C_1v95,0.0 |
| 59 | +timing__hold_vio__count__corner:nom_ff_n40C_1v95,0 |
| 60 | +timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.118662 |
| 61 | +timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0 |
| 62 | +timing__setup_vio__count__corner:nom_ff_n40C_1v95,0 |
| 63 | +timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,17.020761 |
| 64 | +timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0 |
| 65 | +design__max_slew_violation__count,0 |
| 66 | +design__max_fanout_violation__count,3 |
| 67 | +design__max_cap_violation__count,0 |
| 68 | +clock__skew__worst_hold,-0.2545521643298877 |
| 69 | +clock__skew__worst_setup,0.2545382310305346 |
| 70 | +timing__hold__ws,0.11619544544313942 |
| 71 | +timing__setup__ws,8.18383961540097 |
| 72 | +timing__hold__tns,0.0 |
| 73 | +timing__setup__tns,0.0 |
| 74 | +timing__hold__wns,0 |
| 75 | +timing__setup__wns,0.0 |
| 76 | +timing__hold_vio__count,0 |
| 77 | +timing__hold_r2r__ws,0.116195 |
| 78 | +timing__hold_r2r_vio__count,0 |
| 79 | +timing__setup_vio__count,0 |
| 80 | +timing__setup_r2r__ws,8.183840 |
| 81 | +timing__setup_r2r_vio__count,0 |
| 82 | +design__die__bbox,0.0 0.0 161.0 111.52 |
| 83 | +design__core__bbox,2.76 2.72 158.24 108.8 |
| 84 | +design__io,45 |
| 85 | +design__die__area,17954.7 |
| 86 | +design__core__area,16493.3 |
| 87 | +design__instance__count__stdcell,781 |
| 88 | +design__instance__area__stdcell,5433.96 |
| 89 | +design__instance__count__macros,0 |
| 90 | +design__instance__area__macros,0 |
| 91 | +design__instance__utilization,0.329464 |
| 92 | +design__instance__utilization__stdcell,0.329464 |
| 93 | +design__instance__count__class:inverter,10 |
| 94 | +design__instance__count__class:sequential_cell,68 |
| 95 | +design__instance__count__class:multi_input_combinational_cell,403 |
| 96 | +flow__warnings__count,1 |
| 97 | +flow__errors__count,0 |
| 98 | +design__instance__count__class:fill_cell,1228 |
| 99 | +design__instance__count__class:tap_cell,225 |
| 100 | +design__power_grid_violation__count__net:VPWR,0 |
| 101 | +design__power_grid_violation__count__net:VGND,0 |
| 102 | +design__power_grid_violation__count,0 |
| 103 | +timing__drv__floating__nets,0 |
| 104 | +timing__drv__floating__pins,0 |
| 105 | +design__instance__displacement__total,0 |
| 106 | +design__instance__displacement__mean,0 |
| 107 | +design__instance__displacement__max,0 |
| 108 | +route__wirelength__estimated,9510.85 |
| 109 | +design__violations,0 |
| 110 | +design__instance__count__class:timing_repair_buffer,59 |
| 111 | +design__instance__count__class:clock_buffer,9 |
| 112 | +design__instance__count__class:clock_inverter,7 |
| 113 | +design__instance__count__setup_buffer,0 |
| 114 | +design__instance__count__hold_buffer,31 |
| 115 | +antenna__violating__nets,0 |
| 116 | +antenna__violating__pins,0 |
| 117 | +route__antenna_violation__count,0 |
| 118 | +antenna_diodes_count,0 |
| 119 | +route__net,568 |
| 120 | +route__net__special,2 |
| 121 | +route__drc_errors__iter:1,302 |
| 122 | +route__wirelength__iter:1,11004 |
| 123 | +route__drc_errors__iter:2,138 |
| 124 | +route__wirelength__iter:2,10850 |
| 125 | +route__drc_errors__iter:3,98 |
| 126 | +route__wirelength__iter:3,10782 |
| 127 | +route__drc_errors__iter:4,4 |
| 128 | +route__wirelength__iter:4,10768 |
| 129 | +route__drc_errors__iter:5,4 |
| 130 | +route__wirelength__iter:5,10768 |
| 131 | +route__drc_errors__iter:6,0 |
| 132 | +route__wirelength__iter:6,10779 |
| 133 | +route__drc_errors,0 |
| 134 | +route__wirelength,10779 |
| 135 | +route__vias,3851 |
| 136 | +route__vias__singlecut,3851 |
| 137 | +route__vias__multicut,0 |
| 138 | +design__disconnected_pin__count,17 |
| 139 | +design__critical_disconnected_pin__count,0 |
| 140 | +route__wirelength__max,181.54 |
| 141 | +timing__unannotated_net__count__corner:nom_tt_025C_1v80,42 |
| 142 | +timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0 |
| 143 | +timing__unannotated_net__count__corner:nom_ss_100C_1v60,42 |
| 144 | +timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0 |
| 145 | +timing__unannotated_net__count__corner:nom_ff_n40C_1v95,42 |
| 146 | +timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0 |
| 147 | +design__max_slew_violation__count__corner:min_tt_025C_1v80,0 |
| 148 | +design__max_fanout_violation__count__corner:min_tt_025C_1v80,3 |
| 149 | +design__max_cap_violation__count__corner:min_tt_025C_1v80,0 |
| 150 | +clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.25571143148941194 |
| 151 | +clock__skew__worst_setup__corner:min_tt_025C_1v80,0.2557020223490122 |
| 152 | +timing__hold__ws__corner:min_tt_025C_1v80,0.33635684078923983 |
| 153 | +timing__setup__ws__corner:min_tt_025C_1v80,14.338046711302814 |
| 154 | +timing__hold__tns__corner:min_tt_025C_1v80,0.0 |
| 155 | +timing__setup__tns__corner:min_tt_025C_1v80,0.0 |
| 156 | +timing__hold__wns__corner:min_tt_025C_1v80,0 |
| 157 | +timing__setup__wns__corner:min_tt_025C_1v80,0.0 |
| 158 | +timing__hold_vio__count__corner:min_tt_025C_1v80,0 |
| 159 | +timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.336357 |
| 160 | +timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0 |
| 161 | +timing__setup_vio__count__corner:min_tt_025C_1v80,0 |
| 162 | +timing__setup_r2r__ws__corner:min_tt_025C_1v80,14.576703 |
| 163 | +timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0 |
| 164 | +timing__unannotated_net__count__corner:min_tt_025C_1v80,42 |
| 165 | +timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0 |
| 166 | +design__max_slew_violation__count__corner:min_ss_100C_1v60,0 |
| 167 | +design__max_fanout_violation__count__corner:min_ss_100C_1v60,3 |
| 168 | +design__max_cap_violation__count__corner:min_ss_100C_1v60,0 |
| 169 | +clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.2588837273385433 |
| 170 | +clock__skew__worst_setup__corner:min_ss_100C_1v60,0.2588833942716265 |
| 171 | +timing__hold__ws__corner:min_ss_100C_1v60,0.9341540028148595 |
| 172 | +timing__setup__ws__corner:min_ss_100C_1v60,8.414109647183325 |
| 173 | +timing__hold__tns__corner:min_ss_100C_1v60,0.0 |
| 174 | +timing__setup__tns__corner:min_ss_100C_1v60,0.0 |
| 175 | +timing__hold__wns__corner:min_ss_100C_1v60,0 |
| 176 | +timing__setup__wns__corner:min_ss_100C_1v60,0.0 |
| 177 | +timing__hold_vio__count__corner:min_ss_100C_1v60,0 |
| 178 | +timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.934154 |
| 179 | +timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0 |
| 180 | +timing__setup_vio__count__corner:min_ss_100C_1v60,0 |
| 181 | +timing__setup_r2r__ws__corner:min_ss_100C_1v60,8.414109 |
| 182 | +timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0 |
| 183 | +timing__unannotated_net__count__corner:min_ss_100C_1v60,42 |
| 184 | +timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0 |
| 185 | +design__max_slew_violation__count__corner:min_ff_n40C_1v95,0 |
| 186 | +design__max_fanout_violation__count__corner:min_ff_n40C_1v95,3 |
| 187 | +design__max_cap_violation__count__corner:min_ff_n40C_1v95,0 |
| 188 | +clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.2545521643298877 |
| 189 | +clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.2545382310305346 |
| 190 | +timing__hold__ws__corner:min_ff_n40C_1v95,0.11619544544313942 |
| 191 | +timing__setup__ws__corner:min_ff_n40C_1v95,14.865677998232304 |
| 192 | +timing__hold__tns__corner:min_ff_n40C_1v95,0.0 |
| 193 | +timing__setup__tns__corner:min_ff_n40C_1v95,0.0 |
| 194 | +timing__hold__wns__corner:min_ff_n40C_1v95,0 |
| 195 | +timing__setup__wns__corner:min_ff_n40C_1v95,0.0 |
| 196 | +timing__hold_vio__count__corner:min_ff_n40C_1v95,0 |
| 197 | +timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.116195 |
| 198 | +timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0 |
| 199 | +timing__setup_vio__count__corner:min_ff_n40C_1v95,0 |
| 200 | +timing__setup_r2r__ws__corner:min_ff_n40C_1v95,17.067410 |
| 201 | +timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0 |
| 202 | +timing__unannotated_net__count__corner:min_ff_n40C_1v95,42 |
| 203 | +timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0 |
| 204 | +design__max_slew_violation__count__corner:max_tt_025C_1v80,0 |
| 205 | +design__max_fanout_violation__count__corner:max_tt_025C_1v80,3 |
| 206 | +design__max_cap_violation__count__corner:max_tt_025C_1v80,0 |
| 207 | +clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.2575274788533039 |
| 208 | +clock__skew__worst_setup__corner:max_tt_025C_1v80,0.25758948481098287 |
| 209 | +timing__hold__ws__corner:max_tt_025C_1v80,0.3425105851441719 |
| 210 | +timing__setup__ws__corner:max_tt_025C_1v80,14.291649157523887 |
| 211 | +timing__hold__tns__corner:max_tt_025C_1v80,0.0 |
| 212 | +timing__setup__tns__corner:max_tt_025C_1v80,0.0 |
| 213 | +timing__hold__wns__corner:max_tt_025C_1v80,0 |
| 214 | +timing__setup__wns__corner:max_tt_025C_1v80,0.0 |
| 215 | +timing__hold_vio__count__corner:max_tt_025C_1v80,0 |
| 216 | +timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.342511 |
| 217 | +timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0 |
| 218 | +timing__setup_vio__count__corner:max_tt_025C_1v80,0 |
| 219 | +timing__setup_r2r__ws__corner:max_tt_025C_1v80,14.455412 |
| 220 | +timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0 |
| 221 | +timing__unannotated_net__count__corner:max_tt_025C_1v80,42 |
| 222 | +timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0 |
| 223 | +design__max_slew_violation__count__corner:max_ss_100C_1v60,0 |
| 224 | +design__max_fanout_violation__count__corner:max_ss_100C_1v60,3 |
| 225 | +design__max_cap_violation__count__corner:max_ss_100C_1v60,0 |
| 226 | +clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.26139216531132486 |
| 227 | +clock__skew__worst_setup__corner:max_ss_100C_1v60,0.26147471039554027 |
| 228 | +timing__hold__ws__corner:max_ss_100C_1v60,0.9409516765422858 |
| 229 | +timing__setup__ws__corner:max_ss_100C_1v60,8.18383961540097 |
| 230 | +timing__hold__tns__corner:max_ss_100C_1v60,0.0 |
| 231 | +timing__setup__tns__corner:max_ss_100C_1v60,0.0 |
| 232 | +timing__hold__wns__corner:max_ss_100C_1v60,0 |
| 233 | +timing__setup__wns__corner:max_ss_100C_1v60,0.0 |
| 234 | +timing__hold_vio__count__corner:max_ss_100C_1v60,0 |
| 235 | +timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.940952 |
| 236 | +timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0 |
| 237 | +timing__setup_vio__count__corner:max_ss_100C_1v60,0 |
| 238 | +timing__setup_r2r__ws__corner:max_ss_100C_1v60,8.183840 |
| 239 | +timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0 |
| 240 | +timing__unannotated_net__count__corner:max_ss_100C_1v60,42 |
| 241 | +timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0 |
| 242 | +design__max_slew_violation__count__corner:max_ff_n40C_1v95,0 |
| 243 | +design__max_fanout_violation__count__corner:max_ff_n40C_1v95,3 |
| 244 | +design__max_cap_violation__count__corner:max_ff_n40C_1v95,0 |
| 245 | +clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.2561621542945815 |
| 246 | +clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.2562135576220754 |
| 247 | +timing__hold__ws__corner:max_ff_n40C_1v95,0.12072998498201272 |
| 248 | +timing__setup__ws__corner:max_ff_n40C_1v95,14.83736908666057 |
| 249 | +timing__hold__tns__corner:max_ff_n40C_1v95,0.0 |
| 250 | +timing__setup__tns__corner:max_ff_n40C_1v95,0.0 |
| 251 | +timing__hold__wns__corner:max_ff_n40C_1v95,0 |
| 252 | +timing__setup__wns__corner:max_ff_n40C_1v95,0.0 |
| 253 | +timing__hold_vio__count__corner:max_ff_n40C_1v95,0 |
| 254 | +timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.120730 |
| 255 | +timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0 |
| 256 | +timing__setup_vio__count__corner:max_ff_n40C_1v95,0 |
| 257 | +timing__setup_r2r__ws__corner:max_ff_n40C_1v95,16.976191 |
| 258 | +timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0 |
| 259 | +timing__unannotated_net__count__corner:max_ff_n40C_1v95,42 |
| 260 | +timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0 |
| 261 | +timing__unannotated_net__count,42 |
| 262 | +timing__unannotated_net_filtered__count,0 |
| 263 | +design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79992 |
| 264 | +design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999 |
| 265 | +design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000783889 |
| 266 | +design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000766516 |
| 267 | +design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000110669 |
| 268 | +design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000766516 |
| 269 | +design_powergrid__voltage__worst,0.0000766516 |
| 270 | +design_powergrid__voltage__worst__net:VPWR,1.79992 |
| 271 | +design_powergrid__drop__worst,0.0000783889 |
| 272 | +design_powergrid__drop__worst__net:VPWR,0.0000783889 |
| 273 | +design_powergrid__voltage__worst__net:VGND,0.0000766516 |
| 274 | +design_powergrid__drop__worst__net:VGND,0.0000766516 |
| 275 | +ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125 |
| 276 | +ir__drop__avg,0.00001099999999999999971398746689832393030883395113050937652587890625 |
| 277 | +ir__drop__worst,0.000078399999999999994758186072640882002815487794578075408935546875 |
| 278 | +magic__drc_error__count,0 |
| 279 | +magic__illegal_overlap__count,0 |
| 280 | +design__lvs_device_difference__count,0 |
| 281 | +design__lvs_net_difference__count,0 |
| 282 | +design__lvs_property_fail__count,0 |
| 283 | +design__lvs_error__count,0 |
| 284 | +design__lvs_unmatched_device__count,0 |
| 285 | +design__lvs_unmatched_net__count,0 |
| 286 | +design__lvs_unmatched_pin__count,0 |
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