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feat: update project tt_um_gregac_tiny_nn from GregAC/tt10-tiny-nn
Commit: f025818f4a7c85dc6803ca3644cfdb8717519ec3 Workflow: https://github.com/GregAC/tt10-tiny-nn/actions/runs/13569828002
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‎projects/tt_um_gregac_tiny_nn/LICENSE

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Apache License
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‎projects/tt_um_gregac_tiny_nn/commit_id.json

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{
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"app": "Tiny Tapeout tt10 8f10bc8c",
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"repo": "https://github.com/GregAC/tt10-tiny-nn",
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"commit": "f025818f4a7c85dc6803ca3644cfdb8717519ec3",
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"workflow_url": "https://github.com/GregAC/tt10-tiny-nn/actions/runs/13569828002",
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"sort_id": 1740673201435,
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"openlane_version": "OpenLane2 2.2.9",
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"pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"
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}

‎projects/tt_um_gregac_tiny_nn/docs/info.md

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## How it works
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This project is a neural network accelerator designed for use with convolutional
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neural networks. The verilog is generated from system verilog source which lives
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in a separate repository: https://github.com/GregAC/tiny-nn which also contains
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the full DV environment, model, documentation and related utilities and
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software.
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Internally it contains a number of 16-bit floating point add and multiply units
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(using something approximating the BF16 floating point encoding) that can be
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configured to work in different ways for different operations. Operations
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available are
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- Convolve - Computes a 4x2 convolution kernel across an image. The parameters
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are loaded in and held in flops then the image is streamed in one pixel at a
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time. The most recent 4x2 image pixels are also held in flops so every 2 new
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pixels giving a new image column computes a new convolution (internally the
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last image column is dropped and the new column shifted in).
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- Accumulate - Sum groups of N input numbers with a fixed bias added and an
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optional RELU operation (0 if accumulation less than 0 otherwise leaves
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accumulation untouched). N is provided by the operation word and the bias is
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only loaded in once. E.g. if you set N = 4 an bias of 1.0 for each 4 numbers
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input it would sum them together then add the bias and do the optional RELU.
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Numbers keep streaming in until the operation is terminated
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The interface is a fixed 16 bits in and 8 bits out synchronous to the clock.
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Each operation has a special operand code that starts it that needs to be sent
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on the 16 input bits. Once started the 16 input bits provide the numbers used
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for the operation.
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The 16-bit numbers output are split over 2 clock cycles for the 8 bit output.
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With the lower byte output first. The user needs to know when the output is
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relevant (some cycles the output should be ignored and some it should be
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captured).
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- ui_in, uio_in - 16-bit input, ui_in is top byte
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- uio_out - 8-bit output
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https://github.com/GregAC/tiny-nn should contain full documentation with the
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details and software to use the accelerator (both a work in progress at tapeout
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time!).
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## How to test
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The simplest operation is the accumulate one. We'll configure it to add two
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numbers at a time with a -3.5 bias and RELU. Then we'll add 1.0 + 2.0 and 3.0 +
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4.0. Put the following on the input over successive clocks
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- 16'h2101 # Command word for accumulate operation
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- 16'hc060 # -3.5 bias
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- 16'h3f80 # 1.0
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- 16'h4000 # 2.0
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- 16'h4040 # 3.0
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- 16'h4080 # 4.0
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- 16'hffff # NaN - terminates operation
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On the output you should observe:
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- 16'hX
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- 16'hX
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- 16'hX
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- 16'hX
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- 16'h00
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- 16'h00
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- 16'h60
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- 16'h40
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The 16'hX outputs could be anything and should be ignored, the first number
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output is 0000 representing 0.0 RELU(1.0 + 2.0 - 3.5) = 0.0, the second number
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output is 4060 representing 3.5 RELU(3.0 + 4.0 - 3.5) = 3.5.
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## External hardware
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No specific external hardware required but it does need some external part to
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drive the desired sequences, this can be handled by the RP2040 on the demo
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board.

‎projects/tt_um_gregac_tiny_nn/info.yaml

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# Tiny Tapeout project information
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project:
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title: "Tiny Neural Network Accelerator" # Project title
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author: "Greg Chadwick" # Your name
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discord: "gregac" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
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description: "A toy neural network accelerator targetting CNNs" # One line description of what your project does
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language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
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clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)
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# How many tiles your design occupies? A single tile is about 167x108 uM.
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tiles: "4x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
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# Your top module name must start with "tt_um_". Make it unique by including your github username:
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top_module: "tt_um_gregac_tiny_nn"
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# List your project's source files here.
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# Source files must be in ./src and you must list each source file separately, one per line.
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# Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
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source_files:
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- "project.v"
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- "tiny_nn.v"
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# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
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pinout:
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# Inputs
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ui[0]: "ui[0]"
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ui[1]: "ui[1]"
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ui[2]: "ui[2]"
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ui[3]: "ui[3]"
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ui[4]: "ui[4]"
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ui[5]: "ui[5]"
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ui[6]: "ui[6]"
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ui[7]: "ui[7]"
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# Outputs
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uo[0]: "uo[0]"
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uo[1]: "uo[1]"
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uo[2]: "uo[2]"
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uo[3]: "uo[3]"
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uo[4]: "uo[4]"
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uo[5]: "uo[5]"
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uo[6]: "uo[6]"
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uo[7]: "uo[7]"
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# Bidirectional pins
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uio[0]: "uio[0]"
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uio[1]: "uio[1]"
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uio[2]: "uio[2]"
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uio[3]: "uio[3]"
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uio[4]: "uio[4]"
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uio[5]: "uio[5]"
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uio[6]: "uio[6]"
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uio[7]: "uio[7]"
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# Do not change!
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yaml_version: 6

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