Deliverables
- Submit a PR on fixing the runtime wrong-result bug in the Triton RISC-V swap example.
- Include focused pytest evidence showing that
python/examples/test_swap.py::test passes and that both swapped tensors match the expected originals.
Background
The current repository has a runtime correctness failure in test_swap.py. The first assertion confirms that x receives the original y, but the second assertion fails because y does not receive the original x:
assert torch.equal(y, x_)
E assert False
Unlike the compiler failures, this case reaches execution and produces an incorrect result, so it should be treated as a generated-code or memory-aliasing correctness bug.
Task Description
- Reproduce from the
triton-riscv repository root:
cd python/examples
pytest -q test_swap.py::test
- Inspect
test_swap.py and the generated IR/object behavior for the swap kernel to determine whether the failure is caused by load/store ordering, aliasing, vectorization, or backend memory lowering.
- Implement the minimal fix that preserves both values during the swap and does not rely on changing the test expectation.
- Run the focused pytest case above and one nearby load/store or vector add example to check for shared memory-lowering regressions.
- In the PR description, include before/after pytest output and the root cause of the incorrect
y value.
Deliverables
python/examples/test_swap.py::testpasses and that both swapped tensors match the expected originals.Background
The current repository has a runtime correctness failure in
test_swap.py. The first assertion confirms thatxreceives the originaly, but the second assertion fails becauseydoes not receive the originalx:Unlike the compiler failures, this case reaches execution and produces an incorrect result, so it should be treated as a generated-code or memory-aliasing correctness bug.
Task Description
triton-riscvrepository root:cd python/examples pytest -q test_swap.py::testtest_swap.pyand the generated IR/object behavior for the swap kernel to determine whether the failure is caused by load/store ordering, aliasing, vectorization, or backend memory lowering.yvalue.