From 94865b3a6a012b8d6ba0378009fd3a3bfdade5f7 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Tue, 20 Oct 2026 09:29:01 +0200 Subject: [PATCH] cpu/esp32: enable SPI RAM cache workaround for ESP32 CONFIG_SPIRAM_CACHE_WORKAROUND is defined in sdkconfig_esp32.h, but the corresponding compiler and linker flags were never used. ESP-IDF compiles all code with `-mfix-esp32-psram-cache-issue` and links the libc/libgcc multilib variants built with this workaround if SPI RAM is used on ESP32. Without it, writes to SPI RAM can get lost on ESP32 revisions < 3 when an interrupt occurs while a cache line is fetched, which corrupts e.g. the TLSF block headers of the heap in SPI RAM. Assisted-by: Claude Code Opus 5.5 --- cpu/esp32/Makefile.include | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/cpu/esp32/Makefile.include b/cpu/esp32/Makefile.include index 4beb14a885a0..c47288ce9744 100644 --- a/cpu/esp32/Makefile.include +++ b/cpu/esp32/Makefile.include @@ -203,6 +203,16 @@ endif ifneq (,$(filter esp_spi_ram,$(USEMODULE))) INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_psram/include + ifeq (esp32,$(CPU_FAM)) + # Workaround for the SPI RAM cache bug of ESP32 revisions < 3 + # (CONFIG_SPIRAM_CACHE_WORKAROUND): The compiler avoids the vulnerable + # instruction sequences, and the linker uses the multilib variants of + # libc and libgcc that are compiled with this workaround. + PSRAM_WORKAROUND_FLAGS = -mfix-esp32-psram-cache-issue + PSRAM_WORKAROUND_FLAGS += -mfix-esp32-psram-cache-strategy=memw + CFLAGS += $(PSRAM_WORKAROUND_FLAGS) + LINKFLAGS += $(PSRAM_WORKAROUND_FLAGS) + endif endif ifneq (,$(filter esp_idf_lcd,$(USEMODULE)))