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Prajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 s…

verilog

microprocessor

vivado

fibonacci-numbers

7-segment

• Tcl
·
• 5
·
• Updated
  on Dec 7, 2022

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