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2075 lines (2054 loc) · 72.9 KB
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Index: include/VBox/vmm/pdmiceifs.h
===================================================================
--- include/VBox/vmm/pdmiceifs.h (nicht existent)
+++ include/VBox/vmm/pdmiceifs.h (Arbeitskopie)
@@ -0,0 +1,149 @@
+/** @file
+ * PDM - Pluggable Device Manager, In-Circuit emulator related interfaces.
+ */
+
+/*
+ * Copyright (C) 2020 Oracle Corporation
+ *
+ * This file is part of VirtualBox Open Source Edition (OSE), as
+ * available from http://www.virtualbox.org. This file is free software;
+ * you can redistribute it and/or modify it under the terms of the GNU
+ * General Public License (GPL) as published by the Free Software
+ * Foundation, in version 2 as it comes in the "COPYING" file of the
+ * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
+ * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
+ *
+ * The contents of this file may alternatively be used under the terms
+ * of the Common Development and Distribution License Version 1.0
+ * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
+ * VirtualBox OSE distribution, in which case the provisions of the
+ * CDDL are applicable instead of those of the GPL.
+ *
+ * You may elect to license modified versions of this file under the
+ * terms and conditions of either the GPL or the CDDL or both.
+ */
+
+#ifndef VBOX_INCLUDED_vmm_pdmiceifs_h
+#define VBOX_INCLUDED_vmm_pdmiceifs_h
+#ifndef RT_WITHOUT_PRAGMA_ONCE
+# pragma once
+#endif
+
+#include <VBox/types.h>
+
+RT_C_DECLS_BEGIN
+
+/** @defgroup grp_pdm_ifs_ice PDM In-Circuit emulator Interfaces
+ * @ingroup grp_pdm_interfaces
+ * @{
+ */
+
+
+/**
+ * The memory type.
+ */
+typedef enum PDMIICEMEMTYPE
+{
+ /** Invalid memory type. */
+ PDMIICEMEMTYPE_INVALID = 0,
+ /** RAM type. */
+ PDMIICEMEMTYPE_RAM,
+ /** MMIO type. */
+ PDMIICEMEMTYPE_MMIO,
+ /** Unknown memory type, some guesses have to be made which might fail. */
+ PDMIICEMEMTYPE_UNKNONWN,
+ /** 32bit hack. */
+ PDMIICEMEMTYPE_32BIT_HACK = 0x7fffffff
+} PDMIICEMEMTYPE;
+
+
+/** Pointer to an ICE interface. */
+typedef struct PDMIICE *PPDMIICE;
+/**
+ * ICE interface (down).
+ */
+typedef struct PDMIICE
+{
+ /**
+ * Reads from the given I/O port.
+ *
+ * @returns VBox status code.
+ * @param pInterface Pointer to the interface structure containing the called function pointer.
+ * @param IoPort The I/O port to read from.
+ * @param cb Access width in bytes.
+ * @param pu32 Where to store the read data.
+ */
+ DECLR3CALLBACKMEMBER(int, pfnIoPortRead, (PPDMIICE pInterface, RTIOPORT IoPort, size_t cb, uint32_t *pu32));
+
+
+ /**
+ * Writes to the given I/O port.
+ *
+ * @returns VBox status code.
+ * @param pInterface Pointer to the interface structure containing the called function pointer.
+ * @param IoPort The I/O port to write to.
+ * @param cb Access width in bytes.
+ * @param u32 The data to write.
+ */
+ DECLR3CALLBACKMEMBER(int, pfnIoPortWrite, (PPDMIICE pInterface, RTIOPORT IoPort, size_t cb, uint32_t u32));
+
+
+ /**
+ * Reads the given amount of memory starting from the given guest physical address.
+ *
+ * @returns VBox status code.
+ * @param pInterface Pointer to the interface structure containing the called function pointer.
+ * @param GCPhysStart The guest physical address to start reading from.
+ * @param enmMemType The accessed memory type.
+ * @param cbRead Number of bytes to read.
+ * @param pvBuf Where to store the read data.
+ */
+ DECLR3CALLBACKMEMBER(int, pfnMemRead, (PPDMIICE pInterface, RTGCPHYS GCPhysStart, PDMIICEMEMTYPE enmMemType,
+ size_t cbRead, void *pvBuf));
+
+
+ /**
+ * Writes the given amount of memory starting from the given guest physical address.
+ *
+ * @returns VBox status code.
+ * @param pInterface Pointer to the interface structure containing the called function pointer.
+ * @param GCPhysStart The guest physical address to start writing to.
+ * @param enmMemType The accessed memory type.
+ * @param cbWrite Number of bytes to write.
+ * @param pvBuf The data to write.
+ */
+ DECLR3CALLBACKMEMBER(int, pfnMemWrite, (PPDMIICE pInterface, RTGCPHYS GCPhysStart, PDMIICEMEMTYPE enmMemType,
+ size_t cbWrite, const void *pvBuf));
+
+
+ /**
+ * Reads the given MSR.
+ *
+ * @returns VBox status code.
+ * @param pInterface Pointer to the interface structure containing the called function pointer.
+ * @param idMsr The MSR to read.
+ * @param pu64Val Where to store the read value upon success.
+ */
+ DECLR3CALLBACKMEMBER(int, pfnMsrRead, (PPDMIICE pInterface, uint32_t idMsr, uint64_t *pu64Val));
+
+
+ /**
+ * Writes the given MSR.
+ *
+ * @returns VBox status code.
+ * @param pInterface Pointer to the interface structure containing the called function pointer.
+ * @param idMsr The MSR to write.
+ * @param u64Val The value to write.
+ */
+ DECLR3CALLBACKMEMBER(int, pfnMsrWrite, (PPDMIICE pInterface, uint32_t idMsr, uint64_t u64Val));
+
+} PDMIICE;
+/** PDMIICE interface ID. */
+#define PDMIICE_IID "13abdd9a-f039-41dc-a720-48276083e4df"
+
+
+/** @} */
+
+RT_C_DECLS_END
+
+#endif /* !VBOX_INCLUDED_vmm_pdmiceifs_h */
Property changes on: include/VBox/vmm/pdmiceifs.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Author Date Id Revision
\ No newline at end of property
Added: svn:sync-process
## -0,0 +1 ##
+export
\ No newline at end of property
Index: include/VBox/vmm/cpum.h
===================================================================
--- include/VBox/vmm/cpum.h (Revision 139592)
+++ include/VBox/vmm/cpum.h (Arbeitskopie)
@@ -2647,6 +2647,39 @@
VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
+/**
+ * CPUM MSR read handler.
+ *
+ * @returns VBox status code.
+ * @retval VINF_CPUM_MSR_READ_DO_DEFAULT when the internal MSR read handler should be called.
+ *
+ * @param pVM Pointer to the cross context VM structure.
+ * @param idMsr The MSR to read.
+ * @param pu64Val Where to store the value on return.
+ * @param pvUser Opaque user data passed during registration.
+ */
+typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMMSRREAD,(PVM pVM, uint32_t idMsr, uint64_t *pu64Val, void *pvUser));
+/** Pointer to a FNCPUMMSRREAD. */
+typedef FNCPUMMSRREAD *PFNCPUMMSRREAD;
+
+/**
+ * CPUM MSR write handler.
+ *
+ * @returns VBox status code.
+ * @retval VINF_CPUM_MSR_WRITE_DO_DEFAULT when the internal MSR write handler should be called.
+ *
+ * @param pVM Pointer to the cross context VM structure.
+ * @param idMsr The MSR to write.
+ * @param u64Val The value to write.
+ * @param pvUser Opaque user data passed during registration.
+ */
+typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMMSRWRITE,(PVM pVM, uint32_t idMsr, uint64_t u64Val, void *pvUser));
+/** Pointer to a FNCPUMMSRWRITE. */
+typedef FNCPUMMSRWRITE *PFNCPUMMSRWRITE;
+
+VMMR3DECL(int) CPUMR3MsrRwInterceptSet(PVM pVM, PFNCPUMMSRREAD pfnMsrRead, PFNCPUMMSRWRITE pfnMsrWrite,
+ void *pvUser);
+
/** @} */
#endif /* IN_RING3 */
Index: src/VBox/Devices/Misc/DevIce.cpp
===================================================================
--- src/VBox/Devices/Misc/DevIce.cpp (nicht existent)
+++ src/VBox/Devices/Misc/DevIce.cpp (Arbeitskopie)
@@ -0,0 +1,609 @@
+/* $Id$ */
+/** @file
+ * ICE - In-Circuit Emulator device for hypervisor assisted x86 firmware development
+ */
+
+/*
+ * Copyright (C) 2020 Oracle Corporation
+ *
+ * This file is part of VirtualBox Open Source Edition (OSE), as
+ * available from http://www.virtualbox.org. This file is free software;
+ * you can redistribute it and/or modify it under the terms of the GNU
+ * General Public License (GPL) as published by the Free Software
+ * Foundation, in version 2 as it comes in the "COPYING" file of the
+ * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
+ * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
+ */
+
+
+/*********************************************************************************************************************************
+* Header Files *
+*********************************************************************************************************************************/
+#define LOG_GROUP LOG_GROUP_DEV // LOG_GROUP_DEV_ICE
+#include <VBox/vmm/pdmdev.h>
+#include <VBox/vmm/pdmifs.h>
+#include <VBox/vmm/pdmiceifs.h>
+#include <VBox/vmm/cpum.h>
+#include <VBox/log.h>
+#include <iprt/assert.h>
+#include <iprt/file.h>
+#include <iprt/list.h>
+#include <iprt/mem.h>
+#include <iprt/path.h>
+#include <iprt/uuid.h>
+#include <iprt/x86.h>
+
+#include "VBoxDD.h"
+
+
+/*********************************************************************************************************************************
+* Defined Constants And Macros *
+*********************************************************************************************************************************/
+
+/** Maximum number of ports in one I/O port mapping. */
+#define ICE_IO_PORT_MAPPING_MAX _4K
+
+
+/*********************************************************************************************************************************
+* Structures and Typedefs *
+*********************************************************************************************************************************/
+
+/** Pointer to the device instance data. */
+typedef struct ICE *PICE;
+
+
+/**
+ * I/O port mapping range.
+ */
+typedef struct ICEIOPORTMAPPING
+{
+ /** The first I/O port mapped. */
+ RTIOPORT IoPortBase;
+ /** Number of I/O ports mapped. */
+ RTIOPORT cIoPorts;
+ /** The I/O port handle. */
+ IOMIOPORTHANDLE hIoPorts;
+} ICEIOPORTMAPPING;
+/** Pointer to an ICE I/O port mapping. */
+typedef ICEIOPORTMAPPING *PICEIOPORTMAPPING;
+
+
+/**
+ * MMIO mapping.
+ */
+typedef struct ICEMMIOMAPPING
+{
+ /** Node for list of mappings. */
+ RTLISTNODE NdMmio;
+ /** Guest physical address of the region. */
+ RTGCPHYS GCPhysStart;
+ /** Size of the region. */
+ size_t cbRegion;
+ /** MMIO region handle. */
+ IOMMMIOHANDLE hMmio;
+ /** Mapping description, free with RTStrFree(). */
+ char *pszDesc;
+} ICEMMIOMAPPING;
+/** Pointer to an MMIO mapping descriptor. */
+typedef ICEMMIOMAPPING *PICEMMIOMAPPING;
+
+
+/**
+ * ICE device instance data.
+ */
+typedef struct ICE
+{
+ /** Pointer to the NVMe device instance. */
+ PPDMDEVINS pDevIns;
+
+ /** The system ROM data. */
+ uint8_t const *pu8Rom;
+ /** The system ROM data pointer to be passed to RTFileReadAllFree. */
+ uint8_t *pu8RomFree;
+ /** The size of the system ROM. */
+ size_t cbRom;
+ /** Where the ROM is initially loaded. */
+ RTGCPHYS GCPhysRom;
+ /** Head of list of MMIO mappings. */
+ RTLISTANCHOR LstMmio;
+
+ /** I/O port mappings. */
+ ICEIOPORTMAPPING aIoPorts[65536 / ICE_IO_PORT_MAPPING_MAX]; /* IOM allows mapping 8K ports in one go (sanity checks). */
+ /** The lower ICE driver interface. */
+ PPDMIICE pIfsIce;
+
+ /** @name ICE related interface (R3 only stuff).
+ * @{ */
+ /** Pointer to the attached driver's base interface. */
+ R3PTRTYPE(PPDMIBASE) pDrvBase;
+ /** Pointer to the attached driver's ICE interface. */
+ R3PTRTYPE(PPDMIICE) pDrvIce;
+
+ /** The base interface. */
+ PDMIBASE IBase;
+ /** @} */
+} ICE;
+/** Pointer to const device instance data. */
+typedef const ICE *PCICE;
+
+
+
+static DECLCALLBACK(VBOXSTRICTRC) icePortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
+{
+ PICE pThis = PDMDEVINS_2_DATA(pDevIns, PICE);
+ PICEIOPORTMAPPING pIoPortMapping = (PICEIOPORTMAPPING)pvUser;
+
+ int rc = VINF_SUCCESS;
+ if (pThis->pDrvIce)
+ rc = pThis->pDrvIce->pfnIoPortRead(pThis->pDrvIce, pIoPortMapping->IoPortBase + offPort, cb, pu32);
+ else
+ *pu32 = UINT32_C(0xffffffff);
+
+ LogFlowFunc(("ICE: I/O port read at %RTiop %zu -> %Rrc (%#x)\n", pIoPortMapping->IoPortBase + offPort, cb, rc, *pu32));
+ return rc;
+}
+
+
+static DECLCALLBACK(VBOXSTRICTRC) icePortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
+{
+ PICE pThis = PDMDEVINS_2_DATA(pDevIns, PICE);
+ PICEIOPORTMAPPING pIoPortMapping = (PICEIOPORTMAPPING)pvUser;
+
+ int rc = VINF_SUCCESS;
+ if (pThis->pDrvIce)
+ rc = pThis->pDrvIce->pfnIoPortWrite(pThis->pDrvIce, pIoPortMapping->IoPortBase + offPort, cb, u32);
+
+ LogFlowFunc(("I/O port write at %RTiop %zu %#x -> %Rrc\n", pIoPortMapping->IoPortBase + offPort, cb, u32, rc));
+ return rc;
+}
+
+
+/**
+ * @callback_method_impl{FNIOMMMIONEWWRITE, ICE MMIO write}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) iceR3MmioMappingWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
+{
+ PICE pThis = PDMDEVINS_2_DATA(pDevIns, PICE);
+ PICEMMIOMAPPING pMmio = (PICEMMIOMAPPING)pvUser;
+
+#if 1
+ int rc = VINF_SUCCESS;
+ if (pThis->pDrvIce)
+ rc = pThis->pDrvIce->pfnMemWrite(pThis->pDrvIce, pMmio->GCPhysStart + off, PDMIICEMEMTYPE_MMIO, cb, pv);
+#else
+ RT_NOREF(pThis, pMmio, pvUser, off, pv, cb);
+ int rc = VINF_SUCCESS;
+ AssertReleaseFailed();
+#endif
+
+ return rc;
+}
+
+
+/**
+ * @callback_method_impl{FNIOMMMIONEWREAD, ICE MMIO read}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) iceR3MmioMappingRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
+{
+ PICE pThis = PDMDEVINS_2_DATA(pDevIns, PICE);
+ PICEMMIOMAPPING pMmio = (PICEMMIOMAPPING)pvUser;
+
+#if 1
+ int rc = VINF_SUCCESS;
+ if (pThis->pDrvIce)
+ rc = pThis->pDrvIce->pfnMemRead(pThis->pDrvIce, pMmio->GCPhysStart + off, PDMIICEMEMTYPE_MMIO, cb, pv);
+#else
+ RT_NOREF(pThis, pMmio, pvUser, off, pv, cb);
+ int rc = VINF_SUCCESS;
+ AssertReleaseFailed();
+#endif
+
+ return rc;
+}
+
+
+/**
+ * @callback_method_impl{FNCPUMMSRREAD, ICE MSR read}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) iceR3MsrRead(PVM pVM, uint32_t idMsr, uint64_t *pu64Val, void *pvUser)
+{
+ RT_NOREF(pVM);
+
+ int rc = VINF_CPUM_MSR_READ_DO_DEFAULT;
+ PICE pThis = (PICE)pvUser;
+
+ if (pThis->pDrvIce->pfnMsrRead)
+ rc = pThis->pDrvIce->pfnMsrRead(pThis->pDrvIce, idMsr, pu64Val);
+ if (RT_SUCCESS(rc) && idMsr == MSR_IA32_APICBASE)
+ rc = VINF_CPUM_MSR_READ_DO_DEFAULT;
+ return rc;
+}
+
+
+/**
+ * @callback_method_impl{FNCPUMMSRWRITE, ICE MSR write}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) iceR3MsrWrite(PVM pVM, uint32_t idMsr, uint64_t u64Val, void *pvUser)
+{
+ RT_NOREF(pVM);
+
+ int rc = VINF_CPUM_MSR_WRITE_DO_DEFAULT;
+ PICE pThis = (PICE)pvUser;
+
+ if (pThis->pDrvIce->pfnMsrWrite)
+ rc = pThis->pDrvIce->pfnMsrWrite(pThis->pDrvIce, idMsr, u64Val);
+ if (RT_SUCCESS(rc) && idMsr == MSR_IA32_APICBASE)
+ rc = VINF_CPUM_MSR_WRITE_DO_DEFAULT;
+ return rc;
+
+}
+
+
+/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
+
+/**
+ * @interface_method_impl{PDMIBASE,pfnQueryInterface}
+ */
+static DECLCALLBACK(void *) iceR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
+{
+ PICE pThis = RT_FROM_MEMBER(pInterface, ICE, IBase);
+ PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
+ return NULL;
+}
+
+
+/**
+ * @interface_method_impl{PDMDEVREG,pfnMemSetup}
+ */
+static DECLCALLBACK(void) iceR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
+{
+ RT_NOREF(enmCtx);
+ PICE pThis = PDMDEVINS_2_DATA(pDevIns, PICE);
+ PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
+
+ uint32_t cPages = RT_ALIGN_64(pThis->cbRom, PAGE_SIZE) >> PAGE_SHIFT;
+ RTGCPHYS GCPhys = pThis->GCPhysRom;
+ while (cPages > 0)
+ {
+ uint8_t abPage[PAGE_SIZE];
+
+ /* Read the (original) ROM page and write it back to the RAM page. */
+ int rc = PDMDevHlpROMProtectShadow(pDevIns, GCPhys, PAGE_SIZE, PGMROMPROT_READ_ROM_WRITE_RAM);
+ AssertLogRelRC(rc);
+
+ rc = PDMDevHlpPhysRead(pDevIns, GCPhys, abPage, PAGE_SIZE);
+ AssertLogRelRC(rc);
+ if (RT_FAILURE(rc))
+ memset(abPage, 0xcc, sizeof(abPage));
+
+ rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, abPage, PAGE_SIZE);
+ AssertLogRelRC(rc);
+
+ /* Switch to the RAM/RAM mode. */
+ rc = PDMDevHlpROMProtectShadow(pDevIns, GCPhys, PAGE_SIZE, PGMROMPROT_READ_RAM_WRITE_RAM);
+ AssertLogRelRC(rc);
+
+ /* Advance */
+ GCPhys += PAGE_SIZE;
+ cPages--;
+ }
+
+ /* Syncing makes only sense if there is a driver. */
+ if (pThis->pDrvIce)
+ {
+ /*
+ * Check for any RAM ranges we have to sync.
+ */
+ PCFGMNODE pCfgmMemSync = pHlp->pfnCFGMGetChild(pDevIns->pCfg, "MemSync");
+ if (pCfgmMemSync)
+ {
+ int rc = VINF_SUCCESS;
+
+ for (PCFGMNODE pNd = pHlp->pfnCFGMGetFirstChild(pCfgmMemSync); pNd && RT_SUCCESS(rc); pNd = pHlp->pfnCFGMGetNextChild(pNd))
+ {
+ char szName[32];
+ rc = pHlp->pfnCFGMGetName(pNd, &szName[0], sizeof(szName));
+ AssertMsgRCReturnVoid(rc, ("Configuration error: Range name is too long (or something)! rc=%Rrc\n", rc));
+
+ RTGCPHYS GCPhysStart = NIL_RTGCPHYS;
+ rc = pHlp->pfnCFGMQueryU64(pNd, "PhysicalStart", &GCPhysStart);
+ AssertMsgRCReturnVoid(rc, ("Configuration error: Querying \"PhysicalStart\" failed! rc=%Rrc\n", rc));
+
+ uint32_t cbSync = 0;
+ rc = pHlp->pfnCFGMQueryU32(pNd, "Size", &cbSync);
+ AssertMsgRCReturnVoid(rc, ("Configuration error: Querying \"Size\" failed! rc=%Rrc\n", rc));
+
+ LogRel(("ICE: Syncing RAM range %RGp - %RGp (%zu bytes)\n", GCPhysStart, GCPhysStart + cbSync - 1, cbSync));
+
+ while (cbSync)
+ {
+ uint8_t abSync[_1K];
+ size_t cbThisSync = RT_MIN(cbSync, sizeof(abSync));
+
+ rc = pThis->pDrvIce->pfnMemRead(pThis->pDrvIce, GCPhysStart, PDMIICEMEMTYPE_RAM, cbThisSync, &abSync[0]);
+ AssertMsgRCReturnVoid(rc, ("Reading %zu bytes of memory at %RGp failed! rc=%Rrc\n", cbThisSync, GCPhysStart, rc));
+
+ PDMDevHlpPhysWrite(pDevIns, GCPhysStart, &abSync[0], cbThisSync);
+ GCPhysStart += cbThisSync;
+ cbSync -= cbThisSync;
+ }
+ }
+ }
+ }
+}
+
+
+/**
+ * @interface_method_impl{PDMDEVREG,pfnDestruct}
+ */
+static DECLCALLBACK(int) iceR3Destruct(PPDMDEVINS pDevIns)
+{
+ PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
+ PICE pThis = PDMDEVINS_2_DATA(pDevIns, PICE);
+
+ if (pThis->pu8RomFree)
+ {
+ RTFileReadAllFree(pThis->pu8RomFree, pThis->cbRom);
+ pThis->pu8RomFree = NULL;
+ }
+
+ return VINF_SUCCESS;
+}
+
+
+/**
+ * @interface_method_impl{PDMDEVREG,pfnConstruct}
+ */
+static DECLCALLBACK(int) iceR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
+{
+ PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
+ PICE pThis = PDMDEVINS_2_DATA(pDevIns, PICE);
+ PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
+
+ pThis->pDevIns = pDevIns;
+ pThis->IBase.pfnQueryInterface = iceR3QueryInterface;
+
+ RTListInit(&pThis->LstMmio);
+
+ /*
+ * Validate and read the configuration.
+ */
+ PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
+ "RomImage|"
+ "RomLoadAddr|"
+ "MapBelow4GB|",
+ "MemSync|"
+ "MmioRanges");
+
+ char *pszRomImg = NULL;
+ int rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "RomImage", &pszRomImg);
+ if (RT_SUCCESS(rc))
+ {
+ /* Try setting up the ROM image. */
+ bool fMapBelow4GB;
+ rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "MapBelow4GB", &fMapBelow4GB, true);
+ if (RT_FAILURE(rc))
+ return PDMDEV_SET_ERROR(pDevIns, rc,
+ N_("Configuration error: Querying \"MapTop64KBelow4GB\" failed"));
+
+ rc = pHlp->pfnCFGMQueryU64(pCfg, "RomLoadAddr", &pThis->GCPhysRom);
+ if (RT_SUCCESS(rc))
+ {
+ void *pvFile;
+ size_t cbFile;
+ rc = RTFileReadAllEx(pszRomImg,
+ 0 /*off*/,
+ RTFOFF_MAX /*cbMax*/,
+ RTFILE_RDALL_O_DENY_WRITE,
+ &pvFile,
+ &cbFile);
+ if (RT_FAILURE(rc))
+ return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
+ N_("Loading the ROM image '%s' failed with rc=%Rrc"),
+ pszRomImg, rc);
+ pThis->pu8RomFree = (uint8_t *)pvFile;
+ pThis->pu8Rom = (uint8_t *)pvFile;
+ pThis->cbRom = cbFile;
+
+ /* Register the ROM image. */
+ rc = PDMDevHlpROMRegister(pDevIns, pThis->GCPhysRom, pThis->cbRom, pThis->pu8Rom, pThis->cbRom,
+ PGMPHYS_ROM_FLAGS_SHADOWED | PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ICERomImg");
+ AssertRCReturn(rc, rc);
+
+ rc = PDMDevHlpROMProtectShadow(pDevIns, pThis->GCPhysRom, (uint32_t)pThis->cbRom, PGMROMPROT_READ_RAM_WRITE_RAM);
+ AssertRCReturn(rc, rc);
+
+ if (fMapBelow4GB)
+ {
+ /* We will map the the image just below the 4GB limit where the reset vector will be executed. */
+ rc = PDMDevHlpROMRegister(pDevIns, _4G - pThis->cbRom, pThis->cbRom, pThis->pu8Rom, pThis->cbRom,
+ PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ICERomImgTop");
+ AssertRCReturn(rc, rc);
+
+ rc = PDMDevHlpROMProtectShadow(pDevIns, _4G - pThis->cbRom, (uint32_t)pThis->cbRom, PGMROMPROT_READ_RAM_WRITE_IGNORE);
+ AssertRCReturn(rc, rc);
+ }
+ }
+ else
+ return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
+ N_("Configuration error: Querying \"RomLoadAddr\" as a physical guest address failed"));
+
+ MMR3HeapFree(pszRomImg);
+ }
+ else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
+ return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
+ N_("Configuration error: Querying \"RomImage\" as a string failed"));
+
+
+ for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aIoPorts); i++)
+ {
+ PICEIOPORTMAPPING pIoPortMapping = &pThis->aIoPorts[i];
+
+ pIoPortMapping->IoPortBase = i * ICE_IO_PORT_MAPPING_MAX;
+ pIoPortMapping->cIoPorts = ICE_IO_PORT_MAPPING_MAX;
+ rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, pIoPortMapping->IoPortBase, pIoPortMapping->cIoPorts,
+ icePortWrite, icePortRead, pIoPortMapping,
+ "ICE", NULL /*paExtDescs*/, &pIoPortMapping->hIoPorts);
+ AssertRCReturn(rc, rc);
+ }
+
+ /*
+ * Register MMIO ranges.
+ */
+ PCFGMNODE pCfgmMmio = pHlp->pfnCFGMGetChild(pDevIns->pCfg, "MmioRanges");
+ if (pCfgmMmio)
+ {
+ for (PCFGMNODE pNd = pHlp->pfnCFGMGetFirstChild(pCfgmMmio); pNd && RT_SUCCESS(rc); pNd = pHlp->pfnCFGMGetNextChild(pNd))
+ {
+ char szName[32];
+ rc = pHlp->pfnCFGMGetName(pNd, &szName[0], sizeof(szName));
+ AssertMsgRCReturn(rc, ("Configuration error: Range name is too long (or something)! rc=%Rrc\n", rc), rc);
+
+ RTGCPHYS GCPhysStart = NIL_RTGCPHYS;
+ rc = pHlp->pfnCFGMQueryU64(pNd, "PhysicalStart", &GCPhysStart);
+ AssertMsgRCReturn(rc, ("Configuration error: Querying \"PhysicalStart\" failed! rc=%Rrc\n", rc), rc);
+
+ uint32_t cbMmio = 0;
+ rc = pHlp->pfnCFGMQueryU32(pNd, "Size", &cbMmio);
+ AssertMsgRCReturn(rc, ("Configuration error: Querying \"Size\" failed! rc=%Rrc\n", rc), rc);
+
+ LogRel(("ICE: Creating MMIO range %RGp - %RGp (%zu bytes)\n", GCPhysStart, GCPhysStart + cbMmio - 1, cbMmio));
+
+ PICEMMIOMAPPING pMmioMapping = (PICEMMIOMAPPING)RTMemAllocZ(sizeof(*pMmioMapping));
+ if (pMmioMapping)
+ {
+ pMmioMapping->pszDesc = RTStrDup(&szName[0]);
+ if (pMmioMapping->pszDesc)
+ {
+ rc = PDMDevHlpMmioCreateEx(pDevIns, cbMmio, IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
+ NULL /*pPciDev*/, UINT32_MAX, iceR3MmioMappingWrite, iceR3MmioMappingRead, NULL, pMmioMapping,
+ pMmioMapping->pszDesc, &pMmioMapping->hMmio);
+ AssertRCReturn(rc, rc);
+ rc = PDMDevHlpMmioMap(pDevIns, pMmioMapping->hMmio, GCPhysStart);
+ AssertRCReturn(rc, rc);
+
+ pMmioMapping->GCPhysStart = GCPhysStart;
+ pMmioMapping->cbRegion = cbMmio;
+ RTListAppend(&pThis->LstMmio, &pMmioMapping->NdMmio);
+ }
+ else
+ AssertLogRelMsgFailedReturn(("Configuration error: Failed to allocate memory for MMIO mapping name!\n"), VERR_NO_MEMORY);
+ }
+ else
+ AssertLogRelMsgFailedReturn(("Configuration error: Failed to allocate memory for MMIO mapping!\n"), VERR_NO_MEMORY);
+ }
+ }
+
+ /*
+ * Attach the ICE driver and get the interfaces.
+ */
+ rc = PDMDevHlpDriverAttach(pDevIns, 0 /*iLUN*/, &pThis->IBase, &pThis->pDrvBase, "ICE");
+ if (RT_SUCCESS(rc))
+ {
+ pThis->pDrvIce = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIICE);
+ if (!pThis->pDrvIce)
+ {
+ AssertLogRelMsgFailed(("Configuration error: instance %d has no ICE interface!\n"));
+ return VERR_PDM_MISSING_INTERFACE;
+ }
+
+ /* Register the MSR intercetps if the driver below exposes the MSR read/write functionality. */
+ if (pThis->pDrvIce->pfnMsrRead || pThis->pDrvIce->pfnMsrWrite)
+ {
+ PVM pVM = PDMDevHlpGetVM(pDevIns);
+ rc = CPUMR3MsrRwInterceptSet(pVM, iceR3MsrRead, iceR3MsrWrite, pThis);
+ AssertMsgRC(rc, ("Configuration error: Setting the MSR read/write intercepts failed! rc=%Rrc\n", rc));
+ }
+ }
+ else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
+ {
+ pThis->pDrvBase = NULL;
+ pThis->pDrvIce = NULL;
+ rc = VINF_SUCCESS;
+ LogRel(("ICE#%d: no unit\n", iInstance));
+ }
+ else
+ {
+ AssertLogRelMsgFailed(("ICE: Failed to attach to ICE driver. rc=%Rrc\n", rc));
+ /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
+ return rc;
+ }
+
+
+ return rc;
+}
+
+
+/**
+ * The device registration structure.
+ */
+const PDMDEVREG g_DeviceIce =
+{
+ /* .u32Version = */ PDM_DEVREG_VERSION,
+ /* .uReserved0 = */ 0,
+ /* .szName = */ "ice",
+ /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_NEW_STYLE,
+ /* .fClass = */ PDM_DEVREG_CLASS_MISC,
+ /* .cMaxInstances = */ 1,
+ /* .uSharedVersion = */ 42,
+ /* .cbInstanceShared = */ sizeof(ICE),
+ /* .cbInstanceCC = */ 0,
+ /* .cbInstanceRC = */ 0,
+ /* .cMaxPciDevices = */ 0,
+ /* .cMaxMsixVectors = */ 0,
+ /* .pszDescription = */ "In-Circuit Emulator for hypervisor assisted x86 firmware debugging",
+#if defined(IN_RING3)
+ /* .pszRCMod = */ "",
+ /* .pszR0Mod = */ "",
+ /* .pfnConstruct = */ iceR3Construct,
+ /* .pfnDestruct = */ iceR3Destruct,
+ /* .pfnRelocate = */ NULL,
+ /* .pfnMemSetup = */ iceR3MemSetup,
+ /* .pfnPowerOn = */ NULL,
+ /* .pfnReset = */ NULL,
+ /* .pfnSuspend = */ NULL,
+ /* .pfnResume = */ NULL,
+ /* .pfnAttach = */ NULL,
+ /* .pfnDetach = */ NULL,
+ /* .pfnQueryInterface = */ NULL,
+ /* .pfnInitComplete = */ NULL,
+ /* .pfnPowerOff = */ NULL,
+ /* .pfnSoftReset = */ NULL,
+ /* .pfnReserved0 = */ NULL,
+ /* .pfnReserved1 = */ NULL,
+ /* .pfnReserved2 = */ NULL,
+ /* .pfnReserved3 = */ NULL,
+ /* .pfnReserved4 = */ NULL,
+ /* .pfnReserved5 = */ NULL,
+ /* .pfnReserved6 = */ NULL,
+ /* .pfnReserved7 = */ NULL,
+#elif defined(IN_RING0)
+ /* .pfnEarlyConstruct = */ NULL,
+ /* .pfnConstruct = */ NULL,
+ /* .pfnDestruct = */ NULL,
+ /* .pfnFinalDestruct = */ NULL,
+ /* .pfnRequest = */ NULL,
+ /* .pfnReserved0 = */ NULL,
+ /* .pfnReserved1 = */ NULL,
+ /* .pfnReserved2 = */ NULL,
+ /* .pfnReserved3 = */ NULL,
+ /* .pfnReserved4 = */ NULL,
+ /* .pfnReserved5 = */ NULL,
+ /* .pfnReserved6 = */ NULL,
+ /* .pfnReserved7 = */ NULL,
+#elif defined(IN_RC)
+ /* .pfnConstruct = */ NULL,
+ /* .pfnReserved0 = */ NULL,
+ /* .pfnReserved1 = */ NULL,
+ /* .pfnReserved2 = */ NULL,
+ /* .pfnReserved3 = */ NULL,
+ /* .pfnReserved4 = */ NULL,
+ /* .pfnReserved5 = */ NULL,
+ /* .pfnReserved6 = */ NULL,
+ /* .pfnReserved7 = */ NULL,
+#else
+# error "Not in IN_RING3, IN_RING0 or IN_RC!"
+#endif
+ /* .u32VersionEnd = */ PDM_DEVREG_VERSION
+};
+
Property changes on: src/VBox/Devices/Misc/DevIce.cpp
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Author Date Id Revision
\ No newline at end of property
Added: svn:sync-process
## -0,0 +1 ##
+export
\ No newline at end of property
Index: src/VBox/Devices/Misc/DrvSerialIce.cpp
===================================================================
--- src/VBox/Devices/Misc/DrvSerialIce.cpp (nicht existent)
+++ src/VBox/Devices/Misc/DrvSerialIce.cpp (Arbeitskopie)
@@ -0,0 +1,931 @@
+/* $Id$ */
+/** @file
+ * Driver for the ICE device speaking the serialICE (https://serialice.com) protocol.
+ */
+
+/*
+ * Copyright (C) 2020 Oracle Corporation
+ *
+ * This file is part of VirtualBox Open Source Edition (OSE), as
+ * available from http://www.virtualbox.org. This file is free software;
+ * you can redistribute it and/or modify it under the terms of the GNU
+ * General Public License (GPL) as published by the Free Software
+ * Foundation, in version 2 as it comes in the "COPYING" file of the
+ * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
+ * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
+ */
+
+
+/*********************************************************************************************************************************
+* Header Files *
+*********************************************************************************************************************************/
+#define LOG_GROUP LOG_GROUP_DRV_CHAR /** @todo */
+#include <VBox/vmm/pdmdrv.h>
+#include <VBox/vmm/pdmiceifs.h>
+#include <iprt/asm.h>
+#include <iprt/assert.h>
+#include <iprt/poll.h>
+#include <iprt/stream.h>
+#include <iprt/critsect.h>
+#include <iprt/semaphore.h>
+#include <iprt/uuid.h>
+#include <iprt/tcp.h>
+
+#include "VBoxDD.h"
+
+
+/*********************************************************************************************************************************
+* Defined Constants And Macros *
+*********************************************************************************************************************************/
+
+
+/*********************************************************************************************************************************
+* Structures and Typedefs *
+*********************************************************************************************************************************/
+
+/**
+ * The header for the binary transfer mode.
+ */
+typedef struct SERIALICEBINHDR
+{
+ /** Flags for the transfer. */
+ uint32_t fFlags;
+ /** Size of the transfer in bytes. */
+ uint32_t cbXfer;
+ /** The start address */
+ uint64_t u64AddrStart;
+} SERIALICEBINHDR;
+/** Pointer to a binary transfer header. */
+typedef SERIALICEBINHDR *PSERIALICEBINHDR;
+/** Pointer to a const binary transfer header. */
+typedef const SERIALICEBINHDR *PCSERIALICEBINHDR;
+
+/** Indicates a write request, read if cleared. */
+#define SERIALICE_BIN_REQ_HDR_F_WRITE RT_BIT(0)
+/** Indicates an I/O port access, memory access if clear. */
+#define SERIALICE_BIN_REQ_HDR_F_IOPORT RT_BIT(1)
+/** Indicates a a RAM memory access, MMIO or unknown if clear. */
+#define SERIALICE_BIN_REQ_HDR_F_MEM_RAM RT_BIT(2)
+/** Indicates a a MMIO memory access, RAM or unknown if clear. */
+#define SERIALICE_BIN_REQ_HDR_F_MEM_MMIO RT_BIT(3)
+
+
+/**
+ * SerialICE driver instance data.
+ *
+ * @implements PDMIICE
+ */
+typedef struct DRVSERIALICE
+{
+ /** Pointer to the driver instance structure. */
+ PPDMDRVINS pDrvIns;
+ /** Our ICE interface. */
+ PDMIICE IIce;
+
+ /** Where to connect to. */
+ char *pszLocation;
+ /** Socket handle of the TCP socket connection. */
+ RTSOCKET hTcpSock;
+
+ /** Flag whether the ICE target supports the extended protocol. */
+ bool fIceProtExtended;
+
+} DRVSERIALICE;
+/** Pointer to a serialICE driver instance. */
+typedef DRVSERIALICE *PDRVSERIALICE;
+
+
+static const uint8_t s_abHexToChr[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f' };
+
+
+/**
+ * Converts a hex character to the appropriate nibble.
+ *
+ * @returns Nibble of the character.
+ * @param bVal The value to convert.
+ */
+static inline uint8_t drvSerialIceHexToNibble(uint8_t bVal)
+{
+ if (bVal >= '0' && bVal <= '9')
+ return bVal - '0';
+ else if (bVal >= 'a' && bVal <= 'f')
+ return bVal - 'a' + 10;
+ else if (bVal >= 'A' && bVal <= 'F')
+ return bVal - 'A' + 10;
+
+ return 0xff;
+}
+
+
+/**
+ * Parse a ASCII 32bit value hexadecimal value and return the binary representation.
+ *
+ * @returns VBox status code.
+ * @param pbSrc The data to parse.
+ * @param pu32Val Where to return the value on success.
+ */
+static int drvSerialIceParseU32(uint8_t *pbSrc, uint32_t *pu32Val)
+{
+ int rc = VINF_SUCCESS;
+ *pu32Val = 0;
+
+ const uint8_t *pbData = &pbSrc[(sizeof(uint32_t) * 2) - 2];
+ for (uint32_t i = 0; i < sizeof(uint32_t) && RT_SUCCESS(rc); i++)
+ {
+ *pu32Val <<= 8;
+ uint8_t bNbH = drvSerialIceHexToNibble(pbData[0]);
+ uint8_t bNbL = drvSerialIceHexToNibble(pbData[1]);
+ if (bNbH != 0xff && bNbL != 0xff)
+ *pu32Val |= (bNbH << 4) | bNbL;
+ else
+ rc = VERR_NET_PROTOCOL_ERROR;
+ }
+
+ return rc;
+}
+
+
+/**
+ * Parse a ASCII 16bit value hexadecimal value and return the binary representation.
+ *
+ * @returns VBox status code.
+ * @param pbSrc The data to parse.
+ * @param pu16Val Where to return the value on success.