|
300 | 300 | }; |
301 | 301 |
|
302 | 302 | &gpio4 { |
| 303 | + pinctrl-names = "default"; |
| 304 | + pinctrl-0 = <&pinctrl_gpio4>; |
303 | 305 | gpio-line-names = "", "", "BRIDGE_RXD0", "BRIDGE_RXD1", "S_BRIDGE_RXD2", "S_BRIDGE_RXD3", "", "", |
304 | 306 | "", "", "BRIDGE_LRCLK", "BRIDGE_BCLK", "BRIDGE_TXD0", "BRIDGE_TXD1", "S_BRIDGE_TXD2", "S_BRIDGE_TXD3", |
305 | 307 | "", "", "", "", "", "", "", "", |
306 | 308 | "", "", "", "", "HP_DAC_PDN_N", "SPI2_INT", "HP_DAC_I2CFIL", "DPM_HP_DAC_LRCK"; |
307 | 309 | }; |
308 | 310 |
|
309 | 311 | &gpio5 { |
| 312 | + pinctrl-names = "default"; |
| 313 | + pinctrl-0 = <&pinctrl_gpio5>; |
310 | 314 | gpio-line-names = "DPM_HP_DAC_BCLK", "DPM_HP_DAC_SD", "DPM_HP_DAC_MCLK", "", "", "PWM_MEMBRANE", "", "", |
311 | 315 | "", "", "SPI2_SCK", "SPI2_MOSI", "SPI2_MISO", "SPI2_NSS", "", "", |
312 | 316 | "DPM_I2C2_SCL", "DPM_I2C2_SDA", "", "", "DPM_I2C4_SCL", "DPM_I2C4_SDA", "", "", |
|
323 | 327 | status = "okay"; |
324 | 328 | }; |
325 | 329 |
|
326 | | -&sai3 { |
327 | | - pinctrl-names = "default"; |
328 | | - pinctrl-0 = <&pinctrl_sai3>; |
329 | | - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; |
330 | | - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; |
331 | | - assigned-clock-rates = <24576000>; |
332 | | - status = "okay"; |
333 | | -}; |
334 | | - |
335 | 330 | &snvs_pwrkey { |
336 | 331 | status = "okay"; |
337 | 332 | }; |
|
528 | 523 | >; |
529 | 524 | }; |
530 | 525 |
|
531 | | - pinctrl_sai3: sai3grp { |
| 526 | + pinctrl_gpio4: gpio4grp { |
532 | 527 | fsl,pins = < |
533 | | - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 |
534 | | - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 |
535 | | - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 |
536 | | - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 |
537 | 528 | MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x06 /* HP_DAC_PDN */ |
538 | 529 | MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x06 /* HP_DAC_I2C_FIL */ |
| 530 | + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x26 /* DPM_HP_DAC_LRCK */ |
| 531 | + >; |
| 532 | + }; |
| 533 | + |
| 534 | + pinctrl_gpio5: gpio5grp { |
| 535 | + fsl,pins = < |
| 536 | + MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x26 /* DANTE_OSC_BICK */ |
| 537 | + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x26 /* DANTE_OSC_MCLK */ |
| 538 | + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x06 /* DPM_HP_DAC_SD */ |
539 | 539 | >; |
540 | 540 | }; |
541 | 541 |
|
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